KR20070032649A - 실리콘을 갖는 스트레인드 Ｓｉ／ＳｉＧｅ 온 절연체를형성하는 방법 - Google Patents

실리콘을 갖는 스트레인드 Ｓｉ／ＳｉＧｅ 온 절연체를형성하는 방법 Download PDF

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Publication number
KR20070032649A
KR20070032649A KR1020067023687A KR20067023687A KR20070032649A KR 20070032649 A KR20070032649 A KR 20070032649A KR 1020067023687 A KR1020067023687 A KR 1020067023687A KR 20067023687 A KR20067023687 A KR 20067023687A KR 20070032649 A KR20070032649 A KR 20070032649A
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South Korea
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layer
strained
forming
sige
relaxed
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Ceased
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KR1020067023687A
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English (en)
Korean (ko)
Inventor
휴아지에 첸
스테반 더블유 베델
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR20070032649A publication Critical patent/KR20070032649A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
KR1020067023687A 2004-06-29 2005-02-16 실리콘을 갖는 스트레인드 Ｓｉ／ＳｉＧｅ 온 절연체를형성하는 방법 Ceased KR20070032649A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/710,255 2004-06-29
US10/710,255 US6893936B1 (en) 2004-06-29 2004-06-29 Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
PCT/US2005/005085 WO2006011912A1 (en) 2004-06-29 2005-02-16 Method of forming strained si/sige on insulator with silicon germanium buffer

Publications (1)

Publication Number Publication Date
KR20070032649A true KR20070032649A (ko) 2007-03-22

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KR1020067023687A Ceased KR20070032649A (ko) 2004-06-29 2005-02-16 실리콘을 갖는 스트레인드 Ｓｉ／ＳｉＧｅ 온 절연체를형성하는 방법

Country Status (7)

Country Link
US (1) US6893936B1 (enExample)
EP (1) EP1779422A4 (enExample)
JP (1) JP2008505482A (enExample)
KR (1) KR20070032649A (enExample)
CN (1) CN1954421A (enExample)
TW (1) TWI348200B (enExample)
WO (1) WO2006011912A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101381056B1 (ko) * 2012-11-29 2014-04-14 주식회사 시지트로닉스 Ⅲ-질화계 에피층이 성장된 반도체 기판 및 그 방법
KR20150110377A (ko) * 2014-03-20 2015-10-02 삼성전자주식회사 스트레인 완화 방법 및 이를 이용한 스트레인-완화 반도체층 및 반도체 소자 의 형성 방법 및 관련된 반도체 구조물

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GB9618897D0 (en) 1996-09-10 1996-10-23 Bio Rad Micromeasurements Ltd Micro defects in silicon wafers
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
GB0308182D0 (en) * 2003-04-09 2003-05-14 Aoti Operating Co Inc Detection method and apparatus
US7259084B2 (en) * 2003-07-28 2007-08-21 National Chiao-Tung University Growth of GaAs epitaxial layers on Si substrate by using a novel GeSi buffer layer
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
DE102004062290A1 (de) * 2004-12-23 2006-07-06 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterchips
US20070000434A1 (en) * 2005-06-30 2007-01-04 Accent Optical Technologies, Inc. Apparatuses and methods for detecting defects in semiconductor workpieces
US20070010070A1 (en) * 2005-07-05 2007-01-11 International Business Machines Corporation Fabrication of strained semiconductor-on-insulator (ssoi) structures by using strained insulating layers
TWI391645B (zh) * 2005-07-06 2013-04-01 Nanometrics Inc 晶圓或其他工作表面下污染物及缺陷非接觸測量之差分波長光致發光
TWI439684B (zh) * 2005-07-06 2014-06-01 Nanometrics Inc 具自晶圓或其他工件特定材料層所發射光致發光信號優先偵測之光致發光成像
US20070008526A1 (en) * 2005-07-08 2007-01-11 Andrzej Buczkowski Apparatus and method for non-contact assessment of a constituent in semiconductor workpieces
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
DE102005051332B4 (de) * 2005-10-25 2007-08-30 Infineon Technologies Ag Halbleitersubstrat, Halbleiterchip, Halbleiterbauteil und Verfahren zur Herstellung eines Halbleiterbauteils
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
US7656049B2 (en) 2005-12-22 2010-02-02 Micron Technology, Inc. CMOS device with asymmetric gate strain
US20070176119A1 (en) * 2006-01-30 2007-08-02 Accent Optical Technologies, Inc. Apparatuses and methods for analyzing semiconductor workpieces
US7494856B2 (en) * 2006-03-30 2009-02-24 Freescale Semiconductor, Inc. Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
DE102006019934B4 (de) * 2006-04-28 2009-10-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Ausbildung eines Feldeffekttransistors
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
CN100447950C (zh) * 2007-01-26 2008-12-31 厦门大学 低位错密度锗硅虚衬底的制备方法
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
KR20120049899A (ko) 2009-09-04 2012-05-17 스미또모 가가꾸 가부시키가이샤 반도체 기판, 전계 효과 트랜지스터, 집적 회로 및 반도체 기판의 제조 방법
CN101882624B (zh) * 2010-06-29 2011-09-14 清华大学 在绝缘衬底上形成有高Ge应变层的结构及形成方法
CN102315246B (zh) * 2010-06-30 2013-03-13 中国科学院上海硅酸盐研究所 一种弛豫SiGe虚拟衬底及其制备方法
KR20140071353A (ko) * 2011-08-01 2014-06-11 바스프 에스이 pH 값이 3.0 내지 5.5 인 화학적 기계적 연마 조성물의 존재시의 원소 게르마늄 및/또는 Si₁­ｘGeｘ 재료의 화학적 기계적 연마를 포함하는 반도체 디바이스들의 제조 방법
CN102427068B (zh) * 2011-12-02 2014-06-18 中国科学院上海微系统与信息技术研究所 单片集成具有晶格失配的晶体模板及其制作方法
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
CN103165511B (zh) * 2011-12-14 2015-07-22 中国科学院上海微系统与信息技术研究所 一种制备goi的方法
TWI457985B (zh) * 2011-12-22 2014-10-21 Nat Inst Chung Shan Science & Technology Semiconductor structure with stress absorbing buffer layer and manufacturing method thereof
US8518807B1 (en) * 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
US9716176B2 (en) * 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
WO2016109502A1 (en) * 2014-12-31 2016-07-07 Sunedison Semiconductor Limited Preparation of silicon-germanium-on-insulator structures
KR102257423B1 (ko) 2015-01-23 2021-05-31 삼성전자주식회사 반도체 기판 및 이를 포함하는 반도체 장치
CN107667416B (zh) * 2015-06-01 2021-08-31 环球晶圆股份有限公司 制造绝缘体上半导体的方法
CN114000121B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于mbe法的应变金刚石生长掺杂方法及外延结构
CN114000120B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于cvd法的应变金刚石生长掺杂方法
JP2025168976A (ja) * 2024-04-30 2025-11-12 信越半導体株式会社 ＳｉＧｅ基板の作製方法及びＳｉＧｅ基板

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FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101381056B1 (ko) * 2012-11-29 2014-04-14 주식회사 시지트로닉스 Ⅲ-질화계 에피층이 성장된 반도체 기판 및 그 방법
KR20150110377A (ko) * 2014-03-20 2015-10-02 삼성전자주식회사 스트레인 완화 방법 및 이를 이용한 스트레인-완화 반도체층 및 반도체 소자 의 형성 방법 및 관련된 반도체 구조물

Also Published As

Publication number Publication date
EP1779422A1 (en) 2007-05-02
EP1779422A4 (en) 2007-08-01
TW200601420A (en) 2006-01-01
WO2006011912A1 (en) 2006-02-02
US6893936B1 (en) 2005-05-17
JP2008505482A (ja) 2008-02-21
CN1954421A (zh) 2007-04-25
TWI348200B (en) 2011-09-01

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