JP2008505482A - シリコン・ゲルマニウム・バッファで絶縁体上に歪みＳｉ／ＳｉＧｅを形成する方法 - Google Patents

シリコン・ゲルマニウム・バッファで絶縁体上に歪みＳｉ／ＳｉＧｅを形成する方法 Download PDF

Info

Publication number
JP2008505482A
JP2008505482A JP2007519189A JP2007519189A JP2008505482A JP 2008505482 A JP2008505482 A JP 2008505482A JP 2007519189 A JP2007519189 A JP 2007519189A JP 2007519189 A JP2007519189 A JP 2007519189A JP 2008505482 A JP2008505482 A JP 2008505482A
Authority
JP
Japan
Prior art keywords
layer
sige
strained
relaxed
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007519189A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008505482A5 (enExample
Inventor
チャン、フージエ
ベデル、スティーヴン、ダブリュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2008505482A publication Critical patent/JP2008505482A/ja
Publication of JP2008505482A5 publication Critical patent/JP2008505482A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H10P90/1916—
    • H10P14/20—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10W10/181—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2007519189A 2004-06-29 2005-02-16 シリコン・ゲルマニウム・バッファで絶縁体上に歪みＳｉ／ＳｉＧｅを形成する方法 Pending JP2008505482A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/710,255 US6893936B1 (en) 2004-06-29 2004-06-29 Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
PCT/US2005/005085 WO2006011912A1 (en) 2004-06-29 2005-02-16 Method of forming strained si/sige on insulator with silicon germanium buffer

Publications (2)

Publication Number Publication Date
JP2008505482A true JP2008505482A (ja) 2008-02-21
JP2008505482A5 JP2008505482A5 (enExample) 2008-04-03

Family

ID=34573464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007519189A Pending JP2008505482A (ja) 2004-06-29 2005-02-16 シリコン・ゲルマニウム・バッファで絶縁体上に歪みＳｉ／ＳｉＧｅを形成する方法

Country Status (7)

Country Link
US (1) US6893936B1 (enExample)
EP (1) EP1779422A4 (enExample)
JP (1) JP2008505482A (enExample)
KR (1) KR20070032649A (enExample)
CN (1) CN1954421A (enExample)
TW (1) TWI348200B (enExample)
WO (1) WO2006011912A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009504392A (ja) * 2005-08-16 2009-02-05 コミサリヤ・ア・レネルジ・アトミク 支持体上に薄膜を転写する方法
JP2015103814A (ja) * 2013-11-26 2015-06-04 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． ｆｉｎＦＥＴ半導体素子及びその製造方法
US9112035B2 (en) 2009-09-04 2015-08-18 Sumitomo Chemical Company, Limited Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate
WO2025229832A1 (ja) * 2024-04-30 2025-11-06 信越半導体株式会社 ＳｉＧｅ基板の作製方法及びＳｉＧｅ基板

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9618897D0 (en) 1996-09-10 1996-10-23 Bio Rad Micromeasurements Ltd Micro defects in silicon wafers
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
GB0308182D0 (en) * 2003-04-09 2003-05-14 Aoti Operating Co Inc Detection method and apparatus
US7259084B2 (en) * 2003-07-28 2007-08-21 National Chiao-Tung University Growth of GaAs epitaxial layers on Si substrate by using a novel GeSi buffer layer
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
DE102004062290A1 (de) * 2004-12-23 2006-07-06 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterchips
US20070000434A1 (en) * 2005-06-30 2007-01-04 Accent Optical Technologies, Inc. Apparatuses and methods for detecting defects in semiconductor workpieces
US20070010070A1 (en) * 2005-07-05 2007-01-11 International Business Machines Corporation Fabrication of strained semiconductor-on-insulator (ssoi) structures by using strained insulating layers
TWI391645B (zh) * 2005-07-06 2013-04-01 Nanometrics Inc 晶圓或其他工作表面下污染物及缺陷非接觸測量之差分波長光致發光
TWI439684B (zh) * 2005-07-06 2014-06-01 Nanometrics Inc 具自晶圓或其他工件特定材料層所發射光致發光信號優先偵測之光致發光成像
US20070008526A1 (en) * 2005-07-08 2007-01-11 Andrzej Buczkowski Apparatus and method for non-contact assessment of a constituent in semiconductor workpieces
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
DE102005051332B4 (de) * 2005-10-25 2007-08-30 Infineon Technologies Ag Halbleitersubstrat, Halbleiterchip, Halbleiterbauteil und Verfahren zur Herstellung eines Halbleiterbauteils
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
US7656049B2 (en) * 2005-12-22 2010-02-02 Micron Technology, Inc. CMOS device with asymmetric gate strain
US20070176119A1 (en) * 2006-01-30 2007-08-02 Accent Optical Technologies, Inc. Apparatuses and methods for analyzing semiconductor workpieces
US7494856B2 (en) * 2006-03-30 2009-02-24 Freescale Semiconductor, Inc. Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
DE102006019934B4 (de) 2006-04-28 2009-10-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Ausbildung eines Feldeffekttransistors
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
CN100447950C (zh) * 2007-01-26 2008-12-31 厦门大学 低位错密度锗硅虚衬底的制备方法
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
CN101882624B (zh) * 2010-06-29 2011-09-14 清华大学 在绝缘衬底上形成有高Ge应变层的结构及形成方法
CN102315246B (zh) * 2010-06-30 2013-03-13 中国科学院上海硅酸盐研究所 一种弛豫SiGe虚拟衬底及其制备方法
EP2741892A4 (en) * 2011-08-01 2015-03-18 Basf Se METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS WITH CHEMICAL-MECHANICAL POLISHING ELEMENTARY GERMANIUM AND / OR SI1-XGEX MATERIALS IN THE PRESENCE OF A CMP COMPOSITION OF A PH BETWEEN 3.0 AND 5.5
CN102427068B (zh) * 2011-12-02 2014-06-18 中国科学院上海微系统与信息技术研究所 单片集成具有晶格失配的晶体模板及其制作方法
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
CN103165511B (zh) * 2011-12-14 2015-07-22 中国科学院上海微系统与信息技术研究所 一种制备goi的方法
TWI457985B (zh) * 2011-12-22 2014-10-21 Nat Inst Chung Shan Science & Technology Semiconductor structure with stress absorbing buffer layer and manufacturing method thereof
US8518807B1 (en) * 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
KR101381056B1 (ko) * 2012-11-29 2014-04-14 주식회사 시지트로닉스 Ⅲ-질화계 에피층이 성장된 반도체 기판 및 그 방법
US9343303B2 (en) * 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
WO2016109502A1 (en) * 2014-12-31 2016-07-07 Sunedison Semiconductor Limited Preparation of silicon-germanium-on-insulator structures
KR102257423B1 (ko) 2015-01-23 2021-05-31 삼성전자주식회사 반도체 기판 및 이를 포함하는 반도체 장치
US10304722B2 (en) 2015-06-01 2019-05-28 Globalwafers Co., Ltd. Method of manufacturing semiconductor-on-insulator
CN114000120B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于cvd法的应变金刚石生长掺杂方法
CN114000121B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于mbe法的应变金刚石生长掺杂方法及外延结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004006327A2 (en) * 2002-07-09 2004-01-15 S.O.I. Tec Silicon On Insulator Technologies Transfer of a thin layer from a wafer comprising a buffer layer
WO2004027858A1 (en) * 2002-09-18 2004-04-01 S.O.I.Tec Silicon On Insulator Technologies Formation of a relaxed useful layer from a wafer with no buffer layer
JP2004510350A (ja) * 2000-09-29 2004-04-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 絶縁体上への緩和ＳｉＧｅ層の作製

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US6633066B1 (en) * 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
EP1309989B1 (en) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
US6603156B2 (en) 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US6812116B2 (en) * 2002-12-13 2004-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004510350A (ja) * 2000-09-29 2004-04-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 絶縁体上への緩和ＳｉＧｅ層の作製
WO2004006327A2 (en) * 2002-07-09 2004-01-15 S.O.I. Tec Silicon On Insulator Technologies Transfer of a thin layer from a wafer comprising a buffer layer
WO2004027858A1 (en) * 2002-09-18 2004-04-01 S.O.I.Tec Silicon On Insulator Technologies Formation of a relaxed useful layer from a wafer with no buffer layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009504392A (ja) * 2005-08-16 2009-02-05 コミサリヤ・ア・レネルジ・アトミク 支持体上に薄膜を転写する方法
US9112035B2 (en) 2009-09-04 2015-08-18 Sumitomo Chemical Company, Limited Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate
JP2015103814A (ja) * 2013-11-26 2015-06-04 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． ｆｉｎＦＥＴ半導体素子及びその製造方法
WO2025229832A1 (ja) * 2024-04-30 2025-11-06 信越半導体株式会社 ＳｉＧｅ基板の作製方法及びＳｉＧｅ基板

Also Published As

Publication number Publication date
TWI348200B (en) 2011-09-01
US6893936B1 (en) 2005-05-17
KR20070032649A (ko) 2007-03-22
WO2006011912A1 (en) 2006-02-02
CN1954421A (zh) 2007-04-25
EP1779422A1 (en) 2007-05-02
EP1779422A4 (en) 2007-08-01
TW200601420A (en) 2006-01-01

Similar Documents

Publication Publication Date Title
US6893936B1 (en) Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
US6992025B2 (en) Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
JP4906727B2 (ja) ウェハ接合技術を用いて欠陥のない高Ｇｅ含有量のＳｉＧｅオン・インシュレータ（ＳＧＯＩ）基板を製造する方法
US10510581B2 (en) Methods of forming strained-semiconductor-on-insulator device structures
US6717213B2 (en) Creation of high mobility channels in thin-body SOI devices
TWI225283B (en) Strained semiconductor on insulator substrate and method of forming the same
CA2501580C (en) Method of forming strained silicon on insulator (ssoi) and structures formed thereby
US6995430B2 (en) Strained-semiconductor-on-insulator device structures
JP5259954B2 (ja) 基板上に歪層を製造する方法と層構造
US7897480B2 (en) Preparation of high quality strained-semiconductor directly-on-insulator substrates
JP2010016390A (ja) グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
JP2006524426A5 (enExample)
US20030160300A1 (en) Semiconductor substrate, method of manufacturing the same and semiconductor device
US20070117350A1 (en) Strained silicon on insulator (ssoi) with layer transfer from oxidized donor
US20050070070A1 (en) Method of forming strained silicon on insulator

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080129

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110829

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110927

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111129

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20111129

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20111201

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120228

RD14 Notification of resignation of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7434

Effective date: 20120530