KR20070008599A - 레벨내 용량이 저감된 집적 회로의 배선 구조 - Google Patents

레벨내 용량이 저감된 집적 회로의 배선 구조 Download PDF

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Publication number
KR20070008599A
KR20070008599A KR1020067019469A KR20067019469A KR20070008599A KR 20070008599 A KR20070008599 A KR 20070008599A KR 1020067019469 A KR1020067019469 A KR 1020067019469A KR 20067019469 A KR20067019469 A KR 20067019469A KR 20070008599 A KR20070008599 A KR 20070008599A
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KR
South Korea
Prior art keywords
dielectric layer
dielectric
layer
air gap
conductors
Prior art date
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Ceased
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KR1020067019469A
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English (en)
Korean (ko)
Inventor
리차드 에스. 와이즈
보마이 에이. 첸
마르크 씨. 해케이
홍웬 얀
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR20070008599A publication Critical patent/KR20070008599A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020067019469A 2004-04-21 2005-04-21 레벨내 용량이 저감된 집적 회로의 배선 구조 Ceased KR20070008599A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/709,204 US20050239284A1 (en) 2004-04-21 2004-04-21 Wiring structure for integrated circuit with reduced intralevel capacitance
US10/709,204 2004-04-21

Publications (1)

Publication Number Publication Date
KR20070008599A true KR20070008599A (ko) 2007-01-17

Family

ID=35137032

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067019469A Ceased KR20070008599A (ko) 2004-04-21 2005-04-21 레벨내 용량이 저감된 집적 회로의 배선 구조

Country Status (9)

Country Link
US (2) US20050239284A1 (https=)
EP (1) EP1743366B1 (https=)
JP (1) JP5305651B2 (https=)
KR (1) KR20070008599A (https=)
CN (1) CN1943023B (https=)
AT (1) ATE504079T1 (https=)
DE (1) DE602005027195D1 (https=)
TW (1) TW200539281A (https=)
WO (1) WO2005104212A2 (https=)

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Publication number Priority date Publication date Assignee Title
CN101471324B (zh) * 2007-12-26 2010-07-07 和舰科技(苏州)有限公司 一种超低k互连结构及其制造方法
US8497203B2 (en) 2010-08-13 2013-07-30 International Business Machines Corporation Semiconductor structures and methods of manufacture
US8492270B2 (en) 2010-09-20 2013-07-23 International Business Machines Corporation Structure for nano-scale metallization and method for fabricating same
US8957519B2 (en) 2010-10-22 2015-02-17 International Business Machines Corporation Structure and metallization process for advanced technology nodes
US8735279B2 (en) 2011-01-25 2014-05-27 International Business Machines Corporation Air-dielectric for subtractive etch line and via metallization
CN103094183B (zh) * 2011-10-29 2015-07-29 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN103117244B (zh) * 2011-11-16 2015-04-01 中芯国际集成电路制造(上海)有限公司 Ic内连线和层间介质层之间的空气间隔形成方法
CN102931127A (zh) * 2012-10-10 2013-02-13 哈尔滨工程大学 一种抗辐射加固浅槽隔离结构形成方法
US9431294B2 (en) * 2014-10-28 2016-08-30 GlobalFoundries, Inc. Methods of producing integrated circuits with an air gap
US10770539B2 (en) * 2018-09-25 2020-09-08 Nxp B.V. Fingered capacitor with low-K and ultra-low-K dielectric layers
US11094632B2 (en) * 2019-09-27 2021-08-17 Nanya Technology Corporation Semiconductor device with air gap and method for preparing the same
WO2022006010A1 (en) * 2020-06-30 2022-01-06 Lam Research Corporation Reducing intralevel capacitance in semiconductor devices

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US5372969A (en) * 1991-12-31 1994-12-13 Texas Instruments Incorporated Low-RC multi-level interconnect technology for high-performance integrated circuits
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5792706A (en) * 1996-06-05 1998-08-11 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to reduce permitivity
US5783481A (en) * 1996-06-05 1998-07-21 Advanced Micro Devices, Inc. Semiconductor interlevel dielectric having a polymide for producing air gaps
US5880026A (en) * 1996-12-23 1999-03-09 Texas Instruments Incorporated Method for air gap formation by plasma treatment of aluminum interconnects
JP2962272B2 (ja) * 1997-04-18 1999-10-12 日本電気株式会社 半導体装置の製造方法
US6242336B1 (en) * 1997-11-06 2001-06-05 Matsushita Electronics Corporation Semiconductor device having multilevel interconnection structure and method for fabricating the same
US6211561B1 (en) * 1998-11-16 2001-04-03 Conexant Systems, Inc. Interconnect structure and method employing air gaps between metal lines and between metal layers
JP4134405B2 (ja) * 1998-11-20 2008-08-20 沖電気工業株式会社 半導体素子の製造方法及び半導体素子
TW411570B (en) * 1999-02-02 2000-11-11 Nanya Technology Corp Manufacturing method of self-aligned contact
US6177329B1 (en) * 1999-04-15 2001-01-23 Kurt Pang Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets
US6342722B1 (en) * 1999-08-05 2002-01-29 International Business Machines Corporation Integrated circuit having air gaps between dielectric and conducting lines
GB0001179D0 (en) * 2000-01-19 2000-03-08 Trikon Holdings Ltd Methods & apparatus for forming a film on a substrate
TW444342B (en) * 2000-02-17 2001-07-01 United Microelectronics Corp Manufacturing method of metal interconnect having inner gap spacer
TW465039B (en) * 2000-11-06 2001-11-21 United Microelectronics Corp Void-type metal interconnect and method for making the same
US6380106B1 (en) * 2000-11-27 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures
US6936533B2 (en) * 2000-12-08 2005-08-30 Samsung Electronics, Co., Ltd. Method of fabricating semiconductor devices having low dielectric interlayer insulation layer
US6448177B1 (en) * 2001-03-27 2002-09-10 Intle Corporation Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
KR100460771B1 (ko) * 2001-06-30 2004-12-09 주식회사 하이닉스반도체 듀얼다마신 공정에 의한 다층 배선의 형성 방법
JP2003163266A (ja) * 2001-11-28 2003-06-06 Sony Corp 半導体装置の製造方法および半導体装置
US6806534B2 (en) * 2003-01-14 2004-10-19 International Business Machines Corporation Damascene method for improved MOS transistor

Also Published As

Publication number Publication date
ATE504079T1 (de) 2011-04-15
JP5305651B2 (ja) 2013-10-02
CN1943023A (zh) 2007-04-04
JP2007534178A (ja) 2007-11-22
US20050239284A1 (en) 2005-10-27
WO2005104212A3 (en) 2006-07-20
WO2005104212A2 (en) 2005-11-03
CN1943023B (zh) 2010-09-29
US7329602B2 (en) 2008-02-12
EP1743366A4 (en) 2009-11-11
DE602005027195D1 (de) 2011-05-12
EP1743366A2 (en) 2007-01-17
US20060035460A1 (en) 2006-02-16
TW200539281A (en) 2005-12-01
EP1743366B1 (en) 2011-03-30

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