KR20060120664A - 능동적 보호 회로 장치 - Google Patents
능동적 보호 회로 장치 Download PDFInfo
- Publication number
- KR20060120664A KR20060120664A KR1020067007574A KR20067007574A KR20060120664A KR 20060120664 A KR20060120664 A KR 20060120664A KR 1020067007574 A KR1020067007574 A KR 1020067007574A KR 20067007574 A KR20067007574 A KR 20067007574A KR 20060120664 A KR20060120664 A KR 20060120664A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit arrangement
- inverter
- vdd
- resistors
- vss
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 239000006185 dispersion Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000001960 triggered effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 206010067484 Adverse reaction Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000006838 adverse reaction Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (7)
- 집적 반도체 회로들을 전기 펄스 또는 전기 과전압에 대해서 보호하기 위한 회로 장치이며,상기 장치는 제1 저항(R1; R10) 및 커패시터(C1; C10)로 이루어지며 2개의 공급 전위 라인들(VDD, VSS) 사이에 접속된 RC-소자와,직렬 접속된 인버터들(I10 내지 I12)로 이루어지고 입력측이 제1 저항(R1; R10)과 커패시터(C1; C10)의 연결점에 연결되는 체인과,그 제어 입력부가 인버터 체인의 출력부에 연결되고 출력측에서 2개의 공급 전위 라인들(VDD, VSS)에 연결되는 보호 트랜지스터(ST)를 갖는 회로 장치에 있어서,상기 인버터(I10 - I12)들의 서로간의, 또한 보호 트랜지스터(ST)와의 연결점들은 각각 하나의 저항(R11, R12, R13)에 연결되며, 상기 저항들의 각각의 다른 연결부는 하나의 공급 전위 라인들(VDD, VSS)에 연결되는 것을 특징으로 하는 회로 장치.
- 제1항에 있어서, 상기 저항들은 공급 전위 라인들(VDD, VSS)의 각각 하나에 교대로 연결되는 것을 특징으로 하는 회로 장치.
- 제1항 또는 제2항에 있어서, 인버터 체인의 마지막 인버터(I12)의 입력부는 저항들 중 하나의 저항(R11)에 의해서 하나의 공급 전위 라인(VDD)에 연결되며, 상기 인버터 체인의 마지막 인버터(I12)의 출력부는 상기 저항들 중 다른 하나의 저항(R12)에 의해서 다른 공급 전위 라인(VSS)에 연결되고 보호 트랜지스터(ST)의 제어 입력부에 연결되는 것을 특징으로 하는 회로 장치.
- 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 인버터는 CMOS-인버터(P11, N11; P12, N12; P13, N13)으로서 형성되는 것을 특징으로 하는 회로 장치.
- 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 저항들은 분산 저항들로서 구현되는 것을 특징으로 하는 회로 장치.
- 제1항 내지 제5항 중 어느 한 항에 있어서, 상기 제1 저항(R10)은 분산 저항인 것을 특징으로 하는 회로 장치.
- 제1항 내지 제6항 중 어느 한 항에 있어서, 상기 커패시터(C1; C10)는 산화물 커패시터인 것을 특징으로 하는 회로 장치.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10349405.7 | 2003-10-21 | ||
DE10349405A DE10349405A1 (de) | 2003-10-21 | 2003-10-21 | Aktive Schutzschaltungsanordnung |
PCT/EP2004/011925 WO2005041375A2 (de) | 2003-10-21 | 2004-10-21 | Aktive schutzschaltungsanordnung |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20060120664A true KR20060120664A (ko) | 2006-11-27 |
KR101089469B1 KR101089469B1 (ko) | 2011-12-07 |
Family
ID=34484955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020067007574A KR101089469B1 (ko) | 2003-10-21 | 2004-10-21 | 능동적 보호 회로 장치 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7423855B2 (ko) |
EP (1) | EP1676350B1 (ko) |
JP (1) | JP4723505B2 (ko) |
KR (1) | KR101089469B1 (ko) |
DE (2) | DE10349405A1 (ko) |
WO (1) | WO2005041375A2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101389234B1 (ko) * | 2007-10-30 | 2014-04-24 | 에이저 시스템즈 엘엘시 | 정전기 방전 보호 회로 |
Families Citing this family (18)
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JP4942007B2 (ja) * | 2004-10-25 | 2012-05-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP4712451B2 (ja) * | 2005-06-13 | 2011-06-29 | Hoya株式会社 | 電圧固定用回路 |
KR100651579B1 (ko) * | 2005-11-15 | 2006-11-29 | 매그나칩 반도체 유한회사 | 이에스디 보호회로 |
WO2009023099A2 (en) * | 2007-08-10 | 2009-02-19 | Skyworks Solutions, Inc. | Power clamp for on-chip esd protection |
DE102007042103A1 (de) | 2007-09-05 | 2009-03-26 | Austriamicrosystems Ag | Schaltungsanordnung zum Schutz vor elektrostatischen Entladungen und Verfahren zur Ableitung von elektrostatischen Entladungen |
US7881028B2 (en) * | 2008-03-04 | 2011-02-01 | International Business Machines Corporation | E-fuse used to disable a triggering network |
US7969699B2 (en) * | 2008-08-05 | 2011-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection trigger circuit |
US8339756B2 (en) * | 2009-12-17 | 2012-12-25 | Intel Corporation | Control circuit having a delay-reduced inverter |
US8369054B2 (en) * | 2010-06-08 | 2013-02-05 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | NMOS-based feedback power-clamp for on-chip ESD protection |
EP2405236B1 (de) | 2010-07-07 | 2012-10-31 | Leica Geosystems AG | Geodätisches Vermessungsgerät mit automatischer hochpräziser Zielpunkt-Anzielfunktionalität |
JP5656658B2 (ja) * | 2011-01-14 | 2015-01-21 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置 |
CN102723702A (zh) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | 一种用于片上静电释放保护的双反馈的电源钳位 |
US9112351B2 (en) * | 2013-02-05 | 2015-08-18 | Freescale Semiconductor Inc. | Electrostatic discharge circuit |
CN103515944B (zh) * | 2013-10-14 | 2017-03-29 | 辽宁大学 | 采用双通道技术的用于电源和地之间ESD保护的Power Clamp |
JP6342305B2 (ja) * | 2014-11-12 | 2018-06-13 | 株式会社メガチップス | Esd保護回路 |
DE102020104129A1 (de) * | 2019-05-03 | 2020-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Logikpufferschaltung und verfahren |
US10979049B2 (en) * | 2019-05-03 | 2021-04-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Logic buffer circuit and method |
CN112350709B (zh) * | 2020-11-03 | 2023-08-11 | 中国北方发动机研究所(天津) | 一种多保护电流输入接口电路 |
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-
2003
- 2003-10-21 DE DE10349405A patent/DE10349405A1/de not_active Ceased
-
2004
- 2004-10-21 KR KR1020067007574A patent/KR101089469B1/ko active IP Right Grant
- 2004-10-21 WO PCT/EP2004/011925 patent/WO2005041375A2/de active Application Filing
- 2004-10-21 DE DE502004010498T patent/DE502004010498D1/de active Active
- 2004-10-21 EP EP04790726A patent/EP1676350B1/de active Active
- 2004-10-21 US US10/576,104 patent/US7423855B2/en active Active
- 2004-10-21 JP JP2006536049A patent/JP4723505B2/ja active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101389234B1 (ko) * | 2007-10-30 | 2014-04-24 | 에이저 시스템즈 엘엘시 | 정전기 방전 보호 회로 |
Also Published As
Publication number | Publication date |
---|---|
JP4723505B2 (ja) | 2011-07-13 |
KR101089469B1 (ko) | 2011-12-07 |
EP1676350A2 (de) | 2006-07-05 |
JP2007511901A (ja) | 2007-05-10 |
DE502004010498D1 (de) | 2010-01-21 |
US7423855B2 (en) | 2008-09-09 |
EP1676350B1 (de) | 2009-12-09 |
US20070146950A1 (en) | 2007-06-28 |
DE10349405A1 (de) | 2005-05-25 |
WO2005041375A3 (de) | 2007-05-03 |
WO2005041375A2 (de) | 2005-05-06 |
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