CN109841607B - 具有控制钳位超时行为的电路的用于静电放电（esd）保护的电源钳位 - Google Patents

具有控制钳位超时行为的电路的用于静电放电（esd）保护的电源钳位 Download PDF

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CN109841607B
CN109841607B CN201711385438.6A CN201711385438A CN109841607B CN 109841607 B CN109841607 B CN 109841607B CN 201711385438 A CN201711385438 A CN 201711385438A CN 109841607 B CN109841607 B CN 109841607B
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V·巴特瑞
R·斯坦安达姆
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STMicroelectronics International NV
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    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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Abstract

本公开涉及具有控制钳位超时行为的电路的用于静电放电(ESD)保护的电源钳位。例如，在使用由ESD事件驱动晶体管器件形成的电源钳位电路中提供了静电放电(ESD)保护。响应于独立于电压的电流发生器电路的操作而生成偏置电流。偏置电流被发起以确保晶体管器件在ESD事件消散之后被去激活。

Description

具有控制钳位超时行为的电路的用于静电放电(ESD)保护的 电源钳位
技术领域
本发明涉及一种用于保护集成电路免受过电压并且特别是防止静电放电的装置。
背景技术
图1示出了用于集成电路中的静电放电(ESD)保护的常规电源钳位电路10的电路图。电源钳位电路10由耦合在集成电路的第一电源线14和集成电路的第二电源线16之间的晶体管开关电路12形成。第一电源线14被耦合到集成电路的正电源焊盘22，第二电源线16被耦合到集成电路的负电源焊盘或接地电源焊盘24。待保护的功能电路28也耦合在第一电源线14和第二电源线16之间。晶体管开关电路12具有耦合到第一电源线14的第一导电端子32和耦合到第二电源线16的第二导电端子34。晶体管开关电路12的控制端子36接收由触发电路40产生的触发信号，触发电路40分别感测第一或第二电源线14和16中的瞬态电压差，并响应于感测到的差而启动以断言(assert)触发信号。在一个实施例中，晶体管开关电路12包括n沟道MOSFET器件，其中第一导电端子32是漏极端子，第二导电端子34是源极端子并且控制端子36是栅极端子。触发电路40包括ESD检测电路42和触发信号调节电路44。在本领域中也称为转换速率检测电路的ESD检测电路42由包括电阻器50的电阻-电容(RC)电路形成，该电阻器50与第一和第二电源线14和16之间的电容器52串联连接。电阻器50的第一端子连接到第二电源线16，并且电阻器50的第二端子连接到节点56。电容器52的第二极板(plate)连接到节点56，电容器52的第二极板连接到第一电源线14。触发信号调节电路44在本领域中也被称为预驱动器电路，包括分别串联连接的第一和第二反相器电路60和62。反相器电路60和62由第一和第二电源线14和16供电，反相器电路60的输入连接到节点56，反相器电路60的输出连接到反相器电路62的输入，反相器电路60的输出连接到晶体管开关电路12的控制端子36。
ESD检测电路42被设计成响应于检测到在第一或第二电源线14和16处的转换速率变化而在节点56处断言触发信号，该转换速率变化比一些临界值更快(例如，典型的ESD事件，该值在本领域中被称为目标ESD检测限值)。否则，触发信号不会被断言。响应于触发信号的断言，晶体管开关电路12被致动(这被称为“开启”)。例如，在微秒量级的短时间段之后(这被称为“超时”)，随后使晶体管开关电路12去激活是重要的。本领域中需要电源钳位电路包括用于控制钳位超时的电路。在这方面，超时需要被延迟到足以确保ESD事件被解除，但延迟不能过度。同时，必须确定超时，以确保晶体管开关电路12完全关断。
举例来说，电源钳位的以下操作参数是期望的：a)触发速度：小于200-300ps的开启时间；b)ESD上升时间检测限值：60ns目标，其中小于60ns的上升时间(转换速率)指示ESD事件，并且晶体管开关电路应当完全导通，并且其中大于60ns的上升时间是正常工作的部分，并且晶体管开关电路应保持断开，并且其中焊盘处的正常输入/输出振铃(ringing)和正常加电不应触发导通；c)保持时间：晶体管开关电路一旦在导通时被触发，就应在ESD事件期间保持完全导通，并且在一定的保持时间之后晶体管开关电路应该被完全关断以防止钳位泄漏。
发明内容
在一个实施例中，一种静电放电(ESD)保护电路包括：第一电源线；第二电源线；开关电路，具有连接到第一电源线的第一传导端子、连接到第二电源线的第二传导端子和栅极控制端子；触发电路，用于响应于在第一电源线和第二电源线中的一个或多个电源线处检测到ESD事件而在开关电路的栅极端子处断言触发信号；以及独立于电压的电流发生器电路，由第一电源线和第二电源线供电，以产生控制触发信号的解除断言的偏置电流。
在一个实施例中，一种静电放电(ESD)保护电路包括：第一电源线；第二电源线；开关电路，具有连接到第一电源线的第一传导端子、连接到第二电源线的第二传导端子和栅极控制端子；反相器电路，具有连接到开关电路的栅极控制端子的输出；第一晶体管，具有连接在反相器电路的输入和第二电源线之间的源极-漏极路径以及被耦合以接收ESD检测信号的控制栅极；第二晶体管，具有连接在反相器电路的输入与第一电源线之间的源极-漏极路径以及被耦合以接收偏置电流控制信号的控制栅极；ESD检测电路，被配置为响应于检测到ESD事件而断言ESD检测信号；以及独立于电压的电流发生器电路，由第一电源线和第二电源线供电，并且被配置为产生偏置电流控制信号。
附图说明
本公开包括附图，以提供对本发明的进一步理解，并且被结合在本说明书中并且构成本说明书的一部分，示出了本发明的实施例并且与说明书一起用于解释本发明的原理。
在附图中：
图1示出了用于静电放电(ESD)保护的传统电源钳位电路的电路图；
图2是电源钳位电路的框图；以及
图3是图2的电源钳位电路的电路图。
具体实施方式
现在参考图2，其示出了电源钳位电路100的框图。电路100包括转换速率检测器电路102，该转换速率检测器电路在本实施方式中用作ESD检测电路，用于检测发生在集成电路焊盘处或之间的ESD事件。转换速率检测器电路102响应于集成电路焊盘处的电压改变超过特定转换速率(例如，由于发生ESD事件而导致电压改变)，产生ESD检测信号104。电路100还包括预驱动器电路106，其具有接收ESD检测信号104的第一输入和接收偏置电流控制信号108的第二输入。预驱动器电路106用于调节ESD检测信号104并输出驱动(触发)信号110。转换速率检测器电路102和预驱动器电路106一起形成控制钳位电路112的致动(actuation)和消动(deactuation)的触发电路118。钳位电路112响应于驱动信号110以在集成电路的焊盘之间钳位而致动，并且响应于驱动信号110的解除断言而消动。偏置电流控制信号108由独立于电源的电流源电路116生成，并且源于确保钳位电路112在ESD事件消散之后被消动。
图3示出了图2的电源钳位电路100的电路图。
钳位电路112包括耦合在集成电路的第一电源线124和集成电路的第二电源线126之间的晶体管开关电路122。第一电源线124耦合到用于集成电路的正电源焊盘132，并且第二电源线126耦合到集成电路的负或接地电源焊盘134。待保护的功能电路138也耦合在第一电源线124和第二电源线126之间。晶体管开关电路122具有耦合到第一电源线124的第一传导端子142和耦合到第二电源线126的第二传导端子144。晶体管开关电路122的控制端子146接收驱动信号110。在一个实施例中，晶体管开关电路122包括n沟道MOSFET器件，其中第一导电端子142是漏极端子，第二导电端子144是源极端子，而控制端子146是栅极端子。电阻器150具有连接到控制端子146的第一端子和连接到第二电源线126的第二端子。
预驱动器电路106包括从第一和第二电源线124和126供电的反相器电路160。反相器电路160的输出连接到晶体管开关电路122的控制端子146，并产生驱动信号110。n沟道MOSFET器件162具有连接到反相器电路160的输入166的漏极端子和连接到第二电源线126的源极端子(即，n沟道MOSFET器件162的源极-漏极路径连接在输入166和线126之间)。n沟道MOSFET器件162的栅极端子提供接收ESD检测信号104的预驱动器电路106的第一输入。P沟道MOSFET器件164具有连接到反相器电路160的输入166的漏极端子和连接到第一电源线124的源极端子(即，p沟道MOSFET器件164的源极-漏极路径连接在输入166和线124之间)。p沟道MOSFET器件164的栅极端子提供接收偏置电流控制信号108的预驱动器电路106的第二输入，并且p沟道MOSFET器件164的漏极端子向反相器电路160的输入166提供偏置电流Ibias。
独立于电源的电流源电路116与绝对温度(PTAT)CMOS电流源成比例，独立于电源电压。第一n沟道MOSFET器件170具有连接到第二电源线126的源极端子。第二n沟道MOSFET器件172具有经由电阻器174连接到第二电源线126的源极端子。第一和第二n沟道MOSFET器件170和172的栅极端子彼此连接并连接到第一n沟道MOSFET器件170的漏极端子。第一p沟道MOSFET器件176具有连接到第一电源线124的源极端子和连接到第一n沟道MOSFET器件170的漏极端子的漏极端子。第二p沟道MOSFET器件178具有连接到第一电源线124的源极端子和连接到第二n沟道MOSFET器件172的漏极端子的漏极端子。第一和第二p沟道MOSFET器件176和178的栅极端子彼此连接并连接到第二p沟道MOSFET器件178的漏极端子。PTATCMOS电流源的操作是本领域技术人员所熟知的(参见例如美国专利号7,944,271的图2和相关描述，其通过引用并入本文)。
预驱动器电路106中的p沟道MOSFET器件164的栅极端子以电流镜像电路配置连接到第一和第二p沟道MOSFET器件176和178的栅极端子。因此，由独立于电源的电流源电路116产生的PTAT电流被p沟道MOSFET器件164镜像以提供偏置电流Ibias。
在备选实施方式中，独立于电源的电流源电路116可以包括带隙型电流发生器电路。这种电流发生器电路的电路配置对于本领域技术人员是已知的。预驱动器电路106中的p沟道MOSFET器件164的栅极端子类似地连接到带隙型电流发生器电路的电流镜像节点。
转换速率检测器电路102包括电阻-电容(RC)电路，该电路包括与第一和第二电源线124和126之间的电容器182串联连接的电阻器180。电阻器180的第一端子连接到第二电源线126并且电阻器180的第二端子连接到节点186，从而提供了转换速率检测器电路102的输出，在该处生成ESD检测信号104。电容器182的第一极板连接到节点186，电容器182的第二极板连接到第一电源线124。n沟道MOSFET器件184的源极和漏极端子连接到第二电源线126，并且其栅极端子连接到节点186。n沟道MOSFET器件184因此被连接以形成MOSFET电容器。二极管188的阳极端子连接到节点186，阴极端子连接到第一供电线路124。
转换速率检测器电路102作为基于RC的瞬态检测电路工作。由该电路102执行的一个功能是作为电源转换速率检测器，其响应于典型的ESD事件的转换速率来启动钳位电路，同时保持钳位电路在电源的低于目标ESD检测限值的所有转换速率处断开。由电路102执行的另一功能是，一旦响应于检测到的ESD事件而被启动，就进行操作以使钳位晶体管保持在导通状态一段时间，这段时间足以完全耗散ESD脉冲。二极管188用于(充电设备模型)CDM目的，并且可以是电路100的一些实施方式中的可选部件。配置为电容器的晶体管184存在于电路100中以微调电路设计，并且可以是电路100的一些实施方式中的可选组件。
图3的电源钳位电路100依次工作如下：a)转换速率检测器电路102感测第一和第二电源线124和126处或之间的快速瞬变，并使节点186处的电压升高，断言ESD检测信号104；b)节点186处的上升电压将最终超过n沟道MOSFET器件162的导通电压；c)当n沟道MOSFET器件162导通时，到反相器电路160的输入转换到第二电源线126处的电压，并且反相器电路160内的上拉晶体管导通；d)然后，反相器电路160的输出上升到第一供电线路124处的电压，断言驱动信号110；e)晶体管开关电路122然后由驱动信号110致动以钳位第一和第二电源线124和126。
响应于第一和第二电源线124和126上的钳位动作，第一电源线124处的电压(例如由外部电压源供电)可能崩溃。独立于电源的电流源电路116由第一供电线路124供电。然而，崩溃的供电电压不是所关心的，因为所产生的偏置电流108在PTAT时是独立于电源的。因此，独立于电源的电流源电路116将继续产生独立于电压的电流，其在预驱动器电路106中由p沟道MOSFET器件164镜像，从而即使在崩溃电源电压条件下也获得偏置电流Ibias。
提供电阻器150以在启动期间将节点146保持接地。考虑在没有电阻器150的情况下加电时电路的操作。当电源电压斜升时，电路的器件在完全接通之前通过子阈值区域。当电路工作在该子阈值区域时，节点166处的电压由晶体管164和晶体管162之间的泄漏平衡确定。该泄漏平衡可以依赖于过程而广泛地变化。因此，响应于节点166处的电压的反相器160可能无意中将节点146驱动为高。然而，该操作在电阻器150存在的情况下被排除。
图3的电源钳位电路100将进一步如下操作：a)当检测到的快速瞬态结束时，ESD检测信号104被解除断言，并且n沟道MOSFET器件162将不再驱动到第二供应线126的反相器电路160的输入166；b)独立于电压的电流被p沟道MOSFET器件164镜像，并且作为偏置电流Ibias被提供给反相器电路160的输入端166；c)响应于偏置电流Ibias，反相器输入166处的电压将升高，并且反相器电路160内的下拉晶体管导通；d)反相器电路160的输出然后下降到第二供应线126处的电压，并且驱动信号110被解除断言；e)晶体管开关电路122然后被消动，以释放第一和第二电源线124和126的钳位。超时周期取决于p沟道MOSFET器件164的强度。
对于本领域的技术人员显而易见的是，在不脱离本发明的精神或范围的情况下，可以对本发明进行各种修改和变化。因此，本发明旨在覆盖落入所附权利要求及其等同物范围内的本发明的修改和变化。

Claims (18)

1.一种静电放电(ESD)保护电路，包括：
第一电源线；
第二电源线；
开关电路，具有连接到所述第一电源线的第一传导端子、连接到所述第二电源线的第二传导端子和栅极控制端子；
触发电路，用于响应于在所述第一电源线和所述第二电源线中的一个或多个电源线处检测到ESD事件而在所述开关电路的所述栅极控制端子处产生触发信号；以及
独立于电源电压的电流发生器电路，由所述第一电源线和所述第二电源线供电，用以产生偏置电流来控制所述触发信号的解除，
其中所述触发电路包含电阻电容ESD检测电路，所述电阻电容ESD检测电路被配置为响应于所述ESD事件而产生ESD检测信号，
其中所述触发电路进一步包括与所述电阻电容ESD检测电路的电阻器并联耦合的MOSFET电容器，
其中所述独立于电源电压的电流发生器电路至少包括：
第一p沟道MOSFET器件，具有漏极端子和连接到所述第一电源线的源极端子；
第二p沟道MOSFET器件，具有漏极端子和连接到所述第一电源线的源极端子，所述第一p沟道MOSFET器件和所述第二p沟道MOSFET器件的栅极端子彼此连接并连接到所述第二p沟道MOSFET器件的漏极端子，以及
其中所述触发电路包括：
反相器电路，具有输入，并具有产生所述触发信号的输出；
第一晶体管，具有连接在所述反相器电路的输入与所述第二电源线之间的源极-漏极路径以及被耦合以接收所述ESD检测信号的控制栅极；以及
第二晶体管，具有连接在所述反相器电路的输入和所述第一电源线之间的源极-漏极路径以及被耦合到所述第二p沟道MOSFET器件的漏极端子的控制栅极。
2.根据权利要求1所述的电路，还包括功能电路，所述功能电路被电耦合至所述第一电源线和所述第二电源线，用于为所述功能电路供电。
3.根据权利要求1所述的电路，其中所述开关电路是MOSFET器件，并且所述开关电路的第一传导端子是连接到所述第一电源线的漏极端子，并且所述第二传导端子是连接到所述第一电源线的源极端子。
4.根据权利要求1所述的电路，其中所述触发电路还包括与所述电阻电容ESD检测电路的电容器并联耦合的二极管。
5.根据权利要求1所述的电路，其中所述偏置电流从所述第二晶体管的源极-漏极路径输出。
6.根据权利要求1所述的电路，其中所述ESD检测电路包括与所述第一电源线和产生所述ESD检测信号的输出之间的电容器并联耦合的二极管以及与所述第二电源线和产生所述ESD检测信号的输出之间的电阻器并联耦合的MOSFET电容器。
7.根据权利要求1所述的电路，还包括电阻器，所述电阻器具有连接到所述开关电路的所述栅极控制端子的第一端子和连接到所述第二电源线的第二端子。
8.根据权利要求1所述的电路，其中所述独立于电源电压的电流发生器电路与绝对温度(PTAT)电流发生器电路成比例。
9.根据权利要求1所述的电路，其中所述触发电路包括：
第一晶体管，具有连接在节点与所述第二电源线之间的源极-漏极路径以及被耦合以接收所述ESD检测信号的控制栅极；以及
第二晶体管，具有连接在所述节点和所述第一电源线之间的源极-漏极路径以及被耦合到所述独立于电源电压的电流发生器电路的输出的控制栅极；
其中所述触发信号是响应于所述节点处的电压而生成的。
10.根据权利要求9所述的电路，其中所述偏置电流从所述第二晶体管的源极-漏极路径输出。
11.根据权利要求9所述的电路，其中所述ESD检测电路包括与所述第一电源线和产生所述ESD检测信号的输出之间的电容器并联耦合的二极管。
12.根据权利要求9所述的电路，其中所述ESD检测电路包括与所述第二电源线和产生所述ESD检测信号的输出之间的电阻器并联耦合的MOSFET电容器。
13.一种静电放电(ESD)保护电路，包括：
第一电源线；
第二电源线；
开关电路，具有连接到所述第一电源线的第一传导端子、连接到所述第二电源线的第二传导端子和栅极控制端子；
反相器电路，具有连接到所述开关电路的所述栅极控制端子的输出；
第一晶体管，具有连接在所述反相器电路的输入和所述第二电源线之间的源极-漏极路径以及被耦合以接收ESD检测信号的控制栅极；
第二晶体管，具有连接在所述反相器电路的输入与所述第一电源线之间的源极-漏极路径以及被耦合以接收偏置电流控制信号的控制栅极；
ESD检测电路，被配置为响应于检测到ESD事件而产生所述ESD检测信号；以及
独立于电源电压的电流发生器电路，由所述第一电源线和所述第二电源线供电，并且被配置为产生所述偏置电流控制信号，
其中所述ESD检测电路包括：
电容器，位于所述第一电源线与所述第一晶体管的控制栅极之间；和
电阻器，位于所述第二电源线与所述第一晶体管的控制栅极之间，
其中所述ESD检测电路进一步包括与所述电阻器并联耦合的MOSFET电容器，
其中所述独立于电源电压的电流发生器电路至少包括：
第一p沟道MOSFET器件，具有漏极端子和连接到所述第一电源线的源极端子；
第二p沟道MOSFET器件，具有漏极端子和连接到所述第一电源线的源极端子，所述第一p沟道MOSFET器件和所述第二p沟道MOSFET器件的栅极端子彼此连接并连接到所述第二p沟道MOSFET器件的漏极端子，以及
其中所述第二晶体管的控制栅极被耦合到所述第二p沟道MOSFET器件的漏极端子。
14.根据权利要求13所述的电路，还包括功能电路，所述功能电路被电耦合，以由所述第一电源线和所述第二电源线供电。
15.根据权利要求13所述的电路，其中所述开关电路是MOSFET器件，并且所述开关电路的所述第一传导端子是连接到所述第一电源线的漏极端子，并且所述第二传导端子是连接到所述第一电源线的源极端子。
16.根据权利要求13所述的电路，其中所述ESD检测电路进一步包括与所述电容器并联耦合的二极管。
17.根据权利要求13所述的电路，还包括电阻器，所述电阻器具有连接到所述开关电路的所述栅极控制端子的第一端子和连接到所述第二电源线的第二端子。
18.根据权利要求13所述的电路，其中所述独立于电源电压的电流发生器电路与绝对温度(PTAT)电流发生器电路成比例。
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Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
CN108695313B (zh) 2017-03-29 2023-03-21 意法半导体国际有限公司 使用遂穿场效应晶体管和碰撞电离mosfet器件的静电放电保护电路
US10811873B2 (en) * 2017-11-28 2020-10-20 Stmicroelectronics International N.V. Power supply clamp for electrostatic discharge (ESD) protection having a circuit for controlling clamp time out behavior
US10965118B2 (en) * 2018-02-07 2021-03-30 Mediatek Inc. Over voltage/energy protection apparatus
US11063429B2 (en) 2018-04-12 2021-07-13 Stmicroelectronics International N.V. Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection
US10944257B2 (en) * 2018-04-13 2021-03-09 Stmicroelectronics International N.V. Integrated silicon controlled rectifier (SCR) and a low leakage SCR supply clamp for electrostatic discharge (ESP) protection
US11303116B2 (en) * 2018-08-29 2022-04-12 Allegro Microsystems, Llc Methods and apparatus for electrical overstress protection
US11387649B2 (en) * 2019-09-11 2022-07-12 Vanguard International Semiconductor Corporation Operating circuit having ESD protection function
CN114512489A (zh) * 2020-11-16 2022-05-17 力旺电子股份有限公司 非挥发性存储器的存储单元
JP2022135597A (ja) * 2021-03-05 2022-09-15 キオクシア株式会社 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552886B1 (en) * 2000-06-29 2003-04-22 Pericom Semiconductor Corp. Active Vcc-to-Vss ESD clamp with hystersis for low supply chips
CN1868104A (zh) * 2003-10-10 2006-11-22 飞思卡尔半导体公司 静电放电保护电路及操作方法
CN103582948A (zh) * 2011-06-01 2014-02-12 全球Oled科技有限责任公司 用于显示和感测图像的设备
CN105098743A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 动态静电放电钳位电路
CN105470252A (zh) * 2014-09-29 2016-04-06 瑞萨电子株式会社 半导体器件
CN107026434A (zh) * 2016-01-29 2017-08-08 联发科技股份有限公司 静电放电保护电路及方法
CN208284476U (zh) * 2017-11-28 2018-12-25 意法半导体国际有限公司 静电放电（esd）保护电路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI264106B (en) * 2002-04-30 2006-10-11 Winbond Electronics Corp Static charge protection circuit of adopting gate-coupled MOSFET (metal-oxide-semiconductor field effect transistor)
US7209332B2 (en) * 2002-12-10 2007-04-24 Freescale Semiconductor, Inc. Transient detection circuit
US7944271B2 (en) 2009-02-10 2011-05-17 Standard Microsystems Corporation Temperature and supply independent CMOS current source
FR2956246B1 (fr) * 2010-02-08 2013-11-01 St Microelectronics Rousset Circuit integre muni d'une protection contre des decharges electrostatiques
US8890047B2 (en) * 2011-09-21 2014-11-18 Aptina Imaging Corporation Stacked-chip imaging systems
JP2014120711A (ja) * 2012-12-19 2014-06-30 Toshiba Corp Ｅｓｄ保護回路
CN104765397B (zh) * 2014-01-02 2017-11-24 意法半导体研发(深圳)有限公司 用于内部电源的具有改善的负载瞬态性能的ldo调节器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552886B1 (en) * 2000-06-29 2003-04-22 Pericom Semiconductor Corp. Active Vcc-to-Vss ESD clamp with hystersis for low supply chips
CN1868104A (zh) * 2003-10-10 2006-11-22 飞思卡尔半导体公司 静电放电保护电路及操作方法
CN103582948A (zh) * 2011-06-01 2014-02-12 全球Oled科技有限责任公司 用于显示和感测图像的设备
CN105098743A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 动态静电放电钳位电路
CN105470252A (zh) * 2014-09-29 2016-04-06 瑞萨电子株式会社 半导体器件
CN107026434A (zh) * 2016-01-29 2017-08-08 联发科技股份有限公司 静电放电保护电路及方法
CN208284476U (zh) * 2017-11-28 2018-12-25 意法半导体国际有限公司 静电放电（esd）保护电路

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
曾庆贵等.瞬态ESD钳位电路.《集成电路版图设计教程》.2012,232页. *
李春茂.电压源和电流源.《电路基础》.2011, *

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