KR20040071631A - 반도체장치 및 그 제조방법 - Google Patents
반도체장치 및 그 제조방법 Download PDFInfo
- Publication number
- KR20040071631A KR20040071631A KR1020040007357A KR20040007357A KR20040071631A KR 20040071631 A KR20040071631 A KR 20040071631A KR 1020040007357 A KR1020040007357 A KR 1020040007357A KR 20040007357 A KR20040007357 A KR 20040007357A KR 20040071631 A KR20040071631 A KR 20040071631A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- interlayer insulating
- insulating film
- wiring
- carbon concentration
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 230
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 228
- 230000004888 barrier function Effects 0.000 claims abstract description 161
- 239000011229 interlayer Substances 0.000 claims abstract description 119
- 239000010410 layer Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims description 34
- 239000007789 gas Substances 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 27
- 239000001301 oxygen Substances 0.000 claims description 27
- 229910052760 oxygen Inorganic materials 0.000 claims description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 238000004380 ashing Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 15
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 239000002994 raw material Substances 0.000 claims description 12
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims description 11
- 238000010521 absorption reaction Methods 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 9
- GCSJLQSCSDMKTP-UHFFFAOYSA-N ethenyl(trimethyl)silane Chemical compound C[Si](C)(C)C=C GCSJLQSCSDMKTP-UHFFFAOYSA-N 0.000 claims description 5
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000862 absorption spectrum Methods 0.000 claims description 2
- 238000009751 slip forming Methods 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 239000010949 copper Substances 0.000 abstract description 72
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 21
- 230000008569 process Effects 0.000 description 15
- 229910010271 silicon carbide Inorganic materials 0.000 description 15
- 230000000694 effects Effects 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 8
- 125000004429 atom Chemical group 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 238000011161 development Methods 0.000 description 6
- 229910018540 Si C Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 4
- 230000002265 prevention Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (14)
- 상감법에 의해 형성된 배선(interconnection) 또는 비아플러그를 구비한 반도체장치에 있어서, 실리콘 및 탄소를 함유하며 다른 탄소함유량을 갖는 복수개의 적층막들로 이루어진 장벽막이 상기 배선 또는 상기 비아플러그 및 그것의 상층인 층간절연막 사이에 배치된 구조를 포함하는 반도체장치.
- 상감법에 의해 형성된 배선 또는 비아플러그를 구비한 반도체장치에 있어서, 실리콘, 탄소 및 질소를 함유하며 다른 탄소함유량을 갖는 복수개의 적층막들로 이루어진 장벽막이 상기 배선 또는 상기 비아플러그 및 그것의 상층인 층간절연막 사이에 배치된 구조를 포함하는 반도체장치.
- 제1항 또는 제2항에 있어서, 상기 장벽막은, 상기 배선 또는 상기 비아플러그 측에, 적은 탄소함유량의 저탄소농도막을, 그리고, 상기 층간절연막 측에, 상기 저탄소농도막의 탄소함유량보다 많은 탄소함유량을 갖는 고탄소농도막을 포함하는 반도체장치.
- 제3항에 있어서, 상기 장벽막의 적외선흡수스펙트럼에서, 810㎝-1근방에서 피크를 갖는 적외선흡수대의 적외선흡수면적을 I1로 표시하고 1250㎝-1근방에서 피크를 갖는 적외선흡수대의 적외선흡수면적을 I2로 표시할 때,상기 장벽막에서의 상기 저탄소농도막에 대한 I2/I1의 값은 대략 0.004 내지 0.0067이고, 상기 장벽막에서의 상기 저탄소농도막에 대한 I2/I1의 값은 대략 0.0067 내지 0.014인 반도체장치.
- 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 장벽막 상에 형성된 상기 층간절연막은 주된 구성원소들이 실리콘, 탄소 및 산소인 절연막으로 이루어진 반도체장치.
- 배선 또는 비아플러그가 상감법에 의해 형성되는 반도체장치를 제조하는 방법에 있어서,실리콘 및 탄소를 함유하며 다른 탄소함유량을 갖는 복수개의 적층막들로 이루어진 장벽막을 상기 배선 또는 상기 비아플러그 및 그것의 상층인 층간절연막 사이에 배치하는 단계를 포함하는 반도체장치 제조방법.
- 배선 또는 비아플러그가 상감법에 의해 형성되는 반도체장치를 제조하는 방법에 있어서,실리콘, 탄소 및 질소를 함유하며 다른 탄소함유량을 갖는 복수개의 적층막들로 이루어진 장벽막을 상기 배선 또는 상기 비아플러그 및 그것의 상층인 층간절연막 사이에 배치하는 단계를 포함하는 반도체장치 제조방법.
- 제6항 또는 제7항에 있어서, 적은 탄소함유량을 갖는 저탄소농도막이 상기 배선 또는 상기 비아플러그 측에 형성되고, 그 후 상기 저탄소농도막의 탄소함유량보다 많은 탄소함유량을 갖는 고탄소농도막이 상기 층간절연막 측에 형성되는 반도체장치 제조방법.
- 제6항 내지 제8항 중 어느 한 항에 있어서, 상기 장벽막 상에 위치된 상기 층간절연막은 주된 구성원소들이 실리콘, 탄소 및 산소인 절연막으로 이루어진 반도체장치 제조방법.
- 배선 또는 비아플러그가 형성된 기판 상에, 적어도, 실리콘, 탄소 및 질소를 함유하며 적은 탄소함유량을 갖는 저탄소농도막과 실리콘, 탄소 및 질소를 함유하며 상기 저탄소농도막의 탄소함유량보다 많은 탄소함유량을 갖는 고탄소농도막이 그 순서대로 놓이는 장벽막을 형성하는 단계;상기 장벽막 상에, 주된 구성원소들이 실리콘, 탄소 및 산소인 층간절연막을 형성하는 단계;상기 층간절연막 상에 형성된 레지스트패턴을 마스크로서 사용하고 상기 저탄소농도막을 식각스토퍼로서 사용하면서, 건식식각을 수행하여, 상기 층간절연막 및 상기 고탄소농도막을 제거하는 단계;상기 레지스트패턴을 산소함유기체를 이용한 애싱에 의해 제거하는 단계;상기 저탄소농도막을 에치백에 의해 제거하여 비아홀 또는 배선트렌치를 형성하는 단계; 및상기 비아홀 또는 상기 배선트렌치를 장벽금속 및 배선재료로 채워, 비아플러그 또는 배선을 형성하는 단계를 포함하는 반도체장치 제조방법.
- 제1배선이 형성된 기판 상에, 적어도, 실리콘, 탄소 및 질소를 함유하며 적은 탄소함유량을 갖는 저탄소농도막 및 실리콘, 탄소 및 질소를 함유하며 상기 저탄소농도막의 탄소함유량보다 많은 탄소함유량을 갖는 고탄소농도막이 그 순서로 놓이는 제1장벽막을 형성하는 단계;상기 제1장벽막 상에, 제1층간절연막, 제2장벽막 및 제2층간절연막의 주된 구성원소들이 실리콘, 탄소 및 산소인 제1층간절연막, 제2장벽막 및 제2층간절연막을 형성하는 단계;상기 제2층간절연막 상에 형성된 제1레지스트막을 마스크로서 사용하고 상기 저탄소농도막을 식각스토퍼로서 사용하면서, 건식식각을 수행하여, 상기 제2층간절연막, 상기 제2장벽막, 상기 제1층간절연막 및 상기 고탄소농도막을 제거하는 단계;상기 제1레지스트패턴을 산소함유기체를 이용한 애싱에 의해 제거하는 단계;상기 제2층간절연막 상에 형성된 제2레지스트패턴을 마스크로서 사용하고 상기 제2장벽막을 식각스토퍼로서 사용하면서, 건식식각을 수행하여, 상기 제2층간절연막을 제거하는 단계;상기 제2레지스트막을 산소함유기체를 이용한 애싱에 의해 제거하는 단계;상기 저탄소농도막을 에치백에 의해 제거하여 비아홀을 포함한 배선트렌치를 형성하는 단계; 및상기 배선트렌치를 장벽금속 및 배선재료로 채워, 제2배선을 형성하는 단계를 포함하는 반도체장치 제조방법.
- 제6항 내지 제11항 중 어느 한 항에 있어서, 플라즈마CVD(Chemical Vapor Deposition)법을 사용하여, 상기 장벽막 또는 상기 제1장벽막이 하나의 동일 챔버 내에서 원료기체압력을 변경하여 연속해서 형성되는 반도체장치 제조방법.
- 제12항에 있어서, 트리메틸실란, 테트라메틸실란 및 트리메틸비닐실란 중의 하나가 상기 원료기체로 사용되는 반도체장치 제조방법.
- 제8항, 제10항 및 제11항 중 어느 한 항에 있어서, 트리메틸실란, NH3및 He로 된 원료기체를 이용하는 플라즈마CVD법을 이용하여, 상기 저탄소농도막은 대략 330 내지 530㎩의 기체압력에서 성장되고 상기 고탄소농도막은 대략 530 내지 730㎩의 기체압력에서 성장되는 반도체장치 제조방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2003-00026783 | 2003-02-04 | ||
JP2003026783A JP4086673B2 (ja) | 2003-02-04 | 2003-02-04 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040071631A true KR20040071631A (ko) | 2004-08-12 |
KR100652243B1 KR100652243B1 (ko) | 2006-12-01 |
Family
ID=32820798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020040007357A KR100652243B1 (ko) | 2003-02-04 | 2004-02-04 | 반도체장치 및 그 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7391115B2 (ko) |
JP (1) | JP4086673B2 (ko) |
KR (1) | KR100652243B1 (ko) |
CN (1) | CN1519925B (ko) |
TW (1) | TWI278965B (ko) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7459388B2 (en) | 2006-09-06 | 2008-12-02 | Samsung Electronics Co., Ltd. | Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses |
KR100937953B1 (ko) * | 2009-07-02 | 2010-01-21 | 주식회사 아토 | 반도체 소자 및 그 제조 방법 |
US10090242B2 (en) | 2014-10-17 | 2018-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US10475739B2 (en) | 2017-08-02 | 2019-11-12 | Samsung Electronics Co., Ltd. | Semiconductor device |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1521127B1 (en) | 2003-10-01 | 2009-05-27 | Ricoh Company, Ltd. | Toner, process of manufacturing toner, developer, toner container, process cartridge, image forming apparatus, and image forming process |
US20060009038A1 (en) * | 2004-07-12 | 2006-01-12 | International Business Machines Corporation | Processing for overcoming extreme topography |
US20060138668A1 (en) * | 2004-12-27 | 2006-06-29 | Hung-Wen Su | Passivation structure for semiconductor devices |
JP5180426B2 (ja) * | 2005-03-11 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4578332B2 (ja) * | 2005-06-15 | 2010-11-10 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5022900B2 (ja) * | 2005-08-15 | 2012-09-12 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US7557447B2 (en) * | 2006-02-06 | 2009-07-07 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
JP4675258B2 (ja) * | 2006-02-22 | 2011-04-20 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法および半導体装置 |
JP2007305739A (ja) * | 2006-05-10 | 2007-11-22 | Nec Electronics Corp | 半導体装置 |
US8563431B2 (en) * | 2006-08-25 | 2013-10-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
JP4110192B1 (ja) * | 2007-02-23 | 2008-07-02 | キヤノン株式会社 | 光電変換装置及び光電変換装置を用いた撮像システム |
US7645701B2 (en) | 2007-05-21 | 2010-01-12 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
KR100900231B1 (ko) * | 2007-06-21 | 2009-06-02 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
JP2009088269A (ja) * | 2007-09-28 | 2009-04-23 | Toshiba Corp | 半導体装置、およびその製造方法 |
US7456030B1 (en) * | 2007-10-11 | 2008-11-25 | National Semiconductor Corporation | Electroforming technique for the formation of high frequency performance ferromagnetic films |
JP4675393B2 (ja) * | 2008-05-12 | 2011-04-20 | パナソニック株式会社 | 半導体装置および半導体装置の製造方法 |
JP5530118B2 (ja) * | 2009-04-08 | 2014-06-25 | 東京エレクトロン株式会社 | 酸化マンガン膜の形成方法、半導体装置の製造方法および半導体装置 |
US7928570B2 (en) * | 2009-04-16 | 2011-04-19 | International Business Machines Corporation | Interconnect structure |
US20100282758A1 (en) * | 2009-05-08 | 2010-11-11 | Gm Global Technology Operations, Inc. | Interlocking Hollow Tanks |
CN102110639B (zh) * | 2009-12-23 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | 制作扩散阻挡层的方法 |
US8349746B2 (en) * | 2010-02-23 | 2013-01-08 | Applied Materials, Inc. | Microelectronic structure including a low k dielectric and a method of controlling carbon distribution in the structure |
CN102468218B (zh) * | 2010-10-29 | 2014-07-02 | 中芯国际集成电路制造(北京)有限公司 | 形成双镶嵌结构的方法、半导体器件 |
JP5408116B2 (ja) * | 2010-12-17 | 2014-02-05 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP5755471B2 (ja) * | 2011-03-10 | 2015-07-29 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN102760689B (zh) * | 2011-04-29 | 2015-03-04 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件制造方法 |
CN102881632B (zh) * | 2011-07-13 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
US8525339B2 (en) | 2011-07-27 | 2013-09-03 | International Business Machines Corporation | Hybrid copper interconnect structure and method of fabricating same |
US8754508B2 (en) * | 2012-08-29 | 2014-06-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure to increase resistance to electromigration |
US9312203B2 (en) | 2013-01-02 | 2016-04-12 | Globalfoundries Inc. | Dual damascene structure with liner |
JP6037914B2 (ja) * | 2013-03-29 | 2016-12-07 | 富士フイルム株式会社 | 保護膜のエッチング方法およびテンプレートの製造方法 |
KR102186873B1 (ko) * | 2013-11-08 | 2020-12-04 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
JP6318433B2 (ja) * | 2013-11-28 | 2018-05-09 | 大陽日酸株式会社 | シリコン窒化膜の形成方法及びシリコン窒化膜 |
US10163644B2 (en) * | 2014-02-07 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company | Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same |
KR102161793B1 (ko) * | 2014-07-18 | 2020-10-06 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN105336673A (zh) * | 2014-07-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
US9576852B2 (en) * | 2015-06-26 | 2017-02-21 | GlobalFoundries, Inc. | Integrated circuits with self aligned contacts and methods of manufacturing the same |
KR102521554B1 (ko) * | 2015-12-07 | 2023-04-13 | 삼성전자주식회사 | 배선 구조물, 배선 구조물 설계 방법, 및 배선 구조물 형성 방법 |
US10658296B2 (en) * | 2016-09-30 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dielectric film for semiconductor fabrication |
US10510657B2 (en) | 2017-09-26 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with interconnecting structure and method for manufacturing the same |
KR102606765B1 (ko) * | 2018-02-07 | 2023-11-27 | 삼성전자주식회사 | 비아 플러그를 갖는 반도체 소자 및 그 형성 방법 |
US10741442B2 (en) * | 2018-05-31 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer formation for conductive feature |
US10672652B2 (en) * | 2018-06-29 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gradient atomic layer deposition |
KR102580659B1 (ko) * | 2018-10-01 | 2023-09-20 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR20210137276A (ko) * | 2020-05-07 | 2021-11-17 | 삼성전자주식회사 | 반도체 소자 |
US20220108917A1 (en) * | 2020-10-06 | 2022-04-07 | Applied Materials, Inc. | Low resistance and high reliability metallization module |
CN115775768B (zh) * | 2023-02-13 | 2023-07-04 | 长鑫存储技术有限公司 | 半导体结构及其制作方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6227151B1 (en) * | 1997-08-01 | 2001-05-08 | Ford Global Technologies, Inc. | Gasoline internal combustion engine |
US6436824B1 (en) | 1999-07-02 | 2002-08-20 | Chartered Semiconductor Manufacturing Ltd. | Low dielectric constant materials for copper damascene |
US6337151B1 (en) | 1999-08-18 | 2002-01-08 | International Business Machines Corporation | Graded composition diffusion barriers for chip wiring applications |
US6593653B2 (en) | 1999-09-30 | 2003-07-15 | Novellus Systems, Inc. | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications |
US6784485B1 (en) | 2000-02-11 | 2004-08-31 | International Business Machines Corporation | Diffusion barrier layer and semiconductor device containing same |
US6417092B1 (en) | 2000-04-05 | 2002-07-09 | Novellus Systems, Inc. | Low dielectric constant etch stop films |
JP4425432B2 (ja) | 2000-06-20 | 2010-03-03 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2002083870A (ja) | 2000-09-11 | 2002-03-22 | Tokyo Electron Ltd | 半導体装置及びその製造方法 |
JP4484345B2 (ja) | 2000-09-11 | 2010-06-16 | 東京エレクトロン株式会社 | 半導体装置及びその製造方法 |
US6350675B1 (en) * | 2000-10-12 | 2002-02-26 | Chartered Semiconductor Manufacturing Ltd. | Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects |
US6768200B2 (en) * | 2000-10-25 | 2004-07-27 | International Business Machines Corporation | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device |
US7091137B2 (en) * | 2001-12-14 | 2006-08-15 | Applied Materials | Bi-layer approach for a hermetic low dielectric constant layer for barrier applications |
US20030134499A1 (en) * | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
US6656840B2 (en) * | 2002-04-29 | 2003-12-02 | Applied Materials Inc. | Method for forming silicon containing layers on a substrate |
US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
-
2003
- 2003-02-04 JP JP2003026783A patent/JP4086673B2/ja not_active Expired - Fee Related
-
2004
- 2004-01-29 TW TW093102009A patent/TWI278965B/zh not_active IP Right Cessation
- 2004-02-02 US US10/768,676 patent/US7391115B2/en not_active Expired - Fee Related
- 2004-02-04 CN CN2004100036368A patent/CN1519925B/zh not_active Expired - Fee Related
- 2004-02-04 KR KR1020040007357A patent/KR100652243B1/ko active IP Right Grant
-
2008
- 2008-04-04 US US12/098,190 patent/US7910474B2/en active Active
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7459388B2 (en) | 2006-09-06 | 2008-12-02 | Samsung Electronics Co., Ltd. | Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses |
KR100937953B1 (ko) * | 2009-07-02 | 2010-01-21 | 주식회사 아토 | 반도체 소자 및 그 제조 방법 |
US10090242B2 (en) | 2014-10-17 | 2018-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US10720386B2 (en) | 2014-10-17 | 2020-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US11404368B2 (en) | 2014-10-17 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company Ltd | Etch stop layer in integrated circuits |
US11942419B2 (en) | 2014-10-17 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch stop layer in integrated circuits |
US10475739B2 (en) | 2017-08-02 | 2019-11-12 | Samsung Electronics Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR100652243B1 (ko) | 2006-12-01 |
CN1519925B (zh) | 2010-05-26 |
US7391115B2 (en) | 2008-06-24 |
JP2004241464A (ja) | 2004-08-26 |
JP4086673B2 (ja) | 2008-05-14 |
TW200425402A (en) | 2004-11-16 |
US20080194102A1 (en) | 2008-08-14 |
CN1519925A (zh) | 2004-08-11 |
US20040155342A1 (en) | 2004-08-12 |
US7910474B2 (en) | 2011-03-22 |
TWI278965B (en) | 2007-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100652243B1 (ko) | 반도체장치 및 그 제조방법 | |
US8822331B2 (en) | Anchored damascene structures | |
US8629560B2 (en) | Self aligned air-gap in interconnect structures | |
US7763979B2 (en) | Organic insulating film, manufacturing method thereof, semiconductor device using such organic insulating film and manufacturing method thereof | |
KR101677345B1 (ko) | 반도체 구조체 및 그 제조 방법 | |
JP4425432B2 (ja) | 半導体装置の製造方法 | |
US7176571B2 (en) | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure | |
US10510588B2 (en) | Interconnection structure and manufacturing method thereof | |
US20070059919A1 (en) | Method of manufacturing semiconductor device | |
US20070197023A1 (en) | Entire encapsulation of Cu interconnects using self-aligned CuSiN film | |
US20040067658A1 (en) | Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant | |
JP2007281114A (ja) | 半導体装置の製造方法および半導体装置 | |
US7602063B2 (en) | Semiconductor device and manufacturing method therefor | |
JP4746829B2 (ja) | 半導体装置およびその製造方法 | |
JP2004235548A (ja) | 半導体装置およびその製造方法 | |
US6352920B1 (en) | Process of manufacturing semiconductor device | |
US6689690B2 (en) | Semiconductor device manufacturing method of forming an etching stopper film on a diffusion prevention film at a higher temperature | |
JP5613272B2 (ja) | 半導体装置 | |
US7199038B2 (en) | Method for fabricating semiconductor device | |
US20230178379A1 (en) | Film deposition for patterning process | |
JP2007088495A (ja) | 有機絶縁膜及びその製造方法及び有機絶縁膜を用いた半導体装置及びその製造方法 | |
KR20100073779A (ko) | 반도체 소자의 금속배선 및 그 제조 방법 | |
KR20060118257A (ko) | 반도체 소자의 제조방법 | |
JP2005252199A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2003078008A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E90F | Notification of reason for final refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121114 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20131031 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20141103 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20151016 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20161019 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20171018 Year of fee payment: 12 |