KR20040038142A - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR20040038142A KR20040038142A KR1020020067021A KR20020067021A KR20040038142A KR 20040038142 A KR20040038142 A KR 20040038142A KR 1020020067021 A KR1020020067021 A KR 1020020067021A KR 20020067021 A KR20020067021 A KR 20020067021A KR 20040038142 A KR20040038142 A KR 20040038142A
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- nitride film
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000002955 isolation Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 101000793686 Homo sapiens Azurocidin Proteins 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 특히, STI(Shallow Trench Isolation) 공정을 통해 형성된 소자분리막 표면이 세정 공정을 포함한 후속 공정에 의해 손실되는 것을 방지하기 위한 방법에 관한 것이다.The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, to a method for preventing the surface of a device isolation film formed through a shallow trench isolation (STI) process from being lost by a subsequent process including a cleaning process.
주지된 바와 같이, 최근의 반도체 소자는 소자들간의 전기적 분리를 위한 소자분리막을 STI(Shallow Trench Isolation) 공정을 이용하여 형성하고 있다. 이것은 기존의 로코스(LOCOS) 공정의 경우 소자분리막의 상단 가장자리에 새부리 형상의 버즈-빅(bird's-beak)이 발생되는 것으로 인해 액티브 영역의 크기를 감소시키게 되지만, 상기 STI 공정의 경우 작은 폭으로의 소자분리막 형성이 가능하여 액티브 영역의 크기를 확보할 수 있기 때문이다.As is well known, recent semiconductor devices have formed a device isolation film for electrical isolation between devices using a shallow trench isolation (STI) process. This reduces the size of the active region due to the bird's-beak of the beak shape at the upper edge of the device isolation layer in the conventional LOCOS process, but in a small width in the STI process This is because the device isolation film can be formed to ensure the size of the active region.
이하에서는 종래의 STI 공정을 이용한 소자분리막 형성방법을 도 1a 및 도 1b를 참조하여 간략하게 설명하도록 한다.Hereinafter, a device isolation film forming method using a conventional STI process will be briefly described with reference to FIGS. 1A and 1B.
도 1a를 참조하면, 실리콘 기판(1) 상에 패드산화막(2)과 패드질화막(3)을 차례로 형성한 다음, 공지의 공정에 따라 상기 패드질화막(3)과 패드산화막(2)을 패터닝하여 필드(field) 영역에 해당하는 기판 부분을 노출시킨다. 그런다음, 노출된 기판 부분을 식각하여 소정 깊이의 트렌치(4)를 형성한다. 이어서, 트렌치(4)를 매립하도록 상기 기판 결과물 상에 두껍게 산화막(5)을 증착한 후, 상기 패드질화막(3)이 노출될 때까지 산화막(5)의 표면을 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP)한다.Referring to FIG. 1A, a pad oxide film 2 and a pad nitride film 3 are sequentially formed on a silicon substrate 1, and then the pad nitride film 3 and the pad oxide film 2 are patterned according to a known process. A portion of the substrate corresponding to the field region is exposed. The exposed substrate portions are then etched to form trenches 4 of predetermined depth. Subsequently, a thick oxide film 5 is deposited on the substrate resultant to fill the trench 4, and then the surface of the oxide film 5 is chemically mechanically polished until the pad nitride film 3 is exposed. Hereinafter, CMP).
도 1b를 참조하면, 트렌치 형성을 위한 기판 식각시에 식각 장벽으로 이용된 패드질화막을, 예컨데, 인산(H3PO4) 등의 식각액을 이용한 습식 식각을 통해 제거하고, 이 결과로서, 트렌치형의 소자분리막(6)을 형성한다.Referring to FIG. 1B, a pad nitride film used as an etching barrier when etching a substrate for forming trenches is removed by wet etching using an etchant such as phosphoric acid (H 3 PO 4), and as a result, a trench type device isolation film. (6) is formed.
그러나, 전술한 종래의 STI 공정을 이용한 소자분리막의 형성방법에 따르면, 그 자체로는 큰 문제가 없지만, 산화막의 CMP 후 금속배선 공정까지 세정 공정을 포함한 일련의 후속 공정이 진행되는 동안 500∼1000Å 정도 소자분리막의 표면 손실(loss)이 발생하게 되고, 이에 따라, 도 2에 도시된 바와 같이, 최종적인 토폴로지(topology)에서 소자분리막(6)의 표면이 액티브 영역의 실리사이드막(8) 표면 보다 낮아짐으로써 접합 누설(leakage current) 현상이 일어나는 것에 의해 소자 특성 저하가 초래된다. 도 2에서, 미설명된 도면부호 7은 접합 영역, 9은 층간절연막, 그리고, 10은 콘택홀을 각각 나타낸다.However, according to the method of forming a device isolation film using the above-described conventional STI process, there is no problem in itself. Surface loss of the device isolation film is generated, and as shown in FIG. 2, the surface of the device isolation film 6 in the final topology is larger than the surface of the silicide film 8 in the active region. The lowering results in deterioration of device characteristics due to the occurrence of leakage current. In FIG. 2, reference numeral 7 denotes a junction region, 9 an interlayer insulating film, and 10 a contact hole, respectively.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 세정 공정을 포함한 후속 공정에서 소자분리막의 표면 손실이 야기되는 것을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of preventing the surface loss of the device isolation film from being caused in a subsequent process including a cleaning process. have.
또한, 본 발명은 소자분리막의 표면 손실을 방지하여 안정적인 소자 특성을 확보할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of preventing the surface loss of the device isolation film to ensure stable device characteristics.
도 1a 및 도 1b는 종래의 STI 공정을 이용한 소자분리막 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a device isolation film using a conventional STI process.
도 2는 종래의 문제점을 설명하기 위한 단면도.2 is a cross-sectional view for explaining a conventional problem.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 소자분리막 형성방법을 설명하기 위한 공정별 단면도.3A to 3D are cross-sectional views of processes for describing a method of forming an isolation layer according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
31 : 실리콘 기판 32 : 패드산화막31 silicon substrate 32 pad oxide film
33 : 패드질화막 34 : 트렌치33: pad nitride film 34: trench
35 : HDP-산화막 36 : 질화막35: HDP-oxide film 36: nitride film
36a : 질화막 캡 37 : 감광막 패턴36a: nitride film cap 37: photosensitive film pattern
38 : 소자분리막38: device isolation film
상기와 같은 목적들을 달성하기 위하여, 본 발명은, 액티브 영역 및 필드 영역을 갖는 실리콘 기판 상에 패드산화막과 패드질화막을 차례로 형성하는 단계; 상기 패드질화막과 패드산화막을 패터닝하여 기판 필드 영역을 노출시키는 단계; 상기 노출된 기판 필드 영역을 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 산화막을 증착하는 단계; 상기 패드질화막이 노출될 때까지 상기 산화막을 CMP하는 단계; 상기 패드질화막을 제거하는 단계; 상기 기판 결과물 상에 질화막을 증착하는 단계; 및 상기 질화막을 식각하여 트렌치 내에 매립된 산화막 표면 상에 질화막 캡을 형성하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법을 제공한다.In order to achieve the above objects, the present invention comprises the steps of forming a pad oxide film and a pad nitride film on a silicon substrate having an active region and a field region; Patterning the pad nitride film and the pad oxide film to expose a substrate field region; Etching the exposed substrate field region to form a trench; Depositing an oxide film to fill the trench; CMPing the oxide film until the pad nitride film is exposed; Removing the pad nitride film; Depositing a nitride film on the substrate resultant; And forming a nitride film cap on the surface of the oxide film embedded in the trench by etching the nitride film.
여기서, 상기 질화막은 바람직하게 100∼300Å의 두께로 형성한다.The nitride film is preferably formed to a thickness of 100 to 300 kPa.
상기 질화막의 식각은 상기 질화막 상에 리버스 액티브 마스크를 사용하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 이용하여 노출된 질화막 부분을 식각하는 단계와, 상기 감광막 패턴을 제거하는 단계로 구성되며, 상기 감광막 패턴은 식각 프로파일을 고려하여 4000∼5000Å의 두께로 형성하고, 상기 질화막의 식각은 88∼90°의 슬로프를 유지하면서 질화막 대 산화막의 식각 선택비를 13:1로 유지시키는 다운 플로우(down flow) 방식으로 수행한다.The etching of the nitride layer may include forming a photoresist pattern on the nitride layer using a reverse active mask, etching the exposed portion of the nitride layer using the photoresist pattern, and removing the photoresist pattern. The photoresist pattern is formed to a thickness of 4000 to 5000 kPa in consideration of an etching profile, and the etching of the nitride film maintains an 88 to 90 ° slope while maintaining an etching selectivity ratio of the nitride film to the oxide film at 13: 1. flow).
본 발명에 따르면, 산화막의 CMP 후에 질화막의 증착 및 이에 대한 식각 공정을 추가 수행하여 소자분리막 표면에 질화막 캡을 형성시켜 줌으로써, 세정 공정을 포함한 일련의 후속 공정이 진행되는 동안 소자분리막의 표면 손실을 방지할 수 있으며, 그래서, 안정적인 소자 특성을 확보할 수 있다.According to the present invention, the nitride film cap is formed on the surface of the device isolation layer by further performing the deposition and etching process of the nitride film after the CMP of the oxide film, thereby reducing the surface loss of the device isolation film during a subsequent process including a cleaning process. It is possible to prevent and, thus, to secure stable device characteristics.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 소자분리막 형성방법을 설명하기 위한 공정별 단면도이다.3A to 3D are cross-sectional views of processes for describing a method of forming a device isolation film according to an embodiment of the present invention.
도 3a를 참조하면, 액티브 영역과 필드 영역을 갖는 실리콘 기판(31) 상에 각각 100∼150Å 및 1000∼2000Å의 두께로 패드산화막(32)과 패드질화막(33)을 차례로 형성한다. 그런다음, 공지의 공정에 따라 패드질화막(33)과 패드산화막(32)을 패터닝하여 필드 영역에 해당하는 기판 부분을 노출시킨 후, 노출된 기판 부분을 식각하여 소정 깊이의 트렌치(34)를 형성한다.Referring to FIG. 3A, the pad oxide film 32 and the pad nitride film 33 are sequentially formed on the silicon substrate 31 having the active region and the field region at a thickness of 100 to 150 microseconds and 1000 to 2000 microseconds, respectively. Then, the pad nitride film 33 and the pad oxide film 32 are patterned to expose a substrate portion corresponding to the field region according to a known process, and then the exposed substrate portion is etched to form a trench 34 having a predetermined depth. do.
이어서, 트렌치 식각시에 발생된 기판 데미지를 회복시키기 위해 상기 기판 결과물에 대해 희생 산화(Sacrificial oxidation) 공정을 수행하고, 연이어, 트렌치 상단 가장자리가 라운딩(rounding)지도록 월 산화(Wall oxidation) 공정을 수행한다.Subsequently, a sacrificial oxidation process is performed on the substrate resultant to recover the substrate damage generated during the trench etching, followed by a wall oxidation process so that the trench upper edge is rounded. do.
그 다음, 상기 단계까지의 기판 결과물 상에 트렌치(34)를 완전 매립하도록 트렌치 매립 산화막, 예컨데, HDP(High Density Plasma)-산화막(35)을 증착한 후, 패드질화막(33)이 노출될 때까지 상기 HDP-산화막(35)의 표면을 CMP한다.Then, after depositing a trench buried oxide film, for example, a high density plasma (HDP) -oxide film 35 to completely fill the trench 34 on the substrate resultant up to the step, when the pad nitride film 33 is exposed. CMP the surface of the HDP-oxide 35 until.
도 3b를 참조하면, 기판 트렌치 식각시에 식각 장벽으로 이용된 패드산화막을 식각 제거한다. 그런다음, 기판 결과물 상에 질화막(36)을 증착한다. 이때, 상기 질화막(36)은 그 자신을 포함한 최종 소자분리막의 높이가 크게 높아지지 않도록 100∼300Å 정도의 두께로 증착한다. 이것은 후속 공정에서 폴리 스트링거(poly stringer)를 방지하기 위함이다.Referring to FIG. 3B, the pad oxide layer used as the etch barrier during the etching of the substrate trench is etched away. Then, a nitride film 36 is deposited on the substrate output. At this time, the nitride film 36 is deposited to a thickness of about 100 to about 300 kPa so that the height of the final device isolation film including itself is not significantly increased. This is to prevent poly stringers in subsequent processes.
도 3c를 참조하면, 트렌치 내에 매립된 산화막(35) 상의 질화막 부분 상에 감광막 패턴(37)을 형성한다. 이때, 상기 감광막 패턴(37)은 식각 프로파일을 고려하여 4000∼5000Å의 두께로 형성하며, 바람직하게 리버스 액티브 마스크(reverse active mask)를 사용하여 형성한다.Referring to FIG. 3C, a photosensitive film pattern 37 is formed on the nitride film portion on the oxide film 35 embedded in the trench. In this case, the photoresist pattern 37 is formed to have a thickness of 4000 to 5000 하여 in consideration of an etching profile, and preferably is formed using a reverse active mask.
도 3d를 참조하면, 감광막 패턴을 식각 장벽으로 이용해서 상기 감광막 패턴에 의해 가려지지 않은 질화막 부분을 선택적으로 식각하고, 이를 통해, 트렌치 내에 매립된 산화막 상에 질화막 캡(36a)을 형성함으로써 최종적인 소자분리막(37)의 형성을 완성한다. 이때, 상기 질화막의 식각은 88∼90°의 슬로프를 유지하도록 수행하며, 아울러, 질화막 대 산화막의 최대 식각 선택비가 3:1 정도가 되는 플라즈마 방식이 아니라 질화막 대 산화막의 식각 선택비를 13:1로 유지시키는 다운 플로우(down flow) 방식으로 수행한다.Referring to FIG. 3D, the photoresist pattern is used as an etch barrier to selectively etch portions of the nitride film not covered by the photoresist pattern, thereby forming a nitride film cap 36a on the oxide film embedded in the trench. The formation of the device isolation film 37 is completed. In this case, the etching of the nitride film is performed to maintain a slope of 88 to 90 °, and the etching selectivity of the nitride film to the oxide film is 13: 1, not the plasma method in which the maximum etching selectivity of the nitride film to the oxide film is about 3: 1. It is performed in a down flow manner that is maintained as.
여기서, 상기 질화막 캡(36a)은 산화막의 CMP 후 세정 공정을 포함한 후속 공정이 진행되는 동안 산화막, 즉, 소자분리막의 표면 손실이 일어나는 것을 방지하도록 기능하므로, 소자분리막 형성 이후의 후속 공정에 의해 소자분리막의 표면이 액티브 영역의 실리사이드막 표면 보다 낮아지는 현상을 방지할 수 있으며, 그래서, 접합 누설과 같은 소자 특성 저하가 일어나는 것을 억제시킬 수 있다.Here, the nitride film cap 36a functions to prevent the surface loss of the oxide film, that is, the device isolation film, during the subsequent process including the cleaning process after the CMP of the oxide film. The phenomenon in which the surface of the separator becomes lower than the surface of the silicide film in the active region can be prevented, so that deterioration of device characteristics such as junction leakage can be suppressed.
이상에서와 같이, 본 발명은 산화막의 CMP 후에 질화막의 증착 및 이에 대한 식각 공정을 추가 수행하여 소자분리막 표면에 질화막 캡을 형성시켜 줌으로써, 상기 질화막 캡에 의해 세정 공정을 포함한 일련의 후속 공정이 진행되는 동안 소자분리막의 표면 손실을 방지할 수 있으며, 그래서, 접합 누설을 방지할 수 있는 바, 소자 특성을 향상시킬 수 있다.As described above, according to the present invention, the nitride film cap is formed on the surface of the device isolation layer by further performing a deposition process and an etching process of the nitride film after the CMP of the oxide film. Surface loss of the device isolation film can be prevented during the process, so that the junction leakage can be prevented, thereby improving the device characteristics.
한편, 전술한 본 발명의 실시예는 예시의 목적을 위해 개시된 것이므로, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경 및 부가 등이 가능할 것이며, 따라서, 이러한 수정 및 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.On the other hand, since the embodiments of the present invention described above are for the purpose of illustration, various modifications, changes, and additions will be possible to those skilled in the art within the spirit and scope of the present invention, and therefore, such modifications and changes are claimed It should be seen as belonging to a range.
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