KR20010057685A - Pre-metal dielectric layer forming method of semiconductor device - Google Patents
Pre-metal dielectric layer forming method of semiconductor device Download PDFInfo
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- KR20010057685A KR20010057685A KR1019990061058A KR19990061058A KR20010057685A KR 20010057685 A KR20010057685 A KR 20010057685A KR 1019990061058 A KR1019990061058 A KR 1019990061058A KR 19990061058 A KR19990061058 A KR 19990061058A KR 20010057685 A KR20010057685 A KR 20010057685A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자의 제조 공정중 반도체 소자가 형성된 실리콘웨이퍼와 반도체 소자의 금속 배선층 사이를 전기적으로 절연하기 위한 반도체 소자의 금속전 절연막(pre-metal dielectric layer)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a metal insulating film of a semiconductor device for electrically insulating between a silicon wafer on which a semiconductor device is formed and a metal wiring layer of a semiconductor device during a semiconductor device manufacturing process. to a method of forming a metal dielectric layer.
일반적으로 반도체 소자를 제조하는 공정에서 모스 소자가 형성된 실리콘웨이퍼와 금속 배선층 사이를 전기적으로 절연하기 위한 금속전 절연막은 산화막을 증착하여 형성하게 되는 데, 산화막의 증착시 금속 배선층 형성 이전의 평탄화, 나트륨 이온(Na+) 게터링(gettering) 등의 목적으로 붕소(B)나 인(P)을 함유하는 반응물을 첨가하여 SiO2-B2O3-P2O5의 BPSG(borophosphosilicate glass)막을 형성하고 있다.Generally, in the process of manufacturing a semiconductor device, a metal pre-insulating layer for electrically insulating between a silicon wafer on which a MOS device is formed and a metal wiring layer is formed by depositing an oxide film. Forming a BPSG (borophosphosilicate glass) film of SiO 2 -B 2 O 3 -P 2 O 5 by adding a reactant containing boron (B) or phosphorus (P) for purposes such as ions (Na + ) gettering Doing.
그러면, 도 1a와 도 1b를 참조하여 종래 반도체 소자의 금속전 절연막을 형성하는 방법을 개략적으로 설명한다.1A and 1B, a method of forming a metal pre-insulating layer of a conventional semiconductor device will be described.
먼저 도 1a에 도시한 바와 같이, LOCOS(local oxidation of silicon) 방법이나 STI(shallow trench isolation) 방법 등에 의해 소자 분리 영역(2)이 정의된 실리콘웨이퍼(1)의 소자 영역에 게이트(G), 소스(S), 드레인(D)을 포함하는 N모스 또는 P모스 트랜지스터를 형성한다. 그리고, N모스 또는 P모스 트랜지스터의 역활을 위해 티타늄 박막의 증착 및 샐리사이드 형성 공정을 진행한 이후, 실리콘웨이퍼(1)에 바로 BPSG막이 접촉할 경우 불순물인 붕소나 인이 실리콘에 침투할 수가 있으므로 플라즈마 화학 기상 증착(plasma-enhanced chemical vapor deposition)에 의해 실리콘웨이퍼(1) 전면에 불순물이 도핑되지 않은 라이너 산화막 또는 라이너 질화막(3)을 증착한다.First, as shown in FIG. 1A, the gate G is formed in the device region of the silicon wafer 1 in which the device isolation region 2 is defined by a local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) method. An N-MOS or P-MOS transistor including a source S and a drain D is formed. In addition, since the BPSG film is directly contacted with the silicon wafer 1 after the deposition of the titanium thin film and the salicide forming process for the role of the NMOS or PMOS transistor, boron or phosphorus as impurities may penetrate into the silicon. A liner oxide film or a liner nitride film 3 which is not doped with impurities is deposited on the entire surface of the silicon wafer 1 by plasma-enhanced chemical vapor deposition.
그 다음 도 1b에 도시한 바와 같이, 라이너 산화막 또는 라이너 질화막(3) 상부에 금속 배선층 형성 이전의 평탄화, 나트륨 이온 게터링 등의 목적으로 TEOS(tetraethylorthosilicate)계 BPSG막(4)을 증착하고 화학 기계적 연마(chemical mechanical deposition) 공정에 의해 평탄화한다.Then, as shown in FIG. 1B, a tetraethylorthosilicate (TEOS) -based BPSG film 4 is deposited on the liner oxide film or the liner nitride film 3 for the purpose of planarization, sodium ion gettering, or the like before forming the metal wiring layer. Planarization is carried out by a chemical mechanical deposition process.
이와 같은 종래의 방법에서 라이너 산화막 또는 라이너 질화막(3)의 플라즈마 화학 증착시 반응 가스로 실란 가스(SiH4)을 이용하게 되는 데, 이때 플라즈마 화학 기상 증착에서 많은 양의 실란 가스를 사용하게 되어 라이너 산화막 또는 라이너 질화막(3)의 수소 함유량이 높아지게 된다.In such a conventional method, silane gas (SiH 4 ) is used as a reaction gas during plasma chemical vapor deposition of the liner oxide film or liner nitride film 3, whereby a large amount of silane gas is used in plasma chemical vapor deposition. The hydrogen content of the oxide film or liner nitride film 3 becomes high.
그리고, 라이너 산화막 또는 라이너 질화막(3)의 수소 함유량이 높아짐으로 인하여 반도체 소자의 전기적 특성이 저하된다.In addition, due to an increase in the hydrogen content of the liner oxide film or the liner nitride film 3, the electrical characteristics of the semiconductor device are degraded.
또한, 상부 BPSG막(4)의 보론과 인의 불순물이 하부로 침투하고, 스트레스 안정성(stability)이 저하됨으로 인하여 반도체 소자의 전기적 신뢰성에 큰 영향을 줄 수 있다.In addition, since impurities of boron and phosphorus in the upper BPSG film 4 penetrate downward, and the stress stability is lowered, it may greatly affect the electrical reliability of the semiconductor device.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 반도체 소자가 형성된 실리콘웨이퍼와 금속 배선층 사이를 전기적으로 절연하기 위한 BPSG막의 하부에 형성되는 라이너 박막의 수소 함유량을 최소화하는 반도체 소자의 금속전 절연막을 형성하는 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a metal field of a semiconductor device which minimizes the hydrogen content of a liner thin film formed under the BPSG film for electrically insulating between the silicon wafer on which the semiconductor device is formed and the metal wiring layer. There is provided a method of forming an insulating film.
도 1a와 도 1b는 종래 반도체 소자의 금속전 절연막 형성 방법을 개략적으로 도시한 공정도이고,1A and 1B are process diagrams schematically illustrating a method of forming a pre-metal insulating layer of a conventional semiconductor device.
도 2a와 도 2b는 본 발명의 일 실시예에 따라 반도체 소자의 금속전 절연막 형성 방법을 개략적으로 도시한 공정도이다.2A and 2B are process diagrams schematically illustrating a method of forming a pre-metal insulating layer of a semiconductor device according to an exemplary embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 BPSG막 하부에 라이너 산화막 또는 라이너 질화막에 비해 상대적으로 수소 함유량이 적은 라이너 산질화막을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized by forming a liner oxynitride film having a lower hydrogen content than the liner oxide film or liner nitride film under the BPSG film.
따라서, 본 발명은 실리콘웨이퍼의 소자 영역에 게이트, 소스, 드레인을 포함하는 모스 소자를 형성하고, 모스 소자를 포함한 실리콘웨이퍼 상부에 라이너 산질화막을 형성한다. 이후, 라이너 산질화막 상부에 BPSG막을 증착하고 평탄화하여 반도체 소자의 금속전 절연막을 완성한다.Accordingly, the present invention forms a MOS device including a gate, a source, a drain in the device region of the silicon wafer, and a liner oxynitride film is formed on the silicon wafer including the MOS device. Thereafter, a BPSG film is deposited and planarized on the liner oxynitride film to complete the metal pre-insulating film of the semiconductor device.
또한, 본 발명은 모스 소자를 포함한 실리콘웨이퍼 상부에 라이너 산질화막을 형성하기 이전에, 모스 소자의 게이트, 소스, 드레인 상부에 실리사이드를 형성하고, 라이너 산질화막 형성 이후 BPSG막을 증착한다.In addition, before the liner oxynitride film is formed on the silicon wafer including the MOS device, silicide is formed on the gate, the source, and the drain of the MOS device, and the BPSG film is deposited after the liner oxynitride film is formed.
상기에서 라이너 산질화막의 형성은 플라즈마 화학 기상 증착에 의해 증착하는 것이 바람직하다.Formation of the liner oxynitride film in the above is preferably deposited by plasma chemical vapor deposition.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a와 도 2b는 본 발명의 일 실시예에 따라 반도체 소자의 금속전 절연막을 형성하는 방법을 개략적으로 도시한 공정도이다.2A and 2B are process diagrams schematically illustrating a method of forming a metal pre-insulating layer of a semiconductor device according to an embodiment of the present invention.
먼저 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11)에 LOCOS 방법이나 STI 방법 등에 의해 소자 분리 영역(12)을 정의한다. 그리고, 소자 분리 영역(12)이 정의된 실리콘웨이퍼(11)의 소자 영역에 게이트(G), 소스(S), 드레인(D)을 포함하는 N모스 또는 P모스 트랜지스터를 형성한다. 그리고, N모스 또는 P모스 트랜지스터의 역할을 위해 티타늄 박막의 증착 및 샐리사이드 형성 공정을 진행한 이후, 실리콘웨이퍼(11)에 바로 BPSG막이 접촉할 경우 불순물인 붕소나 인이 실리콘에 침투할 수가 있으므로 플라즈마 화학 기상 증착에 의해 라이너 산질화막(oxynitride layer)(13)을 증착한다. 산질화막은 산화막과 질화막의 중간적 성질을 갖는 것으로, 현재 원자외(deep UV) 노광을 위한 반사 방지막으로 주로 사용되고 있다. 이때, 라이너 산질화막(13) 증착을 위한 플라즈마 화학 기상 증착에서는 종래 라이너 산화막 또는 라이너 질화막 증착에 비해 반응 가스인 실란 가스의 공급량이 상대적으로 적으므로 수소 함유량이 낮은 라이너 박막을 형성하게 된다.First, as shown in FIG. 2A, the device isolation region 12 is defined in the silicon wafer 11 by the LOCOS method, the STI method, or the like. In addition, an NMOS or PMOS transistor including a gate G, a source S, and a drain D is formed in the device region of the silicon wafer 11 in which the device isolation region 12 is defined. After the process of depositing and salicide forming a titanium thin film for the role of an N-MOS or P-MOS transistor, boron or phosphorus as impurities may penetrate into silicon when the BPSG film directly contacts the silicon wafer 11. The liner oxynitride layer 13 is deposited by plasma chemical vapor deposition. The oxynitride film has an intermediate property between an oxide film and a nitride film, and is currently mainly used as an antireflection film for deep UV exposure. In this case, in the plasma chemical vapor deposition for the deposition of the liner oxynitride layer 13, since the supply amount of the silane gas, which is a reactive gas, is relatively smaller than that of the conventional liner oxide or liner nitride deposition, a liner thin film having a low hydrogen content is formed.
그 다음 도 2b에 도시한 바와 같이, 라이너 산질화막(13) 상부에 금속 배선층 형성 이전의 평탄화, 나트륨 이온 게터링 등의 목적으로 TEOS계 BPSG막(14)을 증착하고 화학 기계적 연마 공정에 의해 평탄화한다. 이때, BPSG막 하부에 종래 라이너 산화막 또는 라이너 질화막에 비해 상대적으로 수소 함유량이 적은 라이너 산질화막(13)이 형성되어 있으므로 BPSG막(14)의 불순물인 붕소나 인이 하부로 침투하는 것을 방지할 수 있을 뿐만 아니라 스트레스 안정성을 향상시킬 수 있어 모스 트랜지스터의 전기적 신뢰성을 향상시킨다. 또한, 후속 콘택 형성 공정을 위한 BPSG막(14)의 건식 식각시 라이너 산질화막(13)이 하드(hard) 마스크 역할을 수행하여 식각 정지용으로 사용되므로 종래 라이너 산화막 또는 라이너 질화막에 비해 BPSG막(14)에 대한 식각 선택비를 높여주므로 식각 공정 마진이 증가된다.Then, as shown in FIG. 2B, the TEOS-based BPSG film 14 is deposited on the liner oxynitride film 13 for the purpose of planarization before forming the metal wiring layer, sodium ion gettering, and the like, and planarization by a chemical mechanical polishing process. do. At this time, since the liner oxynitride film 13 having a relatively smaller hydrogen content than the conventional liner oxide film or the liner nitride film is formed below the BPSG film, boron or phosphorus, which is an impurity of the BPSG film 14, may be prevented from penetrating downward. In addition, the stress stability can be improved to improve the electrical reliability of the MOS transistor. In addition, since the liner oxynitride layer 13 serves as a hard mask during the dry etching of the BPSG layer 14 for the subsequent contact forming process, the liner oxynitride layer 13 serves as a hard mask so that the BPSG layer 14 may be used in comparison with the conventional liner oxide layer or the liner nitride layer. Increases the etching selectivity to), increasing the etching process margin.
이와 같이 본 발명은 금속전 절연막인 BPSG막 하부에 종래 라이너 산화막 또는 라이너 질화막에 비해 수소 함유량이 적은 라이너 산질화막을 형성함으로써 BPSG막의 불순물이 하부로 침투하는 것을 방지할 수 있을 뿐만 아니라 스트레스 안정성을 향상시킬 수 있어 반도체 소자의 전기적 신뢰성을 향상시킬 수 있다.As described above, the present invention forms a liner oxynitride film having a lower hydrogen content than the conventional liner oxide film or the liner nitride film under the BPSG film, which is a metal pre-insulating film, to prevent the impurities from the BPSG film from penetrating to the bottom and to improve stress stability. The electrical reliability of the semiconductor device can be improved.
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| KR1019990061058A KR20010057685A (en) | 1999-12-23 | 1999-12-23 | Pre-metal dielectric layer forming method of semiconductor device |
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| Country | Link |
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| KR (1) | KR20010057685A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587597B1 (en) * | 2002-10-31 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990012160A (en) * | 1997-07-28 | 1999-02-25 | 윤종용 | Morse element having a source / drain silicide and a method of manufacturing the same |
| WO1999010924A1 (en) * | 1997-08-25 | 1999-03-04 | Advanced Micro Devices, Inc. | Reduction of charge loss in nonvolatile memory cells by phosphorous implantation into pecvd nitride/oxynitride films |
| WO1999016118A1 (en) * | 1997-09-25 | 1999-04-01 | Advanced Micro Devices, Inc. | Process for fabricating semiconductor device including antireflective etch stop layer |
-
1999
- 1999-12-23 KR KR1019990061058A patent/KR20010057685A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990012160A (en) * | 1997-07-28 | 1999-02-25 | 윤종용 | Morse element having a source / drain silicide and a method of manufacturing the same |
| WO1999010924A1 (en) * | 1997-08-25 | 1999-03-04 | Advanced Micro Devices, Inc. | Reduction of charge loss in nonvolatile memory cells by phosphorous implantation into pecvd nitride/oxynitride films |
| WO1999016118A1 (en) * | 1997-09-25 | 1999-04-01 | Advanced Micro Devices, Inc. | Process for fabricating semiconductor device including antireflective etch stop layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587597B1 (en) * | 2002-10-31 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
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