KR20040004927A - 반도체 장치의 평탄막 형성방법 - Google Patents
반도체 장치의 평탄막 형성방법 Download PDFInfo
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- KR20040004927A KR20040004927A KR1020020039159A KR20020039159A KR20040004927A KR 20040004927 A KR20040004927 A KR 20040004927A KR 1020020039159 A KR1020020039159 A KR 1020020039159A KR 20020039159 A KR20020039159 A KR 20020039159A KR 20040004927 A KR20040004927 A KR 20040004927A
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- 238000000034 method Methods 0.000 title claims abstract description 110
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 52
- 239000011229 interlayer Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims description 34
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 238000001039 wet etching Methods 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 230000000153 supplemental effect Effects 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 2
- 239000005001 laminate film Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 13
- 238000010438 heat treatment Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (18)
- 표면에 요철구조를 가진 반도체 기판 상에 표면이 평탄한 층간막을 형성하는 방법에 있어서,상기 반도체 기판 상에 상기 요철구조의 프로파일을 따른 표면굴곡을 가진 층간막을 형성하는 단계;상기 층간막 철부의 평탄 영역을 대략적으로 소정의 깊이(h : h는 1이상의 양의 실수)로 제거하기 위하여 상기 평탄영역을 제외한 나머지 영역 상에 h/n(여기서 n은 1이상의 양의 실수) 이상의 두께를 가진 포토레지스트 패턴을 형성하는 단계;상기 평탄영역의 에지로부터 상기 평탄영역 둘레의 경사영역에 걸쳐서 위치한 포토레지스트 패턴의 두께를 h/n 이하로 하기 위하여 상기 포토레지스트 패턴을 리플로우시키는 단계; 및상기 포토레지스트 패턴과 상기 층간막의 식각 선택비가 1:n인 에천트를 사용하여 상기 층간막을 h만큼 식각하는 단계를 구비한 것을 특징으로 하는 평탄막의 형성방법.
- 제 1 항에 있어서, 상기 층간막은 BPSG, TEOS, TOSZ막 및 이들의 조합 적층막 중 어느 하나인 것을 특징으로 하는 평탄막의 형성방법.
- 제 1항에 있어서, 상기 포토레지스트 패턴의 리플로우 공정은 포토장비에서 수행되는 것을 특징으로 하는 평탄막 형성방법.
- 제 1 항에 있어서, 상기 포토레지스트 패턴의 리플로우 공정은 식각장비에서 수행되는 것을 특징으로 하는 평탄막 형성방법.
- 제 1 항에 있어서, 상기 층간막의 두께는 5,000~30,000Å인 것을 특징으로 하는 평탄막 형성방법.
- 제 1 항에 있어서, 상기 식각공정 후,상기 남은 포토레지스트 패턴을 제거하는 단계; 및상기 경사영역 상에 잔존하는 필라를 식각하여 표면을 평탄하게 하는 단계를 더 구비하는 것을 특징으로 하는 평탄막 형성방법.
- 제 6 항에 있어서, 상기 잔존 필라의 식각공정은 화학 기계적 연마공정, 습식식각공정 또는 에치백 공정에 의해 수행되는 것을 특징으로 하는 평탄막 형성방법.
- 제 7 항에 있어서, 상기 필라를 제거한 후 상기 층간막과 동일 물질의 보충막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 평탄막 형성방법.
- 제 1 항에 있어서, 상기 식각공정은 이방성 식각공정인 것을 특징으로 하는 평탄막 형성방법.
- 반도체 기판 상에 셀영역과 주변영역을 가지며, 상기 셀영역에는 주변영역에 비해 상대적으로 매우 높은 높이를 가진 캐패시터 패턴이 형성된 반도체 장치에 있어서,상기 반도체 기판 상에 절연막을 소정 두께로 형성하는 단계;상기 셀영역에서 상기 절연막 철부의 평탄 영역을 소정 깊이 (h(여기서 h는 양의 실수)로 제거하기 위하여, 상기 평탄영역을 제외한 나머지 셀영역 및 주변영역 상에 h/n(여기서 n은 1이상의 양의 실수) 이상의 두께를 가진 포토 레지스트 패턴을 형성하는 단계;상기 평탄영역의 에지로부터 상기 평탄영역 둘레의 경사영역에 걸쳐서 위치한 포토레지스트 패턴의 두께를 h/n 이하로 하기 위하여 상기 포토레지스트 패턴을 리플로우시키는 단계; 및상기 포토레지스트 패턴과 상기 절연막의 식각 선택비가 1:n인 에천트를 사용하여 노출된 절연막을 절대단차 h만큼 식각하는 단계를 구비한 것을 특징으로 하는 평탄막의 형성방법.
- 제 10 항에 있어서, 상기 절연막은 BPSG, TEOS, TOSZ막 및 이들의 조합 적층막 중 어느 하나인 것을 특징으로 하는 평탄막의 형성방법.
- 제 10 항에 있어서, 상기 포토레지스트 패턴의 리플로우 공정은 포토장비에서 수행되는 것을 특징으로 하는 평탄막 형성방법.
- 제 10 항에 있어서, 상기 포토레지스트 패턴의 리플로우 공정은 식각장비에서 수행되는 것을 특징으로 하는 평탄막 형성방법.
- 제 10 항에 있어서, 상기 절연막의 두께는 5,000~30,000Å인 것을 특징으로 하는 평탄막 형성방법.
- 제 10 항에 있어서, 상기 식각공정 후,상기 남은 포토레지스트 패턴을 제거하는 단계; 및상기 경사영역 상에 잔존하는 필라를 식각하여 표면을 평탄하게 하는 단계를 더 구비하는 것을 특징으로 하는 평탄막 형성방법.
- 제 15 항에 있어서, 상기 잔존 필라의 식각공정은 화학 기계적 연마공정, 습식식각공정 또는 에치백 공정에 의해 수행되는 것을 특징으로 하는 평탄막 형성방법.
- 제 16 항에 있어서, 상기 필라를 제거한 후 상기 절연막과 동일 물질의 부가 절연막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 평탄막 형성방법.
- 제 10 항에 있어서, 상기 식각공정은 이방성 식각공정인 것을 특징으로 하는 평탄막 형성방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0039159A KR100445707B1 (ko) | 2002-07-06 | 2002-07-06 | 반도체 장치의 평탄막 형성방법 |
US10/464,645 US7008755B2 (en) | 2002-07-06 | 2003-06-19 | Method for forming a planarized layer of a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2002-0039159A KR100445707B1 (ko) | 2002-07-06 | 2002-07-06 | 반도체 장치의 평탄막 형성방법 |
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KR20040004927A true KR20040004927A (ko) | 2004-01-16 |
KR100445707B1 KR100445707B1 (ko) | 2004-08-21 |
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KR10-2002-0039159A KR100445707B1 (ko) | 2002-07-06 | 2002-07-06 | 반도체 장치의 평탄막 형성방법 |
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US (1) | US7008755B2 (ko) |
KR (1) | KR100445707B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100513798B1 (ko) * | 2003-06-30 | 2005-09-13 | 주식회사 하이닉스반도체 | 유동성 절연막의 평탄화 특성을 개선한 반도체 소자의제조방법 |
Families Citing this family (9)
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KR100828029B1 (ko) * | 2006-12-11 | 2008-05-08 | 삼성전자주식회사 | 스택형 반도체 장치의 제조 방법 |
JP2011082223A (ja) * | 2009-10-02 | 2011-04-21 | Renesas Electronics Corp | 半導体集積回路装置 |
JP2011210916A (ja) * | 2010-03-30 | 2011-10-20 | Mitsumi Electric Co Ltd | 半導体装置の製造方法 |
KR20120095693A (ko) * | 2011-02-21 | 2012-08-29 | 삼성전자주식회사 | 평탄화된 절연막들을 구비하는 반도체 소자 및 그 제조방법 |
CN107255905A (zh) * | 2012-01-27 | 2017-10-17 | 旭化成株式会社 | 干式蚀刻用热反应型抗蚀剂材料、模具的制造方法及模具 |
JP2016058599A (ja) * | 2014-09-11 | 2016-04-21 | キヤノン株式会社 | 撮像装置の製造方法 |
CN110349855B (zh) * | 2018-04-03 | 2021-11-26 | 华邦电子股份有限公司 | 半导体装置的制造方法 |
TWI660404B (zh) * | 2018-04-03 | 2019-05-21 | 華邦電子股份有限公司 | 半導體裝置的製造方法 |
KR20210052997A (ko) * | 2019-11-01 | 2021-05-11 | 삼성전자주식회사 | 반도체 소자 및 그 형성 방법 |
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JPH06177351A (ja) * | 1992-12-02 | 1994-06-24 | Toshiba Corp | 半導体装置の製造方法 |
US5872060A (en) * | 1995-11-02 | 1999-02-16 | Texas Instruments Incorporated | Semiconductor device manufacturing method |
KR970052834A (ko) | 1995-12-23 | 1997-07-29 | 김주용 | 반도체 소자의 글로벌 단차 완화 방법 |
JPH10284702A (ja) | 1997-04-09 | 1998-10-23 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
KR20010086625A (ko) | 2000-02-15 | 2001-09-15 | 윤종용 | 반도체 메모리 소자의 층간절연막 평탄화 방법 |
KR20020011814A (ko) | 2000-08-04 | 2002-02-09 | 윤종용 | 반도체 소자의 절연막 평탄화 방법 |
JP3976598B2 (ja) * | 2002-03-27 | 2007-09-19 | Nec液晶テクノロジー株式会社 | レジスト・パターン形成方法 |
-
2002
- 2002-07-06 KR KR10-2002-0039159A patent/KR100445707B1/ko active IP Right Grant
-
2003
- 2003-06-19 US US10/464,645 patent/US7008755B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100513798B1 (ko) * | 2003-06-30 | 2005-09-13 | 주식회사 하이닉스반도체 | 유동성 절연막의 평탄화 특성을 개선한 반도체 소자의제조방법 |
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Publication number | Publication date |
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KR100445707B1 (ko) | 2004-08-21 |
US20040005518A1 (en) | 2004-01-08 |
US7008755B2 (en) | 2006-03-07 |
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