KR20020059851A - 웨이퍼 레벨에서 형성된 집적 회로 패키지 - Google Patents

웨이퍼 레벨에서 형성된 집적 회로 패키지 Download PDF

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Publication number
KR20020059851A
KR20020059851A KR1020027007432A KR20027007432A KR20020059851A KR 20020059851 A KR20020059851 A KR 20020059851A KR 1020027007432 A KR1020027007432 A KR 1020027007432A KR 20027007432 A KR20027007432 A KR 20027007432A KR 20020059851 A KR20020059851 A KR 20020059851A
Authority
KR
South Korea
Prior art keywords
integrated circuit
bonding pads
wafer
metalized
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020027007432A
Other languages
English (en)
Korean (ko)
Inventor
람켄엠
Original Assignee
페레고스 조지, 마이크 로스
아트멜 코포레이숀
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 페레고스 조지, 마이크 로스, 아트멜 코포레이숀 filed Critical 페레고스 조지, 마이크 로스
Publication of KR20020059851A publication Critical patent/KR20020059851A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings

Landscapes

  • Wire Bonding (AREA)
KR1020027007432A 1999-12-14 2000-12-11 웨이퍼 레벨에서 형성된 집적 회로 패키지 Withdrawn KR20020059851A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/460,902 US6388335B1 (en) 1999-12-14 1999-12-14 Integrated circuit package formed at a wafer level
US09/460,902 1999-12-14
PCT/US2000/042765 WO2001045167A2 (en) 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level

Publications (1)

Publication Number Publication Date
KR20020059851A true KR20020059851A (ko) 2002-07-13

Family

ID=23830502

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020027007432A Withdrawn KR20020059851A (ko) 1999-12-14 2000-12-11 웨이퍼 레벨에서 형성된 집적 회로 패키지

Country Status (10)

Country Link
US (2) US6388335B1 (https=)
EP (1) EP1238427A2 (https=)
JP (1) JP2004537841A (https=)
KR (1) KR20020059851A (https=)
CN (1) CN1217410C (https=)
CA (1) CA2392837A1 (https=)
MY (1) MY135942A (https=)
NO (1) NO20022792L (https=)
TW (1) TW490822B (https=)
WO (1) WO2001045167A2 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098407B2 (en) 2003-08-23 2006-08-29 Samsung Electronics Co., Ltd. Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate
US7268303B2 (en) 2002-10-11 2007-09-11 Seiko Epson Corporation Circuit board, mounting structure of ball grid array, electro-optic device and electronic device
KR101080629B1 (ko) * 2003-07-01 2011-11-08 프리스케일 세미컨덕터, 인크. 활성화 플레이트를 사용하여 집적 회로들의 무전해 및 침지도금

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US6078100A (en) 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
US7102892B2 (en) * 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US6487078B2 (en) * 2000-03-13 2002-11-26 Legacy Electronics, Inc. Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
US6713854B1 (en) 2000-10-16 2004-03-30 Legacy Electronics, Inc Electronic circuit module with a carrier having a mounting pad array
KR100440507B1 (ko) * 2000-03-23 2004-07-15 세이코 엡슨 가부시키가이샤 반도체장치 및 그 제조방법, 회로기판 및 전자기기
US6281046B1 (en) * 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
US7337522B2 (en) * 2000-10-16 2008-03-04 Legacy Electronics, Inc. Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
US6524885B2 (en) * 2000-12-15 2003-02-25 Eaglestone Partners I, Llc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
WO2002074024A2 (en) * 2001-03-14 2002-09-19 Legacy Electronics, Inc. A method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
TW523857B (en) * 2001-12-06 2003-03-11 Siliconware Precision Industries Co Ltd Chip carrier configurable with passive components
US6492196B1 (en) * 2002-01-07 2002-12-10 Picta Technology Inc. Packaging process for wafer level IC device
US6800948B1 (en) * 2002-07-19 2004-10-05 Asat Ltd. Ball grid array package
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
US6987032B1 (en) * 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
KR100512971B1 (ko) * 2003-02-24 2005-09-07 삼성전자주식회사 솔더볼을 이용한 마이크로 전자 기계 시스템의 제조 방법
JP2004335915A (ja) * 2003-05-12 2004-11-25 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP4130158B2 (ja) * 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7073702B2 (en) * 2003-10-17 2006-07-11 International Business Machines Corporation Self-locking wire bond structure and method of making the same
KR100676493B1 (ko) * 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
US7435097B2 (en) * 2005-01-12 2008-10-14 Legacy Electronics, Inc. Radial circuit board, system, and methods
US8610262B1 (en) 2005-02-18 2013-12-17 Utac Hong Kong Limited Ball grid array package with improved thermal characteristics
US7245013B2 (en) * 2005-07-26 2007-07-17 Infineon Technologies Ag Substrate based IC-package
AT9551U1 (de) * 2006-05-16 2007-11-15 Austria Tech & System Tech Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil
US7824965B2 (en) 2007-08-07 2010-11-02 Skyworks Solutions, Inc. Near chip scale package integration process
US8581403B2 (en) * 2008-01-30 2013-11-12 Nec Corporation Electronic component mounting structure, electronic component mounting method, and electronic component mounting board
CN101572257B (zh) * 2008-04-30 2011-02-16 南茂科技股份有限公司 芯片封装卷带及包含该芯片封装卷带的芯片封装结构
TWI387067B (zh) * 2009-03-17 2013-02-21 南茂科技股份有限公司 無基板晶片封裝及其製造方法
US8367475B2 (en) * 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
TWI487042B (zh) * 2012-10-18 2015-06-01 旭德科技股份有限公司 封裝製程
WO2017066930A1 (en) * 2015-10-21 2017-04-27 GM Global Technology Operations LLC Systems and methods for reinforced adhesive bonding using textured solder elements
US11064615B2 (en) 2019-09-30 2021-07-13 Texas Instruments Incorporated Wafer level bump stack for chip scale package

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US4056681A (en) * 1975-08-04 1977-11-01 International Telephone And Telegraph Corporation Self-aligning package for integrated circuits
US5504035A (en) 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
KR920022482A (ko) * 1991-05-09 1992-12-19 가나이 쯔도무 전자부품 탑재모듈
KR950012658B1 (ko) * 1992-07-24 1995-10-19 삼성전자주식회사 반도체 칩 실장방법 및 기판 구조체
US5734201A (en) * 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5543585A (en) * 1994-02-02 1996-08-06 International Business Machines Corporation Direct chip attachment (DCA) with electrically conductive adhesives
US5539153A (en) * 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
JP2581017B2 (ja) * 1994-09-30 1997-02-12 日本電気株式会社 半導体装置及びその製造方法
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5851845A (en) 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
JP3345541B2 (ja) * 1996-01-16 2002-11-18 株式会社日立製作所 半導体装置及びその製造方法
JP2842361B2 (ja) * 1996-02-28 1999-01-06 日本電気株式会社 半導体装置
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
US5604160A (en) 1996-07-29 1997-02-18 Motorola, Inc. Method for packaging semiconductor devices
US5798557A (en) 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
KR100222299B1 (ko) 1996-12-16 1999-10-01 윤종용 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법
DE19702186C2 (de) * 1997-01-23 2002-06-27 Fraunhofer Ges Forschung Verfahren zur Gehäusung von integrierten Schaltkreisen
US6097098A (en) * 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
JP3176307B2 (ja) * 1997-03-03 2001-06-18 日本電気株式会社 集積回路装置の実装構造およびその製造方法
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US5972734A (en) * 1997-09-17 1999-10-26 Lsi Logic Corporation Interposer for ball grid array (BGA) package
JPH11214421A (ja) * 1997-10-13 1999-08-06 Matsushita Electric Ind Co Ltd 半導体素子の電極形成方法
JP2000036518A (ja) * 1998-07-16 2000-02-02 Nitto Denko Corp ウェハスケールパッケージ構造およびこれに用いる回路基板
US6081026A (en) * 1998-11-13 2000-06-27 Fujitsu Limited High density signal interposer with power and ground wrap
US6081429A (en) * 1999-01-20 2000-06-27 Micron Technology, Inc. Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods
US6281046B1 (en) * 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268303B2 (en) 2002-10-11 2007-09-11 Seiko Epson Corporation Circuit board, mounting structure of ball grid array, electro-optic device and electronic device
KR101080629B1 (ko) * 2003-07-01 2011-11-08 프리스케일 세미컨덕터, 인크. 활성화 플레이트를 사용하여 집적 회로들의 무전해 및 침지도금
US7098407B2 (en) 2003-08-23 2006-08-29 Samsung Electronics Co., Ltd. Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate

Also Published As

Publication number Publication date
NO20022792D0 (no) 2002-06-12
TW490822B (en) 2002-06-11
US6388335B1 (en) 2002-05-14
CN1217410C (zh) 2005-08-31
WO2001045167A2 (en) 2001-06-21
MY135942A (en) 2008-07-31
CN1409872A (zh) 2003-04-09
NO20022792L (no) 2002-06-12
JP2004537841A (ja) 2004-12-16
WO2001045167A3 (en) 2002-05-23
CA2392837A1 (en) 2001-06-21
EP1238427A2 (en) 2002-09-11
US6413799B1 (en) 2002-07-02

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Legal Events

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PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000