JP2004537841A - ウェハレベルで形成される集積回路パッケージ - Google Patents

ウェハレベルで形成される集積回路パッケージ Download PDF

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Publication number
JP2004537841A
JP2004537841A JP2001545366A JP2001545366A JP2004537841A JP 2004537841 A JP2004537841 A JP 2004537841A JP 2001545366 A JP2001545366 A JP 2001545366A JP 2001545366 A JP2001545366 A JP 2001545366A JP 2004537841 A JP2004537841 A JP 2004537841A
Authority
JP
Japan
Prior art keywords
bonding pads
layer
wafer
integrated circuit
metallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001545366A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004537841A5 (https=
Inventor
ラム，ケン・エム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of JP2004537841A publication Critical patent/JP2004537841A/ja
Publication of JP2004537841A5 publication Critical patent/JP2004537841A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings

Landscapes

  • Wire Bonding (AREA)
JP2001545366A 1999-12-14 2000-12-11 ウェハレベルで形成される集積回路パッケージ Withdrawn JP2004537841A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/460,902 US6388335B1 (en) 1999-12-14 1999-12-14 Integrated circuit package formed at a wafer level
PCT/US2000/042765 WO2001045167A2 (en) 1999-12-14 2000-12-11 Integrated circuit package formed at a wafer level

Publications (2)

Publication Number Publication Date
JP2004537841A true JP2004537841A (ja) 2004-12-16
JP2004537841A5 JP2004537841A5 (https=) 2005-03-17

Family

ID=23830502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001545366A Withdrawn JP2004537841A (ja) 1999-12-14 2000-12-11 ウェハレベルで形成される集積回路パッケージ

Country Status (10)

Country Link
US (2) US6388335B1 (https=)
EP (1) EP1238427A2 (https=)
JP (1) JP2004537841A (https=)
KR (1) KR20020059851A (https=)
CN (1) CN1217410C (https=)
CA (1) CA2392837A1 (https=)
MY (1) MY135942A (https=)
NO (1) NO20022792L (https=)
TW (1) TW490822B (https=)
WO (1) WO2001045167A2 (https=)

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US6487078B2 (en) * 2000-03-13 2002-11-26 Legacy Electronics, Inc. Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
US6713854B1 (en) 2000-10-16 2004-03-30 Legacy Electronics, Inc Electronic circuit module with a carrier having a mounting pad array
KR100440507B1 (ko) * 2000-03-23 2004-07-15 세이코 엡슨 가부시키가이샤 반도체장치 및 그 제조방법, 회로기판 및 전자기기
US6281046B1 (en) * 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
US7337522B2 (en) * 2000-10-16 2008-03-04 Legacy Electronics, Inc. Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
US6524885B2 (en) * 2000-12-15 2003-02-25 Eaglestone Partners I, Llc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
WO2002074024A2 (en) * 2001-03-14 2002-09-19 Legacy Electronics, Inc. A method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
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US6492196B1 (en) * 2002-01-07 2002-12-10 Picta Technology Inc. Packaging process for wafer level IC device
US6800948B1 (en) * 2002-07-19 2004-10-05 Asat Ltd. Ball grid array package
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
US6987032B1 (en) * 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
JP2004134648A (ja) * 2002-10-11 2004-04-30 Seiko Epson Corp 回路基板、ボール・グリッド・アレイの実装構造、及び電気光学装置、並びに電子機器
KR100512971B1 (ko) * 2003-02-24 2005-09-07 삼성전자주식회사 솔더볼을 이용한 마이크로 전자 기계 시스템의 제조 방법
JP2004335915A (ja) * 2003-05-12 2004-11-25 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP4130158B2 (ja) * 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
US6974776B2 (en) * 2003-07-01 2005-12-13 Freescale Semiconductor, Inc. Activation plate for electroless and immersion plating of integrated circuits
KR100541394B1 (ko) 2003-08-23 2006-01-10 삼성전자주식회사 비한정형 볼 그리드 어레이 패키지용 배선기판 및 그의제조 방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7073702B2 (en) * 2003-10-17 2006-07-11 International Business Machines Corporation Self-locking wire bond structure and method of making the same
KR100676493B1 (ko) * 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
US7435097B2 (en) * 2005-01-12 2008-10-14 Legacy Electronics, Inc. Radial circuit board, system, and methods
US8610262B1 (en) 2005-02-18 2013-12-17 Utac Hong Kong Limited Ball grid array package with improved thermal characteristics
US7245013B2 (en) * 2005-07-26 2007-07-17 Infineon Technologies Ag Substrate based IC-package
AT9551U1 (de) * 2006-05-16 2007-11-15 Austria Tech & System Tech Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil
US7824965B2 (en) 2007-08-07 2010-11-02 Skyworks Solutions, Inc. Near chip scale package integration process
US8581403B2 (en) * 2008-01-30 2013-11-12 Nec Corporation Electronic component mounting structure, electronic component mounting method, and electronic component mounting board
CN101572257B (zh) * 2008-04-30 2011-02-16 南茂科技股份有限公司 芯片封装卷带及包含该芯片封装卷带的芯片封装结构
TWI387067B (zh) * 2009-03-17 2013-02-21 南茂科技股份有限公司 無基板晶片封裝及其製造方法
US8367475B2 (en) * 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
TWI487042B (zh) * 2012-10-18 2015-06-01 旭德科技股份有限公司 封裝製程
WO2017066930A1 (en) * 2015-10-21 2017-04-27 GM Global Technology Operations LLC Systems and methods for reinforced adhesive bonding using textured solder elements
US11064615B2 (en) 2019-09-30 2021-07-13 Texas Instruments Incorporated Wafer level bump stack for chip scale package

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Also Published As

Publication number Publication date
NO20022792D0 (no) 2002-06-12
TW490822B (en) 2002-06-11
US6388335B1 (en) 2002-05-14
CN1217410C (zh) 2005-08-31
WO2001045167A2 (en) 2001-06-21
MY135942A (en) 2008-07-31
CN1409872A (zh) 2003-04-09
NO20022792L (no) 2002-06-12
WO2001045167A3 (en) 2002-05-23
CA2392837A1 (en) 2001-06-21
KR20020059851A (ko) 2002-07-13
EP1238427A2 (en) 2002-09-11
US6413799B1 (en) 2002-07-02

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A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20080304