TW490822B - Integrated circuit package formed at a wafer level - Google Patents

Integrated circuit package formed at a wafer level Download PDF

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Publication number
TW490822B
TW490822B TW089126574A TW89126574A TW490822B TW 490822 B TW490822 B TW 490822B TW 089126574 A TW089126574 A TW 089126574A TW 89126574 A TW89126574 A TW 89126574A TW 490822 B TW490822 B TW 490822B
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Taiwan
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wafer
substrate
integrated circuit
openings
grain
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TW089126574A
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English (en)
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Ken M Lam
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Atmel Corp
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
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Description

490822 β 修正 五、發明說明⑴ 〜^一^3 【技術領域】 本發明係關於積體電 柵陣列積體封裝件。 放件,及特別是一種晶圓級球 【背景技術】 於一電路板上之一藉騁# 在板上所佔的面積。一、,二,封裝件的覆蓋區是這封裝件 封裝件放置地更緊密。^二需要將覆蓋區最小化以及將 顯現為一更流行的封裝件型^球柵陣列(BGA)封裝件已 覆蓋區、及較短電路徑,咅二^因為其提供高密度、最小 封裝件較佳的效能。工思明/、具有比先前型式的半導體 典型的B G A (球栅陣列)封,杜一 件110,-積體電路晶粒12 2WHf圖9 °桃A封裝 材料製造之基部之上表面i 12θ之上/八接劑被安裝於—基板 引線12G以形成於基部112 孟屬結合線或線結合 形成於晶粒i 2 2之上表面之複數表:上線曰結合塾1 2 8電連接 112包括電鍍穿孔通路118及金屬跡114以 基/ 路至基部11 2之下表面。複數個# 表面連接電 ^ r, ^ s ^ t „ Λ Λ Λ"16 ^ ^ ^ ^ ^ ^ ^ ^ ^ F# ^ IMi ^ ^ s 陣列,或以多列環繞底表面之周圍。 、日王 定晶片封裝件於使用最終產品中用以固 當先前技術的BGA封裝件提供比較早類型封裝件更大 改善之咼密度及高輸入/輸出(1/〇)能力,經常相要使K 封裝件更小以進-步減少印刷電路板上所需要之空間數量 第5頁 89126574.ptc 490822 年
案號 89126574 五、發明說明(2) 以谷納封裝件。因為結合引線係一^預定長度且在相鄰結人 位置間需要一最小空間以提供結合工具足夠之空間,基^ 基部必須比晶粒大,且不可能製造更緊湊的封裝件。理邦、 地,希望製造一封裝件,其中基板基部不需要大於晶粒: 尺寸。 在先前技術中,如上所述,普遍為各別單一晶粒裝配— 封裝件。他人已經體認形成晶圓級][C封裝件是有利的, 即’在晶圓上已形成個別晶片之後,但在晶圓被切割成個 別晶片之前。#此允許輕易量產晶粒封裝件及各種晶粒封 ϊΊί圓ΐ配置成矩陣格式’全部一次地被製造及測 试《如此可以減少1(:晶粒之封裝及測試處理之時間及成 本。 在先前技術中之封裝方法之一些例子 包含1訂亡“1(1之美國專利第5乂日日_、及貝施 一帽孑曰HI iu私壯Ϊ t ’ 60號,其揭示使用 等人之美國專利第5, 798, 557號,裝日置;⑽ 封裝的積體電路具有钍合於半導坪、/述晶圓級抢封地 晶圓一。。d等!。之:護蓋 一種半導體封裝的形成方法,係提供一括5说,其揭不 之晶圓,經由磨光或蝕刻使a n /、種包含複數個晶粒 到-基板,然後,將晶圓切:回者部變薄’將薄晶圓附著 本發明的目的係提供一種球柵 最小的尺寸’使得Ic封裝件 十裝件’其具有- 積。 〈二間不多於I C晶片的面
89126574.ptc $ 6頁 490822 年 Μ 曰 修正 89126574 五、發明說明(3) 本發明的另-目的係提供一種晶圓級的 得量產的較大效率及Ic封裝件 ^ ^件,以獲 【發明概述】 十仃劂忒之優點。 上述的目的已於一種積體電路封裝件中 一種洋片晶片及單一晶圓設計而形成晶圓級。,,、係使用 =電:封裝件之形成係首先形成提供二 其具有複數個微電子電路裝設於其上 =^曰曰®, 準鋁結合墊露出。鋁結合塾新 〃複數個標 後::二ίί 金屬化通路’被對準於晶圓,# 中之通路,組合物被重新】劑則被沉積經過基板 路及在矽晶圓上之結合墊 基板上之電 基板上之金屬塾,缺後被=妾/接球則被置於 後,晶圓被切粒而;^ ί B广;v升Γι 一bga結構。然 裝於-電路板上 早—bga封裳,bga封裝被浮動供安 ,甬ί ^ : 2體電路封裝件係小於先前技術的BGA封裝件 的:加空間’因為不需要使用線結合引線。整 =B曰,可被一久全部同時封裝,其比各晶粒個別地封裝更 ί ί率’且允許對於仍然在晶圓形式之封裝的晶粒作平行 【實施本發明的最佳模式】 參考圖1 ’ 一石夕晶圓2丨具有製造在其上面的複數個微電 路°微電路被安排成個別的晶片或晶粒24,25的矩陣。複 89126574.ptc 第7頁
年月曰 修正 數個銘結合塾2 3 封裝操作中,a 1 曰曰 別晶片被封裝。 割直到晶圓上之 施於晶圓級。 被文排環繞各晶片的周圍。在先前技術之 圓2 1於此點被切割成個別晶片,然後各個 在本t明’晶片被形成於晶圓’但未被切 封裝操作已完成,因此,晶片之封裝被實 圓5 ί Ξν顯示晶圓21之斷面2-2,設有鋁結合墊23於曰, 墊^上。封裝製程之第一步驟為再金屬化鋁結令 ϊ』,r吏:結合塾可焊接。銘,其-般被用於!。的線, 氧化而Ϊ生父2 =次佳理想的金屬’由於1
結合塾需“ί Ϊί,ΠιΪ”本發明之K封裝,翁 接之應用。因此,„ΐΐΐ具有低歐姆接觸電阻供傳導黎 屬化之-製程,二:ΐ:,被再金屬化。結合墊之再逢 電鍍。來考圖3 /、、,卬貝便於貫作,係使用無電式鎳金 播 & . ’百先’一層鋅被沉積在鋁結合墊23,缺 ΐ全;:ΐ電式鎳電錢被沉積在鋅層…後,-層;電 么t :沉積在無電式錄層之頂部上,以形成-鋅: 鍍19以使得結合墊23有助於 二风螺金; 屬化製程使結合塾再金屬化。。另外,可貫施-薄層金 面η:參考圖4 ’ -黏著層27被沉積在晶圓21之頂表 馨 成二:二合塾23露出。黏著劑可以矽樹脂彈性體製 成。黏者層27可透過一網印製程施加,1中, ς :才:被推壓經過「模版或一網版之開口。網版被“在 二版ί Ϊ ::地對,^圓c特定量之石夕樹脂彈性體;料 …同版邊冰刀酉己’-氣動橡膠滚轴磨在網版上當其橫掃
月 修正 曰 案號 89126574 五、發明說明(5) 時,以一恒定壓力剪辦Μ 之較高可流動性,其允料需要高於某-剪斷壓力 所留下之間隙。結合墊23夕+穿透網版而充滿網版之線網 在結合塾的頂端。網版被移=積被佔’使得材料被安置 的頂端。此外,可使用_ 形成一均句材料層在晶圓 到晶圓21的頂表面或至插=:形成以附著這黏著層2? 人膠囊,提供晶圓之環板層^石夕樹脂彈性體作為裝 21之緩衝,緩衝=。樣彈性體也作為晶圓 ^ . . „ . _ , 卜在應力,諸如晶圓及用以安裝I C封 之間之不相配的熱膨脹係數,或晶圓及用以安裝K封 衣件U點使用印刷電路板之間之不相配的熱膨服係數。 參考圖5,一插入基板層3〇跟著被固定於彈性體層27的 頂部以形成一晶圓組合件39。插入基板層3〇是一預形成的 基板,包括金屬電路34及一電介質基部32。金屬電路以典 型地包括遍及基板形成之銅跡。插入基板3 〇也可包括抗焊 接塗層以幫助界定銅金屬電路上之焊接可濕面積。金屬電 路3 4也可形成於插入基板30之單層或多層上。銅金屬電路 可為鎳金電鍍或用一有機材料塗上。電介質基部材料32典 型地以聚氨基化合物製成。此外,也可使用BT樹脂及其他 環氧基樹脂玻璃基板作為電介質基部材料32。金屬電路34 一般作為互連電路’因為跡可被路由遍及基板以自各種结 合墊2 3互連至輸入/輸出(I/O )互連,其將被附加至晶圓 組合件3 9,以下將參考圖7說明。 插入基板3 0的一個主要特色是銅電路上之複數個開〇 3 6。插入基板3 〇之尺寸可以大約相同於晶圓2 1,且被對準 89126574.ptc 第9頁 490822 月 修正 曰 案號 89126574 五、發明說明(6) 到晶am使得開口36對準結合塾23。足夠量之銅必須存在 於開口36以提供焊料或傳導黏著劑之適當連接。一圓形銅 ”繞開口36:戈了銅條橫過開口36可被使用以利此需要。 =:基板30跟著以結合黏著劑黏著至彈性體層27,晶圓組 合件跟著被處理。因此,插入被對準及結合至晶圓。 參考圖6 ’ -焊料糊層4〇被沉積經過插入基板3〇之開口 二:it 士述彈性體層27沉積之相同方式以-網版或模 t i貝把。插入基板基部32層被遮蔽,藉氣動橡膠 f軸使知料糊40沉積進入開口36,使得焊料糊4〇 一次全部 η於晶圓1。晶圓21跟著再過錫以形成複數個電連接 ;a ° 1上之、纟0合塾23及插入基板基部層中之銅金屬電 4,間。使用自動分配設備或使用焊料預形成配置也可 將焊料糊沉積經過插入基板之開口 36 ^此外,一 劑可被使用以取代焊料糊,用以電連接結合墊23及金屬電 Γ。4、空ΐί劑被沉積於開口36中,跟著被處理以形成電連 ^ 地,可使用一環氧基樹脂材料保護 :氧=旨材料之施加也可使用上述之網版或模=製 私,然後處理保護塗層。 下一個步驟是放置封裝件焊料球於晶圓上。 =作為封料之I/Q互連,且制以固定完成的1(^牛裝= 用印刷電路板。參考圖7,經由預形成焊料球 械械轉移’焊料球50被置於金屬化開口 36。此外,焊料 網版或模版印焊料糊形成。焊料跟著再過錫以形 成封竑件焊料球。焊料球50可以想要之圖型型式施加,諸 89126574.ptc 第10頁 490822
490822
89126574.ptc 第12頁 案號 89126574
了頁表面的晶片之矽晶圓的斜 圖式簡單說明 圖1是具有複數個形成於— 視圖。 圖2是圖1中所示矽晶圓之斯 圖3-β是圖1的矽晶圓的横剖 〜2的橫刮面圖。
封裝件所使用之各種製程步驟。圖,顯示形成本發明的1C 圖7是圖1的石夕晶圓的橫剖面图 _ 用之完結的晶圓組合件。 国,顯示本發明的1C封裝件 圖8是本發明的完結的IC封裴株 .衣件之4頁剖面圖。 圖9是已知先則技術之球柵陣列封担 干Μ封裝件的橫剖面圖。
89126574.ptc 第13頁

Claims (1)

  1. 490822 8912RR74 六、申請專利範圍 t 一種晶圓級積體電路封裴件,包含. 一矽晶叙,具有—面積且具有複數個結合勢安排於 表面 月 曰 第 一黏著層,覆蓋該晶粒 結合墊保持露出,彳的弟表面的實質部知 一插入基板,置於該黏著層個金廣電路 數個金屬化開口,該開口是對粗的複數個 及該 複數個 結合墊 曰拉,St f,電連接插入基板的複數個金屬化開口 日日拉上之複數個結合墊,及 複數個輸入/輪屮卩、由 數個金屬化開口。 ,形成於插入基板的複 2.如申請專利範圍第1項之積體電 1/〇互連是形成在該插入基板上之焊料球衣件,其中,該 、3父申請專利範圍第μ之積體“步連接複數個金屬化開口及複數個 、,其中,電 料。 墊之電連接裝置是焊 4. 如申請專利範圍第丨項之積體電路 連接複數個金屬化開口及複數個 //件,其中, 接劑。 墊之電連接裴置是' 5. 如申請專利範圍第1項之積體電路封壯 " 入基板具有該晶粒面積的相同尺寸之面衣件,其中, β —種晶圓級積體電路封裝件,包含·、。 I占 插 石夕晶粒,具有-面積且具有複數;結合㈣ 排於 第 \\326\2d-\91-02\89126574.ptc 第14頁 ^0822 ^0822 月 曰 修正 Jjfe 8912RR7A 六、申請專利範圍 一表面, 钻著層覆蓋该晶粒的第一表面的實質邻於 ^ ^ . 結合墊保持露出, 曰]貝貝口 IM刀,祓數個 一電介質材料構成之插入基板,具 %έ» Ti S 4工 、有不旻數個至屬電路跡 遍及δ又置,插人基板被置於該黏著 ==二 屈化關口,甘B…# 上 且包括複數個金 /、疋對準於該晶粒的複數個结 具有該晶粒面積的相同尺寸之面積,口塾插入基板 化= :;ί =連:妾’形成於插入基板之複數個金屬 J ^ β日日粒上之複數個結合墊之間,及 的複數個金屬化開口。 數個電連接係以焊料形成'。之積體電路封裝件’其中,複 8 · —種晶圓級積體電路封裝件,包 一石夕晶粒,具有一面積 — 一表面, 檟且具有複數個結合墊安排於一第 一黏著層,覆蓋該晶粒 主二h — 結合墊保持露出, 〇弟一表面的貫質部份,複數個 一插入基板,置於該黏荖 跡和複數個金屬化開口,兮9 ,匕括複數個金屬電路 結合墊, μ開口是對準於該晶粒的複數個 複數個電連接,形成於插 該晶粒上之複數個結合塾:二基板,複數個金屬化開口及 傳導性黏接劑沉積於金屬口;數;電連接之形成係以 複數個輸入/輸出(j / 〇 )互連’形成於插入基板的複 W326\2d-\91 -02\89126574 • ptc 第15頁 490822 案號 89126574 Λ_ 曰 修正 t、申請專利範圍 數個金屬化開口 89126574.ptc 第16頁
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