KR20020009316A - 박형 반도체 패키지의 제조 방법 - Google Patents

박형 반도체 패키지의 제조 방법 Download PDF

Info

Publication number
KR20020009316A
KR20020009316A KR1020000043059A KR20000043059A KR20020009316A KR 20020009316 A KR20020009316 A KR 20020009316A KR 1020000043059 A KR1020000043059 A KR 1020000043059A KR 20000043059 A KR20000043059 A KR 20000043059A KR 20020009316 A KR20020009316 A KR 20020009316A
Authority
KR
South Korea
Prior art keywords
substrate
semiconductor package
gold wire
die
manufacturing
Prior art date
Application number
KR1020000043059A
Other languages
English (en)
Inventor
리시에완
Original Assignee
듀흐 마리 에스.
오리엔트 세미컨덕터 일렉트로닉스 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 듀흐 마리 에스., 오리엔트 세미컨덕터 일렉트로닉스 리미티드 filed Critical 듀흐 마리 에스.
Priority to KR1020000043059A priority Critical patent/KR20020009316A/ko
Publication of KR20020009316A publication Critical patent/KR20020009316A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

박형 반도체 패키지(thin type semiconductor)를 제조하는 방법은, 기판을 준비하고, 기판의 상부에 다이(die)를 부착하며, 기판 위에 있는 알루미늄 패드 (pad)와 다이와의 사이를 금선(gold wire)로 접합하며, 칩, 금선 및 리드(lead) 프레임의 상부를 합성 수지로 몰딩(molding)하며, 그리고 회로 레이아웃 (layout)만이 남도록 기판을 에칭하는 단계들을 포함하고, 그것에 의해 초박형 반도체 패키지가 특정 사양의 리드 프레임을 사용하지 않고 종래 방법보다 빠른 속도로 얻어진다.

Description

박형 반도체 패키지의 제조 방법{A Method of Manufacturing Thin Type Semiconductor Packages}
반도체 패키징 기술은 급속도로 발전하고 이들 추세는 다중다리(mutiple leg), 향상된 집적 및 경량화이다. 휴대 용이성, 평면 디스플레이 (planar display), 손바닥형 기기(palm type apparatuse), 이동 전화 등의 최근의 지배적인 경향으로 인해, 제작자들이 박형 반도체 패키지의 설계 및 개발 방법에 애를 쓰고 있다. 현재, 플랫(flat) 패키지보다 더 얇은 박형 반도체 패키지의 제조 방법은 돌출부(protuberance)를 실장하기 위한 그루브(groove)를 포함하는 박형 리드 프레임 C7025번을 주로 사용하고 있다. 도 1a- 1e에 도시된 것처럼, 종래의 박형 반도체 패키지의 제조 방법은 :
a. 리드 프레임 1의 적당한 위치에 칩 14를 접합하는 단계(도 1a 참조) ;
b. 리드 프레임 1의 상부에 있는 리세스(recess) 11내에 범프(bump) 12를 접합하는 단계(도 1b 참조) ;
c. 범프 12 및 칩 14 사이를 금선 13으로 연결하는 단계(도 1c 참조) ;
d. 칩 14, 금선 13 및 리드 프레임 1의 상부를 합성 수지 15로 감싸는 단계(도 1d 참조) ;
e. 회로 레이아웃만을 남기기 위해 부분 16을 에칭하는 단계 ; 및
f. 요구에 맞게 패키지를 자르는 단계를 포함한다.
그러나, 박형 반도체를 제조하는 상술한 방법은 다음의 결점으로 인해 어려움을 겪고 있다.
1. 상술한 방법은 특허된 특정 사양의 리드 프레임을 사용해야하고, 이로 인해 제조자가 리드 프레임에 대해 많은 비용을 부담해야한다.
2. 범프와 칩 사이에 금선을 연결하기 전에 리드 프레임의 리세스 내에 범프를 접합할 필요가 있고 그로 인해 추가적인 작업이 요구된다.
3. 리드 프레임의 한계로 인해, 패키지의 두께를 더 줄이는 것이 불가능하다.
그러므로, 본 발명의 목적은 위에 언급된 결점을 피하거나 줄일 수 있는 박형 반도체 패키지를 제조하는 향상된 방법을 제공하는 것이다.
본 발명의 주목적은 박형 반도체 패키지의 제조 방법을 제공하는 것이고, 거기서 기판은 제조자에 의해 쉽게 제조될 수 있으며 기판의 재료 및 두께는 필요에 따라 변경될 수 있다.
본 발명의 다른 목적은 단지 한 번의 접합 단계를 포함하는 초박형 반도체 패키지의 제조 방법을 제공하는 것이다.
도 1a, 1b, 1c, 1d, 및 1e는 종래의 박형 반도체 패키지의 제조 방법을 나타낸다 ;
도 2a, 2b, 2c, 및 2d는 본 발명에 따른 박형 반도체 패키지의 제조 방법을 나타낸다.
본 발명은 기판을 준비하는 단계, 기판의 상부에 다이(die)를 부착하는 단계, 기판 위에 있는 알루미늄 패드와 다이와의 사이를 금선(gold wire)으로 접합하는 단계, 칩, 금선 및 리드 프레임의 상부를 합성 수지로 몰딩하는 단계, 및 회로 레이아웃만을 남기기 위하여 기판을 에칭하는 단계를 포함하고, 그것에 의해서 초박형 반도체 패키지가 얻어진다.
도 1a-1d에 도시된 것처럼, 본 발명에 따른 박형 반도체 패키지의 제조 방법은 :
a. 기판 2 위에 다이 23을 부착하는 단계(도 2a 참조) ;
b. 기판 2 위에 있는 알루미늄 패드 21 및 다이 14 사이를 금선 22로 접합하는 단계(도 2b 참조) ;
c. 다이 23, 금선 22 및 기판 2를 합성 수지 24로 몰딩하는 단계(도 2c 참조) ;
d. 회로 레이아웃만을 남기기 위하여 기판 2를 에칭하는 단계(도 2d 단계) ;및
e. 패키지를 요구에 맞게 자르는 단계를 포함한다.
본 발명은 상술한 결점을 피하거나 줄일 수 있는 향상된 박형 반도체 패키지의 제조 방법을 제공하고, 또한 단지 한 번의 접합 단계만을 포함하는 초박형 반도체 패키지의 제조 방법을 제공한다.

Claims (1)

  1. a. 기판 위에 다이(die)를 부착하고 ;
    b. 상기 기판 위에 있는 알루미늄 패드 및 상기 다이 사이를 금선(gold wire)로 접합하며(도 2b 참조) ;
    c. 합성 수지로 상기 칩, 상기 금선 및 상기 기판을 몰딩하며 ;
    d. 상기 기판의 회로 레이아웃만이 남도록 상기 기판을 에칭하며 ;
    e. 패키지를 요구에 맞게 자르는
    박형 반도체 패키지의 제조 방법.
KR1020000043059A 2000-07-26 2000-07-26 박형 반도체 패키지의 제조 방법 KR20020009316A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000043059A KR20020009316A (ko) 2000-07-26 2000-07-26 박형 반도체 패키지의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000043059A KR20020009316A (ko) 2000-07-26 2000-07-26 박형 반도체 패키지의 제조 방법

Publications (1)

Publication Number Publication Date
KR20020009316A true KR20020009316A (ko) 2002-02-01

Family

ID=37478022

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000043059A KR20020009316A (ko) 2000-07-26 2000-07-26 박형 반도체 패키지의 제조 방법

Country Status (1)

Country Link
KR (1) KR20020009316A (ko)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252014A (ja) * 1996-03-15 1997-09-22 Nissan Motor Co Ltd 半導体素子の製造方法
JPH11121646A (ja) * 1997-10-14 1999-04-30 Hitachi Cable Ltd 半導体パッケ−ジおよびその製造方法
JPH11195733A (ja) * 1997-10-28 1999-07-21 Seiko Epson Corp 半導体装置の製造方法、半導体装置用導電性板および半導体装置
JP2000012758A (ja) * 1998-06-26 2000-01-14 Matsushita Electron Corp リードフレームおよびそれを用いた樹脂封止型半導体装置およびその製造方法
JP2000077596A (ja) * 1998-09-02 2000-03-14 Matsushita Electronics Industry Corp リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法
KR20000074351A (ko) * 1999-05-20 2000-12-15 마이클 디. 오브라이언 반도체패키지 및 그 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252014A (ja) * 1996-03-15 1997-09-22 Nissan Motor Co Ltd 半導体素子の製造方法
JPH11121646A (ja) * 1997-10-14 1999-04-30 Hitachi Cable Ltd 半導体パッケ−ジおよびその製造方法
JPH11195733A (ja) * 1997-10-28 1999-07-21 Seiko Epson Corp 半導体装置の製造方法、半導体装置用導電性板および半導体装置
JP2000012758A (ja) * 1998-06-26 2000-01-14 Matsushita Electron Corp リードフレームおよびそれを用いた樹脂封止型半導体装置およびその製造方法
JP2000077596A (ja) * 1998-09-02 2000-03-14 Matsushita Electronics Industry Corp リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法
KR20000074351A (ko) * 1999-05-20 2000-12-15 마이클 디. 오브라이언 반도체패키지 및 그 제조방법

Similar Documents

Publication Publication Date Title
US7061079B2 (en) Chip package structure and manufacturing method thereof
US7224045B2 (en) Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
US20010042904A1 (en) Frame for semiconductor package
TWI455213B (zh) 無外引腳封裝結構及其製作方法
US9478484B2 (en) Semiconductor packages and methods of formation thereof
US20210296263A1 (en) Semiconductor package structure for improving die warpage and manufacturing method thereof
US10051742B2 (en) Power module and manufacturing method thereof
TW200947668A (en) Stacked type chip package structure
US10211132B2 (en) Packaged semiconductor device having multi-level leadframes configured as modules
US11227848B2 (en) Chip package array, and chip package
TWI387089B (zh) 多晶片封裝結構及其製造方法
TWI378515B (en) Method of fabricating quad flat non-leaded package
US7888781B2 (en) Micro-layered lead frame semiconductor packages
US20080185698A1 (en) Semiconductor package structure and carrier structure
KR20020009316A (ko) 박형 반도체 패키지의 제조 방법
CN107342276B (zh) 半导体器件及相应方法
TWI757133B (zh) 四方扁平無引腳封裝結構
JP2016162964A (ja) 半導体装置の製造方法および半導体装置
US10916485B2 (en) Molded wafer level packaging
JP2002124627A (ja) 半導体装置及びその製造方法
TW201539673A (zh) 晶片封裝結構及其製作方法
US9171786B1 (en) Integrated circuit with recess for die attachment
TWM482842U (zh) 四方形扁平無引腳封裝（ｑｆｎ）之內封外露散熱裝置結構改良
JP2002151531A (ja) 半導体装置の製造方法
TW201332031A (zh) 用於一半導體封裝之基板製程、封裝方法、封裝結構及系統級封裝結構

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application