KR20020008400A - 칩 모듈용 칩 캐리어 및 칩 모듈 제조방법 - Google Patents
칩 모듈용 칩 캐리어 및 칩 모듈 제조방법 Download PDFInfo
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- KR20020008400A KR20020008400A KR1020017013940A KR20017013940A KR20020008400A KR 20020008400 A KR20020008400 A KR 20020008400A KR 1020017013940 A KR1020017013940 A KR 1020017013940A KR 20017013940 A KR20017013940 A KR 20017013940A KR 20020008400 A KR20020008400 A KR 20020008400A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
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- H01L2924/19042—Component type being an inductor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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Abstract
Description
Claims (14)
- 줄무늬처럼 도안된 커넥션리드들이 상면에 평행하게 연장 배열된 기판을 갖는 칩 모듈을 형성하기 위한 칩 캐리어에 있어서,상기 커넥션리드들은 상기 기판에 적용되는 전기적인 전도성 커넥션 스트랜드(12, 13)로 이루어지고, 상기 기판은 캐리어필름(11)으로 형성됨을 특징으로 하는 칩 캐리어.
- 제1항에 있어서, 상기 캐리어필름(11)은 커넥션 스트랜드(12, 13)의 반대면 상에 소정의 전기용량을 발생시키기 위한 별도의 전도성 카운터 스트랜드(27)가 적어도 하나 이상 제공되며, 절연 캐리어필름은 상기 커넥션 스트랜드와 카운터 스트랜드 사이에 중간층으로써 배열됨을 특징으로 하는 상기 칩 캐리어.
- 제1항 또는 제2항에 있어서, 상기 커넥션 스트랜드(12, 13)는 칩(14)의 콘택금속(15, 16)과 접촉하기 위해 적어도 소정부위에 연결 물질 코팅이 제공됨을 특징으로 하는 상기 칩 캐리어.
- 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 커넥션 스트랜드(12, 13)는 칩(14)의 콘택금속(15, 16)과 접촉하기 위해 적어도 소정부위에 콘택금속이 제공됨을 특징으로 하는 상기 칩 캐리어.
- 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 커넥션 스트랜드(12, 13)는 코일유닛의 터미널들과 연결됨을 특징으로 하는 상기 칩 캐리어.
- 제1항 내지 제5항 중 어느 한 항에 따른 칩 캐리어와 돌출된 콘택금속이 마련된 연결 표면을 갖는 칩이 구비된 칩 모듈에 있어서, 상기 칩(14)의 콘택금속(15, 16)은 커넥션 스트랜드(12, 13)의 상면(21)과 접촉됨을 특징으로 하는 칩 모듈.
- 제6항에 있어서, 상기 칩(14)의 콘택금속(15, 16)과 접촉된 커넥션 스트랜드(12, 13)는 코일유닛의 터미널들과 연결됨을 특징으로 하는 상기 칩 모듈.
- 제6항 또는 제7항에 따른 칩 모듈 제조방법에 있어서,캐리어필름(11)의 일측면에 적어도 두 개의 전기적인 전도성 커넥션 스트랜드(12, 13)가 적용되어, 이 커넥션 스트랜드가 캐리어의 표면상에서 평행하게 연장되는 단계; 및칩(14)의 콘택금속(15, 16)이 상기 커넥션 스트랜드와 접촉되어, 상기 칩의 콘택금속이 각각의 커넥션 스트랜드와 접촉되는 단계;가 포함됨을 특징으로 하는 칩 모듈 제조방법.
- 제8항에 따른 칩 모듈 제조방법에 있어서, 커넥션 스트랜드(12, 13)가 칩(14)과 접촉되기 전에, 상기 커넥션 스트랜드들은 코일유닛과 접촉됨을 특징으로 하는 상기 칩 모듈 제조방법.
- 제8항 또는 제9항에 따른 칩 모듈 제조방법에 있어서, 상기 커넥션 스트랜드와 캐리어필름은 연속 스트랜드로써 조합되고, 접착이 이루어지는 동안 접촉영역(38)내에서 서로 대응되게 연속적으로 이동되는 일련의 과정을 통해 커넥션 스트랜드(12, 13)가 캐리어필름(11)에 연속적으로 적용됨을 특징으로 하는 상기 칩 모듈 제조방법.
- 제10항에 따른 칩 모듈 제조방법에 있어서, 상기 캐리어필름은 커넥션 스트랜드(12, 13)를 갖는 접촉영역(38)에 도달하기 전 소정크기로 규정된 개구창이 형성되고, 이 개구창은 그 다음의 접촉영역에서 포켓형상의 접촉수용부(23, 24)가 형성되는 동시에 커넥션 스트랜드(12, 13)에 의해 덮어씌워짐을 특징으로 하는 상기 칩 모듈 제조방법.
- 제8항 내지 제11항 중 어느 한 항에 따른 칩 모듈 제조방법에 있어서, 상기 캐리어필름(11)은 장차 커넥션 스트랜드(12, 13)가 적용될 측면의 반대면상에 별도의 전기적인 전도성 카운터 스트랜드(27)가 적어도 하나 이상 덮어씌워짐을 특징으로 하는 상기 칩 모듈 제조방법.
- 제8항 내지 제12항 중 어느 한 항에 따른 칩 모듈 제조방법에 있어서, 상기 커넥션 스트랜드(12, 13) 및/또는 적어도 하나 이상의 카운터 스트랜드(27)는 박층제조 공정 중 캐리어필름(11)에 적용됨을 특징으로 하는 상기 칩 모듈 제조방법.
- 제13항에 따른 칩 모듈 제조방법에 있어서, 상기 커넥션 스트랜드(12, 13) 및/또는 적어도 하나 이상의 카운터 스트랜드(27)와 캐리어필름(11)간의 접착은 고융점 도포에 의해 이루어짐을 특징으로 하는 상기 칩 모듈 제조방법.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19920593A DE19920593B4 (de) | 1999-05-05 | 1999-05-05 | Chipträger für ein Chipmodul und Verfahren zur Herstellung des Chipmoduls |
DE19920593.0 | 1999-05-05 | ||
PCT/DE2000/001396 WO2000068994A1 (de) | 1999-05-05 | 2000-05-04 | Chipträger fur ein chipmodul und verfahren zur herstellung des chipmoduls |
Publications (2)
Publication Number | Publication Date |
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KR20020008400A true KR20020008400A (ko) | 2002-01-30 |
KR100763572B1 KR100763572B1 (ko) | 2007-10-04 |
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KR1020017013940A KR100763572B1 (ko) | 1999-05-05 | 2000-05-04 | 칩 모듈용 칩 캐리어 및 칩 모듈 제조방법 |
Country Status (9)
Country | Link |
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US (1) | US7105915B1 (ko) |
EP (1) | EP1177579A1 (ko) |
JP (2) | JP2002544671A (ko) |
KR (1) | KR100763572B1 (ko) |
CN (1) | CN1200460C (ko) |
AU (1) | AU5208000A (ko) |
CA (1) | CA2370878C (ko) |
DE (1) | DE19920593B4 (ko) |
WO (1) | WO2000068994A1 (ko) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1215725A3 (de) * | 2000-12-18 | 2005-03-23 | cubit electronics Gmbh | Anordnung zur Aufnahme elektrischer Bauteile und kontaktloser Transponder |
DE10151657C1 (de) * | 2001-08-02 | 2003-02-06 | Fraunhofer Ges Forschung | Verfahren zur Montage eines Chips auf einem Substrat |
US6859057B2 (en) * | 2002-09-17 | 2005-02-22 | Aehr Test Systems | Die carrier |
DE10358423B4 (de) * | 2003-08-26 | 2006-09-21 | Mühlbauer Ag | Modulbrücken für Smart Labels |
US20050129977A1 (en) * | 2003-12-12 | 2005-06-16 | General Electric Company | Method and apparatus for forming patterned coated films |
TWI288885B (en) * | 2004-06-24 | 2007-10-21 | Checkpoint Systems Inc | Die attach area cut-on-fly method and apparatus |
AU2005304141B2 (en) * | 2004-11-02 | 2010-08-26 | Hid Global Gmbh | Laying device, contacting device, advancing system, laying and contacting unit, production system, method for the production and a transponder unit |
DE102005044306A1 (de) * | 2005-09-16 | 2007-03-22 | Polyic Gmbh & Co. Kg | Elektronische Schaltung und Verfahren zur Herstellung einer solchen |
US8322624B2 (en) | 2007-04-10 | 2012-12-04 | Feinics Amatech Teoranta | Smart card with switchable matching antenna |
US8608080B2 (en) | 2006-09-26 | 2013-12-17 | Feinics Amatech Teoranta | Inlays for security documents |
US7581308B2 (en) | 2007-01-01 | 2009-09-01 | Advanced Microelectronic And Automation Technology Ltd. | Methods of connecting an antenna to a transponder chip |
US7971339B2 (en) | 2006-09-26 | 2011-07-05 | Hid Global Gmbh | Method and apparatus for making a radio frequency inlay |
US7546671B2 (en) | 2006-09-26 | 2009-06-16 | Micromechanic And Automation Technology Ltd. | Method of forming an inlay substrate having an antenna wire |
US8286332B2 (en) | 2006-09-26 | 2012-10-16 | Hid Global Gmbh | Method and apparatus for making a radio frequency inlay |
US7979975B2 (en) | 2007-04-10 | 2011-07-19 | Feinics Amatech Teavanta | Methods of connecting an antenna to a transponder chip |
DE102006047388A1 (de) | 2006-10-06 | 2008-04-17 | Polyic Gmbh & Co. Kg | Feldeffekttransistor sowie elektrische Schaltung |
US7980477B2 (en) | 2007-05-17 | 2011-07-19 | Féinics Amatech Teoranta | Dual interface inlays |
DE602007010634D1 (de) | 2007-09-18 | 2010-12-30 | Baile Na Habhann Co Galway | Verfahren zur Kontaktierung eines Drahtleiters gelegt auf ein Substrat |
DE102008016274A1 (de) | 2008-03-28 | 2009-10-01 | Smartrac Ip B.V. | Chipträger für ein Transpondermodul sowie Transpondermodul |
DE102009012255A1 (de) * | 2009-03-07 | 2010-09-09 | Michalk, Manfred, Dr. | Schaltungsanordnung |
DE102009056122A1 (de) * | 2009-11-30 | 2011-06-01 | Smartrac Ip B.V. | Verfahren zur Kontaktierung eines Chips |
DE102012200258A1 (de) * | 2012-01-10 | 2013-07-11 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur herstellung eines chips |
DE102012209328A1 (de) | 2012-06-01 | 2013-12-05 | 3D-Micromac Ag | Verfahren und Anlage zum Herstellen eines Mehrschichtelements sowie Mehrschichtelement |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3440027A (en) * | 1966-06-22 | 1969-04-22 | Frances Hugle | Automated packaging of semiconductors |
US3691628A (en) * | 1969-10-31 | 1972-09-19 | Gen Electric | Method of fabricating composite integrated circuits |
US3855693A (en) * | 1973-04-18 | 1974-12-24 | Honeywell Inf Systems | Method for assembling microelectronic apparatus |
US4125810A (en) * | 1977-04-08 | 1978-11-14 | Vari-L Company, Inc. | Broadband high frequency baluns and mixer |
US4151579A (en) * | 1977-09-09 | 1979-04-24 | Avx Corporation | Chip capacitor device |
JPH01217934A (ja) * | 1988-02-26 | 1989-08-31 | Hitachi Ltd | キャリアテープ |
US5176853A (en) * | 1988-08-16 | 1993-01-05 | Delco Electronics Corporation | Controlled adhesion conductor |
US5122929A (en) * | 1988-08-16 | 1992-06-16 | Delco Electronics Corporation | Method of achieving selective inhibition and control of adhesion in thick-film conductors |
FR2645680B1 (fr) | 1989-04-07 | 1994-04-29 | Thomson Microelectronics Sa Sg | Encapsulation de modules electroniques et procede de fabrication |
JPH03120746A (ja) | 1989-10-03 | 1991-05-22 | Matsushita Electric Ind Co Ltd | 半導体素子パッケージおよび半導体素子パッケージ搭載配線回路基板 |
FR2673041A1 (fr) * | 1991-02-19 | 1992-08-21 | Gemplus Card Int | Procede de fabrication de micromodules de circuit integre et micromodule correspondant. |
US5635751A (en) * | 1991-09-05 | 1997-06-03 | Mitsubishi Denki Kabushiki Kaisha | High frequency transistor with reduced parasitic inductance |
JP3241139B2 (ja) * | 1993-02-04 | 2001-12-25 | 三菱電機株式会社 | フィルムキャリア信号伝送線路 |
US5385785A (en) * | 1993-08-27 | 1995-01-31 | Tapeswitch Corporation Of America | Apparatus and method for providing high temperature conductive-resistant coating, medium and articles |
DE4416697A1 (de) | 1994-05-11 | 1995-11-16 | Giesecke & Devrient Gmbh | Datenträger mit integriertem Schaltkreis |
US5528222A (en) | 1994-09-09 | 1996-06-18 | International Business Machines Corporation | Radio frequency circuit and memory in thin flexible package |
KR970707444A (ko) * | 1994-10-28 | 1997-12-01 | 야마모토 히데키 | 프로브 구조(probe structure) |
JP3484554B2 (ja) | 1995-02-28 | 2004-01-06 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置 |
DE19509999C2 (de) * | 1995-03-22 | 1998-04-16 | David Finn | Verfahren und Vorrichtung zur Herstellung einer Transpondereinheit sowie Transpondereinheit |
DE69634376D1 (de) * | 1995-05-12 | 2005-03-31 | St Microelectronics Inc | IC-Packungsfassungssystem mit niedrigem Profil |
US5681662A (en) * | 1995-09-15 | 1997-10-28 | Olin Corporation | Copper alloy foils for flexible circuits |
DE19541039B4 (de) * | 1995-11-03 | 2006-03-16 | Assa Abloy Identification Technology Group Ab | Chip-Modul sowie Verfahren zu dessen Herstellung |
DE19601203A1 (de) | 1996-01-15 | 1997-03-20 | Siemens Ag | Datenträgerkarte und Verfahren zu deren Herstellung |
US5847929A (en) * | 1996-06-28 | 1998-12-08 | International Business Machines Corporation | Attaching heat sinks directly to flip chips and ceramic chip carriers |
DE19639646A1 (de) * | 1996-09-26 | 1998-04-02 | Siemens Ag | Trägerband und Verfahren zum Herstellen eines solchen Trägerbandes |
TW480636B (en) * | 1996-12-04 | 2002-03-21 | Seiko Epson Corp | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
FR2756955B1 (fr) | 1996-12-11 | 1999-01-08 | Schlumberger Ind Sa | Procede de realisation d'un circuit electronique pour une carte a memoire sans contact |
DE19651566B4 (de) * | 1996-12-11 | 2006-09-07 | Assa Abloy Identification Technology Group Ab | Chip-Modul sowie Verfahren zu dessen Herstellung und eine Chip-Karte |
JPH113411A (ja) * | 1997-06-13 | 1999-01-06 | Hitachi Chem Co Ltd | Icカード |
US6040702A (en) * | 1997-07-03 | 2000-03-21 | Micron Technology, Inc. | Carrier and system for testing bumped semiconductor components |
US6057174A (en) * | 1998-01-07 | 2000-05-02 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, and electronic apparatus |
US6066512A (en) * | 1998-01-12 | 2000-05-23 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, and electronic apparatus |
US6815251B1 (en) * | 1999-02-01 | 2004-11-09 | Micron Technology, Inc. | High density modularity for IC's |
-
1999
- 1999-05-05 DE DE19920593A patent/DE19920593B4/de not_active Expired - Lifetime
-
2000
- 2000-05-04 US US10/019,696 patent/US7105915B1/en not_active Expired - Lifetime
- 2000-05-04 AU AU52080/00A patent/AU5208000A/en not_active Abandoned
- 2000-05-04 CA CA2370878A patent/CA2370878C/en not_active Expired - Lifetime
- 2000-05-04 CN CNB00809974XA patent/CN1200460C/zh not_active Expired - Fee Related
- 2000-05-04 JP JP2000617495A patent/JP2002544671A/ja not_active Withdrawn
- 2000-05-04 WO PCT/DE2000/001396 patent/WO2000068994A1/de active Application Filing
- 2000-05-04 EP EP00936667A patent/EP1177579A1/de not_active Withdrawn
- 2000-05-04 KR KR1020017013940A patent/KR100763572B1/ko active IP Right Grant
-
2011
- 2011-01-17 JP JP2011006920A patent/JP5444261B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CA2370878A1 (en) | 2000-11-16 |
DE19920593B4 (de) | 2006-07-13 |
US7105915B1 (en) | 2006-09-12 |
WO2000068994A1 (de) | 2000-11-16 |
DE19920593A1 (de) | 2000-11-23 |
AU5208000A (en) | 2000-11-21 |
JP2011101037A (ja) | 2011-05-19 |
CA2370878C (en) | 2011-02-15 |
JP2002544671A (ja) | 2002-12-24 |
EP1177579A1 (de) | 2002-02-06 |
CN1360736A (zh) | 2002-07-24 |
KR100763572B1 (ko) | 2007-10-04 |
JP5444261B2 (ja) | 2014-03-19 |
CN1200460C (zh) | 2005-05-04 |
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