KR20010095678A - 반도체 패키지 및 이것의 제조방법 - Google Patents
반도체 패키지 및 이것의 제조방법 Download PDFInfo
- Publication number
- KR20010095678A KR20010095678A KR1020000018976A KR20000018976A KR20010095678A KR 20010095678 A KR20010095678 A KR 20010095678A KR 1020000018976 A KR1020000018976 A KR 1020000018976A KR 20000018976 A KR20000018976 A KR 20000018976A KR 20010095678 A KR20010095678 A KR 20010095678A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor
- bonding
- chip
- wire
- chips
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (6)
- 반도체 칩 탑재영역을 가지면서 인출수단이 구비된 부재(14)와, 이 부재(14)상의 칩탑재영역에서부터 양측 상면에 형성된 본딩패드가 노출되도록 접착수단(18)에 의하여 서로 엇갈리게 적층된 다수의 반도체 칩(12a,12b,12c,12d)과, 상기 부재(14)의 와이어 본딩영역과 상기 다수의 반도체 칩(12a,12b,12c,12d)의 본딩패드간에 연결된 와이어(16)와, 상기 반도체 칩(12a,12b,12c,12d)들과 와이어(16)등을 외부로부터 보호하기 위하여 몰딩된 수지(20)로 구성된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서, 상기 접착수단(18)으로 접착테이프가 사용된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서, 상기 와이어(16)의 높이는 반도체 칩의 두께와 접착수단의 높이를 합한 것보다 낮은 것을 특징으로 하는 반도체 패키지.
- 부재(14)상에 형성되어 있는 칩탑재영역에 접착테이프(18)를 사용하여 양측상면에 형성된 본딩패드가 노출되도록 다수의 반도체 칩(12a,12b,12c,12d)을 서로 엇갈리게 접착수단을 매개로 적층 부착하는 공정과, 다수의 반도체 칩(12a,12b,12c,12d)중 가장 밑에 적층된 칩(12a)의 본딩패드를 시작으로 가장 위쪽에 적층된 칩(12d)의 본딩패드까지 상기 부재(14)의 본딩영역과 와이어(16)로 본딩하는 공정과, 상기 다수의 칩(12a,12b,12c,12d)과 와이어(16)등을 수지(20)로 몰딩하는 공정으로 이루어진 것을 특징으로 하는 반도체 패키지 제조방법.
- 제 4 항에 있어서, 상기 부재(14)상에 제 1반도체 칩(12a)과 제2반도체 칩(12b)을 부착하는 공정과, 상기 부재의 본딩영역과 제1,2반도체 칩(12a)(12b)의 본딩패드간을 와이어 본딩하는 공정이 별도로 진행되고, 상기 제 3반도체 칩(12c)과 제 4반도체(12d)을 부착하는 공정과 상기 부재의 본딩영역과 제3,4반도체 칩(12c)(12d)의 본딩패드간을 와이어 본딩하는 공정도 별도로 진행되는 것을 특징으로 하는 반도체 패키지 제조방법.
- 제 4 항 또는 제 5 항에 있어서, 상기 각각의 반도체 칩의 저면에는 웨이퍼 상태에서부터 접착수단이 일체로 부착된 것을 특징으로 하는 반도체 패키지 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0018976A KR100464561B1 (ko) | 2000-04-11 | 2000-04-11 | 반도체 패키지 및 이것의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0018976A KR100464561B1 (ko) | 2000-04-11 | 2000-04-11 | 반도체 패키지 및 이것의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010095678A true KR20010095678A (ko) | 2001-11-07 |
KR100464561B1 KR100464561B1 (ko) | 2004-12-31 |
Family
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Family Applications (1)
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KR10-2000-0018976A KR100464561B1 (ko) | 2000-04-11 | 2000-04-11 | 반도체 패키지 및 이것의 제조방법 |
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KR (1) | KR100464561B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8722513B2 (en) | 2010-12-21 | 2014-05-13 | Korea Institute Of Machinery & Materials | Semiconductor chip stack package and manufacturing method thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4489094B2 (ja) | 2007-04-27 | 2010-06-23 | 株式会社東芝 | 半導体パッケージ |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2953899B2 (ja) * | 1993-02-17 | 1999-09-27 | 松下電器産業株式会社 | 半導体装置 |
JP2944449B2 (ja) * | 1995-02-24 | 1999-09-06 | 日本電気株式会社 | 半導体パッケージとその製造方法 |
JPH08279591A (ja) * | 1995-04-07 | 1996-10-22 | Nec Corp | 半導体装置とその製造方法 |
JPH09186289A (ja) * | 1995-12-28 | 1997-07-15 | Lucent Technol Inc | 多層積層化集積回路チップ組立体 |
JP3316409B2 (ja) * | 1997-03-13 | 2002-08-19 | ローム株式会社 | 複数のicチップを備えた半導体装置の構造 |
JP3994498B2 (ja) * | 1998-01-30 | 2007-10-17 | 日立化成工業株式会社 | 半導体装置の製造方法 |
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- 2000-04-11 KR KR10-2000-0018976A patent/KR100464561B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8722513B2 (en) | 2010-12-21 | 2014-05-13 | Korea Institute Of Machinery & Materials | Semiconductor chip stack package and manufacturing method thereof |
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KR100464561B1 (ko) | 2004-12-31 |
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