KR20010040990A - 과전압 보호 ｉ/ｏ 버퍼 - Google Patents

과전압 보호 ｉ/ｏ 버퍼 Download PDF

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Publication number
KR20010040990A
KR20010040990A KR1020007009002A KR20007009002A KR20010040990A KR 20010040990 A KR20010040990 A KR 20010040990A KR 1020007009002 A KR1020007009002 A KR 1020007009002A KR 20007009002 A KR20007009002 A KR 20007009002A KR 20010040990 A KR20010040990 A KR 20010040990A
Authority
KR
South Korea
Prior art keywords
field
effect transistor
transistor
control
output
Prior art date
Application number
KR1020007009002A
Other languages
English (en)
Korean (ko)
Inventor
반스카익윌렘케이
칼크맨윌헬머스제이
위엔트제스르네제이엠
Original Assignee
롤페스 요하네스 게라투스 알베르투스
코닌클리즈케 필립스 일렉트로닉스 엔.브이.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 롤페스 요하네스 게라투스 알베르투스, 코닌클리즈케 필립스 일렉트로닉스 엔.브이. filed Critical 롤페스 요하네스 게라투스 알베르투스
Publication of KR20010040990A publication Critical patent/KR20010040990A/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020007009002A 1998-12-18 1999-12-01 과전압 보호 ｉ/ｏ 버퍼 KR20010040990A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP98204343.2 1998-12-18
EP98204343 1998-12-18
PCT/EP1999/009357 WO2000038322A1 (fr) 1998-12-18 1999-12-01 Tampon e/s protege contre les surtensions

Publications (1)

Publication Number Publication Date
KR20010040990A true KR20010040990A (ko) 2001-05-15

Family

ID=8234497

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020007009002A KR20010040990A (ko) 1998-12-18 1999-12-01 과전압 보호 ｉ/ｏ 버퍼

Country Status (4)

Country Link
EP (1) EP1057262A1 (fr)
JP (1) JP2002533971A (fr)
KR (1) KR20010040990A (fr)
WO (1) WO2000038322A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859074B2 (en) 2001-01-09 2005-02-22 Broadcom Corporation I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
EP1356590B1 (fr) 2001-01-09 2011-03-16 Broadcom Corporation Circuit d'entree/sortie submicronique supportant des tensions d'entree elevees
JP3656742B2 (ja) * 2001-10-30 2005-06-08 日本電気株式会社 携帯情報端末
US6850226B2 (en) 2001-11-09 2005-02-01 Nokia Corporation Multifunction mobile communications device with slidable display screen
US7138836B2 (en) 2001-12-03 2006-11-21 Broadcom Corporation Hot carrier injection suppression circuit
CN100373300C (zh) * 2005-12-16 2008-03-05 北京中星微电子有限公司 一种解决共享总线浮空导致io漏电的设计方法及装置
US20100159992A1 (en) * 2008-12-18 2010-06-24 Nokia Corporation Mobile communication device with a sliding display screen and screen-dividing member
US8283947B1 (en) * 2011-06-03 2012-10-09 Nxp B.V. High voltage tolerant bus holder circuit and method of operating the circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387826A (en) * 1993-02-10 1995-02-07 National Semiconductor Corporation Overvoltage protection against charge leakage in an output driver
WO1994029961A1 (fr) * 1993-06-07 1994-12-22 National Semiconductor Corporation Protection contre les surtensions
JPH0786910A (ja) * 1993-09-10 1995-03-31 Oki Electric Ind Co Ltd 出力駆動回路
JP2901171B2 (ja) * 1993-10-08 1999-06-07 日本電信電話株式会社 ディープサブミクロンｍｏｓｆｅｔ出力バッファ回路
JP3205156B2 (ja) * 1994-01-07 2001-09-04 川崎製鉄株式会社 半導体集積回路
US5418476A (en) * 1994-07-28 1995-05-23 At&T Corp. Low voltage output buffer with improved speed
JP3366484B2 (ja) * 1995-03-27 2003-01-14 沖電気工業株式会社 出力ドライバ回路
CA2171052C (fr) * 1995-09-29 2001-05-15 Colin Harris Pilote de sortie a trois etats pour logique cmos fonctionnant sous 3,3 ou 5 volts
JP3586985B2 (ja) * 1996-08-26 2004-11-10 松下電器産業株式会社 半導体装置の出力回路
JP3544819B2 (ja) * 1997-03-31 2004-07-21 株式会社 沖マイクロデザイン 入力回路および出力回路ならびに入出力回路
JPH11317652A (ja) * 1998-02-13 1999-11-16 Matsushita Electric Ind Co Ltd 出力回路

Also Published As

Publication number Publication date
WO2000038322A1 (fr) 2000-06-29
EP1057262A1 (fr) 2000-12-06
JP2002533971A (ja) 2002-10-08

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Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid