EP1057262A1 - Tampon e/s protege contre les surtensions - Google Patents

Tampon e/s protege contre les surtensions

Info

Publication number
EP1057262A1
EP1057262A1 EP99961033A EP99961033A EP1057262A1 EP 1057262 A1 EP1057262 A1 EP 1057262A1 EP 99961033 A EP99961033 A EP 99961033A EP 99961033 A EP99961033 A EP 99961033A EP 1057262 A1 EP1057262 A1 EP 1057262A1
Authority
EP
European Patent Office
Prior art keywords
field
effect transistor
transistor
control
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99961033A
Other languages
German (de)
English (en)
Inventor
Willem K. Van Schaik
Wilhelmus J. Kalkman
Rene J. M. Wientjes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP99961033A priority Critical patent/EP1057262A1/fr
Publication of EP1057262A1 publication Critical patent/EP1057262A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Definitions

  • the present invention relates to an I/O buffer, and more specifically to a tristate I/O buffer, i.e. a buffer whose output can be in one of the three states: a first state in which the output is actively high, a second state in which the output is actively low and in a third state, also referred to as tristate, in which the output is inactive and this output has a high impedance with respect to the exterior.
  • a tristate I/O buffer i.e. a buffer whose output can be in one of the three states: a first state in which the output is actively high, a second state in which the output is actively low and in a third state, also referred to as tristate, in which the output is inactive and this output has a high impedance with respect to the exterior.
  • the present invention more specifically relates to an I/O buffer constructed as an IC or forming part of an IC.
  • Such logic buffers are generally known and in the active state they produce at their outputs a logic HIGH/LOW level which depends on the logic level received at a data input.
  • An important task of such a buffer is to supply a logic output signal to a load , while a preceding circuit which supplies the data signal is not or hardly loaded.
  • LOW or "0" then corresponds to a first voltage level designated V ss and generally referred to as "ground” and HIGH or " 1" corresponds to a higher second voltage level designated V DD and generally referred to as "supply voltage”.
  • V ss first voltage level
  • V DD second voltage level
  • supply voltage the output of the tristate buffer is connected to a bus to which at least one input of at least one other logic circuit is connected and to which also one or more outputs of other logic circuits are connected.
  • the logic level of the bus is always determined by one of the connected logic circuits.
  • the connected circuits are controlled in such a manner that only one of them can be in an active HIGH/LOW state, the other circuits then being in their tristates in which their outputs consequently present a high impedance with respect to the bus and thus hardly or not affects the HIGH/LOW level supplied by said one circuit.
  • Logic circuits are designed for a predetermined supply voltage.
  • a conventional value for this supply voltage is 5 V but recently circuits have been developed for lower supply voltages. Examples of such lower standard supply voltages are 3.0 V and 3.3 V. These circuits have been developed particularly for battery-powered systems such as, for example, a laptop, because the power consumption decreases as the supply voltage is lower.
  • Another reason for the trend towards circuits with a low supply voltage is the fact that there is a continual tendency towards further miniaturization, which means that the dimensions of the circuit components are constantly reduced. When the supply voltage remains the same the circuit components are exposed to inadmissibly high field strengths.
  • an apparatus may include several logic circuits designed for mutually different supply voltages.
  • a reason for this may be, for example, that a version for a lower supply voltage has not yet been developed for a given circuit or that the performance of a version having a higher supply voltage is better.
  • an I/O buffer is connected to a bus which is also connected to circuits which operate at a supply voltage higher than that of this buffer.
  • a situation may the arise in which the buffer is in its tristate condition and the logic level of the bus is HIGH, which is caused by a circuit which operates at such a higher supply voltage, as a result of which the voltage level appearing at the output terminal of the I/O buffer is higher than its supply voltage level V DD .
  • the I/O buffer therefore has a protection circuit which can prevent such an undesired current.
  • Said protection circuit includes two PMOS transistors, one NMOS transistor and an inverter.
  • the protection circuit is controlled by the control signal for the PMOS pull-up transistor and is consequently derived from the data signal. This has several disadvantages.
  • the control signal for the PMOS pull-up transistor is supplied by a logic unit which in the circuit described in said publication is a NAND gate.
  • this logic unit serves to control not the PMOS pull-up transistor but also the protection circuit, which implies that this logic unit must be capable of supplying comparatively large currents and should therefore be relatively overproportioned.
  • the output of this logic unit is affected by the switching transients of not only the PMOS pull-up transistor but also those of the protection circuit, specifically those of the PMOS blocking transistor, which is arranged in series with the PMOS pull-up transistor.
  • the protection circuit is controlled by a control signal derived from the data signal means that the protection circuit is switched from the on state to the off state comparatively frequently, which is attended by a comparatively high power dissipation. Moreover, this means that the known circuit responds comparatively slowly to changes of state, which implies a limitation of the frequency range.
  • the gate of the PMOS blocking transistor is controlled via a second PMOS transistor.
  • This second PMOS transistor has its gate connected to the internal supply voltage V DD -
  • V DD the internal supply voltage
  • the second PMOS transistor will not be driven into full conduction but will tend to keep the PMOS blocking transistor cut off by means of a leakage current.
  • this will not wholly succeed, as a result of which a leakage current will also flow from the output to the internal supply V DD via the blocking transistor and the pull-up transistor. Since these transistors are larger than the second PMOS transistor this leakage current will also be larger than the leakage current through the second PMOS transistor.
  • a major object of the present invention is to provide an overvoltage-protected I/O buffer with an improved performance.
  • Figure 1 diagrammatically illustrates the basic principle of an I/O buffer
  • Figure 2 diagrammatically illustrates the structure of a PMOS transistor
  • Figure 3 shows the circuit diagram of a preferred embodiment of an I/O buffer in accordance with the present invention.
  • the PMOS pull-up transistor 10 and the NMOS pull-down transistor 20 are controlled by a control device 5 having two outputs 6 and 7.
  • the first output 6 of the control device 5 is connected to the gate 13 of the PMOS pull-up transistor 10 and the second output 7 of the control device 5 is connected to the gate 23 of the NMOS pull-down transistor 20.
  • the control device 5 has a first input 2 for receiving a data signal A, which input will also be referred to as the data input.
  • the control device 5 has a second input 3 for receiving an enable signal E, which input is also referred to as the enable input.
  • the value of the enable signal determines whether the mode of operation of the buffer 1 is "active" or "tristate". Depending on the implementation the active mode of the buffer 1 may be defined by an enable signal E whose value is HIGH and the tristate mode of the buffer 1 may be defined by an enable signal E whose value is low, or the other way around.
  • the control device 5 is further adapted to produce a HIGH signal at its two outputs 6 and 7 in the active mode of the buffer 1 when the input signal A is LOW. This causes NMOS pull-down transistor 20 to be driven into conduction, while the primary PMOS transistor is cut off, as a result of which the output voltage X at the output terminal 4 is pulled down to the level V S s-
  • control device 5 is further adapted to supply a HIGH signal at its first output 6 and to supply a LOW signal at its second output 7, regardless of the value of the data signal A, as a result of which the pull-up transistor 10 and the pull-down transistors 20 are both turned off.
  • the structure of such a PMOS transistor is, in principle, symmetrical, with the proviso that the P+ regions 42 and 43 are substantially identical, as a result of which, in principle, the source and drain terminals in a circuit may be interchanged.
  • the N-well terminal 45 is connected to only one of these two P+ regions 42 and 43 and it is common practice to refer to the P+ region connected to the N+ type N-well terminal 45 as the source.
  • the transition between the P+ region 42 and the N-well region 41 forms a parasitic POSITION junction 662, which will also be referred to hereinafter as the parasitic source junction 62.
  • the transition between the P+ region 43 and the N-well region 41 forms a parasitic drain junction 63.
  • FIG. 3 shows an embodiment of an I/O buffer 101 in accordance with the present invention, in which the an overvoltage protection circuit 110 is arranged between the drain 12 of the PMOS pull-up transistor 10 and the output 4.
  • This overvoltage protection circuit 110 includes a PMOS blocking field-effect transistor 120, a first control field-effect transistor 130 of the PMOS type, and a second control field-effect transistor 140 of the NMOS type.
  • the PMOS blocking transistor 120 has its drain 122 connected to the drain 12 of the PMOS pull-up transistor 10 and has its source 121 connected to the output 4.
  • the first (PMOS) control transistor 130 has its drain 132 connected to the gate 123 of the PMOS blocking transistor 120 and has its source 131 connected to the output 4.
  • the second (NMOS) control transistor 140 has its drain 142 connected to the gate 123 of the PMOS blocking transistor 120 and has its source 141 connected to ground Vss-
  • the respective gates 133 and 143 of the two control transistors 130 and 140 receive the enable signal A.
  • Figure 3 further shows the circuit diagram of an example of the control device 5.
  • the control device 5 comprises a NAND gate 151, an AND gate 152 and an inverter 153.
  • the NAND gate 151 receives the data signal and the enable signal E at its two respective inputs and its output forms the first output 6 of the control device 5 and is consequently connected to the gate 13 of the PMOS pull-up transistor 10.
  • the AND gate 152 receives the enable signal E and the data signal A, inverted via the inverter 153, at its two respective inputs and its output forms the second output 7 of the control device 5 and is consequently connected to the gate 23 of the NMOS pull-down transistor 20.
  • the level of the first output 6 of the control device 5 is HIGH, as a result of which the PMOS pull-up transistor 10 is cut off, and the level of the second output 7 of the control device 5 is LOW, as a result of which the NMOS pulldown transistor 20 is cut off.
  • the level of the gate 143 of the second NMOS control transistor 140 is then LOW, as a result of which the second NMOS control transistor 140 is cut off.
  • the level of the gate 133 of the first PMOS control transistor 130 is low, as a result of which the first PMOS control transistor 130 is turned on if external sources cause the voltage at the output 4 to increase, as a result of which the level of the gate 123 of the blocking transistor 120 is pulled up to the level of the source 121 of this, so that this blocking transistor 120 is cut off and the comparatively high voltage level of the output 4 cannot reach the PMOS pull-up transistor 10.
  • a major advantage of the circuit proposed by the present invention is that the gates 151 and 152 of the control device 5 only have to control the pull-up and pull-down transistors 10 and 20 and are not loaded by components of the overvoltage protection circuit 110.
  • Another major advantage of the circuit proposed by the present invention is that the switching state of the components of the overvoltage protection circuit 110 depends exclusively on the state of the enable signal E and not on the data signal A because the control voltage for the gates 133, 143 of the two control transistors 130, 140 are derived exclusively from the enable signal E.
  • An further major advantage of the circuit proposed by the present invention is that in the tristate mode the gate 133 of the first PMOS control transistor 130 is constantly held at a LOW level by the enable signal E, as a result of which this first PMOS control transistor 130 is already turned on in the case of small increases of the voltage at the output 4, so that even for small increases of the voltage at the output 4 the gate 123 of the blocking transistor 120 is pulled up to the voltage level of the output 4 and, consequently, the blocking transistor 120 is already cut off for small voltage increases at the output 4.
  • This is in contradistinction to the circuit known from WO94/29961, where the blocking transistor is not cut off until the voltage level at the output is higher than V DD plus the threshold voltage of the first control transistor.
  • the overvoltage protection circuit 110 has only a very small number of components and that these components can be realized particularly simply during the fabrication of the buffer 101 without the necessity of additional fabrication steps. It will be evident to those skilled in the art that the scope of the present invention is not limited to the examples described hereinbefore but that various alterations and modifications thereof are possible without departing from the scope of the invention as defined in the appended Claims.
  • control device 5 can be implemented in another manner.
  • the invention can be used not only in a 3 V/5 V environment or 3.3 V/5 V environment but also in other voltage - level environments. Moreover, the invention is also useful if upon turn-off of a system the voltage of a supply line can decrease more rapidly than that of an output.

Abstract

Cette invention se rapporte à un tampon E/S à trois états (101) conçus pour coopérer avec des modules (31) qui sont actifs à une tension d'alimentation supérieure à la tension d'alimentation du tampon (101). La sortie (4) du tampon (101) est pourvue d'un circuit (110) de protection contre les surtensions, qui empêche les fuites de courant de la sortie (4) vers la ligne de tension d'alimentation (VDD) du tampon (101). Le circuit (110) de protection contre les surtensions comprend un transistor de blocage PMOS (120), un premier transistor de commande PMOS (130) et un second transistor de commande NMOS (140). Ces deux transistors de commande (130, 140) sont commandés par un signal de commande qui est dérivé uniquement du signal de validation (E).
EP99961033A 1998-12-18 1999-12-01 Tampon e/s protege contre les surtensions Withdrawn EP1057262A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP99961033A EP1057262A1 (fr) 1998-12-18 1999-12-01 Tampon e/s protege contre les surtensions

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP98204343 1998-12-18
EP98204343 1998-12-18
PCT/EP1999/009357 WO2000038322A1 (fr) 1998-12-18 1999-12-01 Tampon e/s protege contre les surtensions
EP99961033A EP1057262A1 (fr) 1998-12-18 1999-12-01 Tampon e/s protege contre les surtensions

Publications (1)

Publication Number Publication Date
EP1057262A1 true EP1057262A1 (fr) 2000-12-06

Family

ID=8234497

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99961033A Withdrawn EP1057262A1 (fr) 1998-12-18 1999-12-01 Tampon e/s protege contre les surtensions

Country Status (4)

Country Link
EP (1) EP1057262A1 (fr)
JP (1) JP2002533971A (fr)
KR (1) KR20010040990A (fr)
WO (1) WO2000038322A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847248B2 (en) 2001-01-09 2005-01-25 Broadcom Corporation Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
US6859074B2 (en) 2001-01-09 2005-02-22 Broadcom Corporation I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
JP3656742B2 (ja) * 2001-10-30 2005-06-08 日本電気株式会社 携帯情報端末
US6850226B2 (en) 2001-11-09 2005-02-01 Nokia Corporation Multifunction mobile communications device with slidable display screen
US7138836B2 (en) 2001-12-03 2006-11-21 Broadcom Corporation Hot carrier injection suppression circuit
CN100373300C (zh) * 2005-12-16 2008-03-05 北京中星微电子有限公司 一种解决共享总线浮空导致io漏电的设计方法及装置
US20100159992A1 (en) * 2008-12-18 2010-06-24 Nokia Corporation Mobile communication device with a sliding display screen and screen-dividing member
US8283947B1 (en) * 2011-06-03 2012-10-09 Nxp B.V. High voltage tolerant bus holder circuit and method of operating the circuit

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US5387826A (en) * 1993-02-10 1995-02-07 National Semiconductor Corporation Overvoltage protection against charge leakage in an output driver
KR100282287B1 (ko) * 1993-06-07 2001-02-15 클라크 3세 존 엠. 과전압에 대한 보호
JPH0786910A (ja) * 1993-09-10 1995-03-31 Oki Electric Ind Co Ltd 出力駆動回路
JP2901171B2 (ja) * 1993-10-08 1999-06-07 日本電信電話株式会社 ディープサブミクロンｍｏｓｆｅｔ出力バッファ回路
JP3205156B2 (ja) * 1994-01-07 2001-09-04 川崎製鉄株式会社 半導体集積回路
US5418476A (en) * 1994-07-28 1995-05-23 At&T Corp. Low voltage output buffer with improved speed
JP3366484B2 (ja) * 1995-03-27 2003-01-14 沖電気工業株式会社 出力ドライバ回路
CA2171052C (fr) * 1995-09-29 2001-05-15 Colin Harris Pilote de sortie a trois etats pour logique cmos fonctionnant sous 3,3 ou 5 volts
JP3586985B2 (ja) * 1996-08-26 2004-11-10 松下電器産業株式会社 半導体装置の出力回路
JP3544819B2 (ja) * 1997-03-31 2004-07-21 株式会社 沖マイクロデザイン 入力回路および出力回路ならびに入出力回路
JPH11317652A (ja) * 1998-02-13 1999-11-16 Matsushita Electric Ind Co Ltd 出力回路

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Also Published As

Publication number Publication date
JP2002533971A (ja) 2002-10-08
WO2000038322A1 (fr) 2000-06-29
KR20010040990A (ko) 2001-05-15

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