KR19990067078A - Tuning control method - Google Patents

Abstract

The tuning mechanism is provided with a tuning circuit 1 formed by cascading two or more circuits, a frequency control circuit 2 including a phase difference detecting circuit 3 and a control voltage generating circuit 4. The phase difference detecting circuit 3 converts each of the input signal and the output signal of one of the abnormal circuits included in the lookup table 1 into a square wave signal and then calculates an exclusive OR of the two rectangular wave signals to output to the control voltage generating circuit 4 do. The control voltage generating circuit 4 smoothes and amplifies the output of the phase difference detecting circuit 3, adds a predetermined bias voltage, and generates a control voltage for determining the tuning frequency of the tuning circuit 1. This control voltage is input to two or more circuits inside the circuit 1. Based on the control signal, the inquiry circuit 1 adjusts the phase shift amount while keeping the time constant of each ideal circuit equal, and matches the tuning frequency with the frequency of the input signal of the reference circuit 1.

Description

Tuning control method

A filter and a tuning circuit having various configurations using LC resonance or the like are known. For example, an intermediate frequency amplifier circuit of a superheterodyne receiver includes a function as a filter, and a conventional intermediate frequency amplifier circuit generally realizes a desired frequency characteristic by using a plurality of intermediate frequency transformers (IFT) and capacitors have. For example, in the case of an AM receiver, a center frequency of 455 kHz is set and a predetermined amount is attenuated when 9 kHz is detuned from the center frequency. An AM receiver that realizes a desired frequency characteristic by using one ceramic filter instead of plural sets of intermediate frequency transformers is also known.

However, in the conventional technique using the superheterodyne method described above, since the intermediate frequency wave amplifier circuit, which is a filter for tuning, includes an intermediate frequency wave transformer or a ceramic filter, the entirety including them is integrated on the semiconductor substrate It was difficult.

A local oscillation circuit combined with the intermediate frequency amplifier circuit is realized by an LC oscillator using a local oscillation transformer, and a PLL structure using crystal oscillation is realized when the oscillation circuit has a high accuracy. Particularly, when the local oscillation circuit is a PLL structure, since it includes a voltage-controlled oscillator (VCO) that performs sinusoidal oscillation, integration is difficult and a hybrid IC is used in a part.

In this way, it is difficult to integrate not only the intermediate frequency amplifier circuit operating as a filter but also the local oscillation circuit constituting the tuning mechanism in combination with them, and a tuning control system capable of integrating the entire tuning mechanism is preferable. In addition, even if the entirety of a conventional filter or a circuit including this filter is integrated, a large variation occurs in the circuit constant, so that different characteristics are produced for each manufactured chip. Furthermore, since the center frequency may considerably vary depending on the temperature or the like, there is no conventional tuning control method capable of reliably achieving the desired frequency characteristics even when the center frequency is integrated.

The present invention relates to a tuning control method for passing only a predetermined frequency signal.

1 is a configuration diagram of a tuning mechanism which is an embodiment to which the tuning control method of the present invention is applied;

2 is a circuit diagram showing a detailed configuration of a tuning circuit;

Fig. 3 is a circuit diagram showing the configuration of the abnormal circuit of the preceding stage shown in Fig.

4 is a vector diagram showing a relationship between an input / output voltage of the abnormal circuit shown in FIG. 3 and a voltage appearing in a capacitor or the like.

Fig. 5 is a circuit diagram showing the configuration of the abnormal circuit at the rear end shown in Fig.

6 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit at the subsequent stage and the voltage appearing in the capacitor or the like.

Fig. 7 is a circuit diagram in which the entirety of two abnormal circuits and the voltage divider circuit shown in Fig. 2 are replaced with a circuit having a transfer function K1; Fig.

8 is a circuit diagram of the circuit shown in Fig. 7 converted by Mila's theorem. Fig.

Fig. 9 is a diagram showing tuning characteristics of the tuning circuit shown in Fig. 2; Fig.

10 is a diagram showing a phase relationship between signals input to and output from two or more circuits;

11 is a diagram showing the phase relationship between input / output signals of the respective anomalous circuits when the tuned frequency is higher than the frequency of the signal inputted to the anomaly circuit at the previous stage.

Fig. 12 is a diagram showing the phase relationship between input / output signals of the respective anomalous circuits when the tuned frequency is lower than the signal frequency inputted to the anomaly circuit at the previous stage. Fig.

13 is a circuit diagram showing a configuration of a frequency control circuit;

14 is a timing chart when the tuning frequency of the tuning circuit is higher than the frequency of the signal input to the tuning circuit.

15 is a timing chart when the tuning frequency of the tuning circuit is lower than the frequency of the signal input to the tuning circuit.

16 is a circuit diagram showing another configuration example of the frequency control circuit;

Fig. 17 is a timing chart when the tuning frequency is higher than the frequency of the signal input to the tuning circuit shown in Fig. 16; Fig.

Fig. 18 is a timing chart when the tuning frequency is lower than the frequency of the signal input to the tuning circuit shown in Fig. 16; Fig.

19 is a diagram showing a configuration of a tuning mechanism that also serves as an FM detection.

Fig. 20 is a circuit diagram showing a detailed configuration of the high-frequency control circuit shown in Fig. 19; Fig.

21 is a diagram showing the configuration of an FM receiver using the tuning mechanism shown in Fig. 19. Fig.

22 is a diagram showing a configuration of a tuning mechanism using AM detection by synchronous rectification in combination.

23 is a diagram showing the detailed configuration of the synchronous rectification circuit shown in Fig.

24 is a diagram showing the configuration of an AM receiver using the tuning mechanism shown in Fig. 22. Fig.

25 is a circuit diagram showing a configuration of an abnormal circuit including an LR circuit;

Fig. 26 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 25 and the voltage appearing in the capacitor or the like. Fig.

27 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

Fig. 28 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 27 and the voltage appearing on the capacitor or the like. Fig.

29 is a circuit diagram showing a second modification of the tuning circuit;

30 is a circuit diagram showing a configuration of an abnormal circuit including an LR circuit;

31 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

32 is a circuit diagram showing a fourth modification of the tuning circuit;

33 is a circuit diagram showing a fifth modification of the tuning circuit;

34 is a circuit diagram showing a sixth modification of the tuning circuit;

35 is a circuit diagram showing a seventh modification of the tuning circuit;

36 is a circuit diagram showing a eighth modification of the tuning circuit;

Fig. 37 is a circuit diagram showing the configuration of the preceding stage abnormal circuit shown in Fig.

38 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in FIG. 37 and the voltage appearing on the capacitor or the like.

Fig. 39 is a circuit diagram showing the configuration of the abnormal circuit at the rear end shown in Fig.

40 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in FIG. 39 and the voltage appearing on the capacitor or the like.

41 is a circuit diagram showing a configuration of an abnormal circuit including an LR circuit;

Fig. 42 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 41 and the voltage appearing on the capacitor or the like. Fig.

FIG. 43 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit; FIG.

44 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in FIG. 43 and the voltage appearing on the capacitor or the like.

45 is a circuit diagram showing a tenth modification of the tuning circuit;

46 is a circuit diagram showing a modification 11 of the tuning circuit;

47 is a circuit diagram showing a twelfth modification of the tuning circuit;

Fig. 48 is a circuit diagram showing the configuration of the abnormal circuit of the preceding stage shown in Fig.

Fig. 49 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 48 and the voltage appearing on the capacitor or the like. Fig.

Fig. 50 is a circuit diagram showing the configuration of the abnormal circuit at the rear end shown in Fig.

Fig. 51 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 50 and the voltage appearing in the capacitor or the like. Fig.

52 is a circuit diagram showing a configuration of an ideal circuit including an LR circuit;

Fig. 53 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 52 and the voltage appearing in the inductor or the like. Fig.

54 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

Fig. 55 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 54 and the voltage appearing in the inductor or the like. Fig.

56 is a circuit diagram showing a fourteenth modification of the tuning circuit;

57 is a circuit diagram showing a fifteenth modification of the tuning circuit;

Fig. 58 is a circuit diagram of a tuning circuit in which variable resistors in each abnormal circuit shown in Fig. 3 are formed by MOS type FETs; Fig.

FIG. 59 is a circuit diagram of a tuning circuit which changes the entire tuning frequency because the capacitance of the capacitor is changed. FIG.

Fig. 60 is a circuit diagram of a tuning circuit using elements other than FETs as variable resistors in each abnormal circuit shown in Fig. 2; Fig.

Fig. 61 is a circuit diagram showing a portion necessary for operation of the abnormal circuit during the construction of the operational amplifier.

DISCLOSURE OF INVENTION

SUMMARY OF THE INVENTION The present invention is designed to solve such a problem, and its object is to provide a new tuning control method suitable for integration.

The tuning control method of the present invention is a tuning control method in which two or more crossover-connected all-pass circuits of the crossover type and an output of the abnormal circuit at the rear end are fed back to the input side of the abnormal circuit at the previous stage, A tuning circuit for passing only a signal in the vicinity of a predetermined frequency,

Wherein when a signal having a frequency in the vicinity of the predetermined frequency is input to the tuning circuit, a tuning frequency of the tuning circuit is input to the tuning circuit based on a phase difference between input / output signals of one of the two circuits included in the tuning circuit And a frequency control circuit for matching the frequency of the signal.

Then, by performing control so that the phase difference between the input / output signals of one of the anomalous circuits included in the tuning circuit is, for example, 90, the tuning frequency always follows the frequency of the input signal, .

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, one embodiment of the tuning control method of the present invention will be described in detail with reference to the drawings.

[A. Overall Configuration and Operation of Tuning Mechanism]

In the tuning control method of the present invention, when the time constants of two or more circuits included in the tuning circuit are set to be the same, the phase difference between the input and output signals is 90. That is, Or 270. When the AC signal is input to a certain frequency, the phase shift amount of one of the abnormal circuits is controlled to approach 90 or 270. Thus, the characteristic of controlling the tuning frequency to match the frequency of the input signal .

1 is a diagram showing a configuration of a tuning mechanism according to an embodiment to which the tuning control method of the present invention is applied.

The tuning mechanism shown in the figure includes a tuning circuit 1 functioning as a filter for passing a signal in the vicinity of a certain frequency and a frequency control circuit 2 for controlling the passing center frequency of the tuning circuit 1.

The inquiry circuit 1 includes two or more circuits, subtracts the output of the abnormal circuit at the rear end as the output of the inquiry circuit 1, feeds back the signal through the feedback resistor, Signal and a feedback signal fed back through a feedback resistor are added and input to the anomaly circuit at the previous stage so that a predetermined tuning operation is performed at a frequency at which the phase shift amount of all two or more anodes becomes 360. [

When the time constants of the respective anomalous circuits are set to be the same, the amount of phase shift in each of the anomalous circuits becomes 90. When the attention point is changed, it is possible to make the tuning frequency coincide with the frequency of the input signal if the time constant of each ideal circuit is set to be the same and the phase shift amount of one of the ideal circuits is controlled to 90. [

The tuning circuit 1 has a configuration in which the tuning frequency can be arbitrarily set in a certain range by changing the phase shift amount of two or more circuits by a control signal inputted from the outside. The detailed configuration and detailed operation of the inquiry road 1 will be described later.

The frequency control circuit 2 receives two kinds of signals input to and output from one of the abnormal circuits contained in the inquiry circuit 1. When the phase difference between these two signals is shifted to 90 degrees, 1 is controlled.

In order to perform such control, the frequency control circuit 2 includes a phase difference detection circuit 3 and a control voltage generation circuit 4.

The phase difference detecting circuit 3 has a duty ratio of 50% when the phase shift amount of one of the abnormal circuits included in the inquiry circuit 1 is 90. When the phase shift amount is shifted to 90., the duty ratio is 50% And outputs a rectangular wave signal shifted to the right side.

The control voltage generating circuit 4 generates a voltage in accordance with the duty ratio of the rectangular wave signal output from the phase difference detecting circuit 3 and adds the generated voltage and a predetermined bias voltage as a control signal to the control circuit 1 do.

The detailed configuration and operation of the phase difference detection circuit 3 and the control voltage generation circuit 4 constituting the above-described frequency control circuit 2 will be described later.

[B. Detailed Configuration and Operation of Tuning Circuit]

Next, the details of the inquiry route 1 shown in Fig. 1 will be described. Fig. 2 is a circuit diagram showing the detailed configuration of the inquiry path 1. Fig. Reference numeral 1 denotes two abnormal circuits 110C and 130C for carrying out a 360. phase shift in a predetermined frequency by shifting the phase of an AC signal input to each of them by a predetermined amount, And the feedback resistor 170 and the input resistor 174 (the input resistor 174 is assumed to have a resistance value n times as large as the resistance value of the feedback resistor 170) from the resistors 162 and 164 provided on the output side of the voltage dividing circuit 160 And an adder circuit for adding a partial pressure output (feedback signal) and a signal (input signal) input to the input terminal 190 at a predetermined ratio.

Fig. 3 is a diagram showing the structure of the anterior-anterior circuit 110C shown in Fig. The anomaly circuit 110C of the preceding stage shown in the same diagram includes an operational amplifier 112, which is a kind of differential amplifier, a variable resistor 116 which shifts the phase of the AC signal inputted to the input stage 122 by a predetermined amount and inputs it to the non-inverting input terminal of the operational amplifier 112, A resistor 118 inserted between the input terminal 122 and the inverting input terminal of the operational amplifier 112, resistors 121 and 123 connected to the output terminal of the operational amplifier 112 and constituting a voltage dividing circuit, And a resistor 120 connected between the inverting input terminal of the operational amplifier 112 and the inverting input terminal.

In the ideal circuit 110C having such a configuration, the resistance values of the resistors 118 and 120 are set to be the same. 3, the variable resistor 116 uses the channel of the FET as a resistor and is connected to the control input terminal 194 shown in FIG. 2 through the control input terminal 194 And a resistance value is set by applying a control voltage supplied from the outside to the gate.

When a predetermined alternating signal is input to the input terminal 122 shown in Fig. 3, a voltage VR1 appearing at both ends of the variable resistor 116 is applied to the non-inverting input terminal of the operational amplifier 112. [ At both ends of the resistor 118, a voltage VC1 equal to the voltage VC1 appearing at both ends of the capacitor 114 appears. The same current I flows through the two resistors 118 and 120. Further, since the resistance values of the resistors 118 and 120 are the same as described above, the voltage VC1 appears on both ends of the resistor 120 as well. Assuming that the inverting input terminal (voltage VR1) of the operational amplifier 112 is taken as a reference, the result of vectorially adding the both-end voltage VC1 of the resistor 118 to the input voltage Ei, (Partial voltage output) Eo 'at the connection point between the resistor 121 and the resistor 123.

Fig. 4 is a vector diagram showing the relationship between the input / output voltage and the voltage appearing in the capacitor or the like in the preceding stage anomaly circuit 110C.

As described above, when the voltage VR1 applied to the non-inverting input terminal of the operational amplifier 112 is taken as a reference, the input voltage Ei and the divided voltage Eo 'are different only in the direction in which the voltage VC1 is synthesized, and their absolute values are the same. Therefore, the relation between the input voltage Ei and the magnitude of the partial pressure output Eo 'and this phase can be expressed by an isosceles triangle having the input voltage Ei and the partial pressure output Eo' as the oblique side and twice the voltage VC1 as the bottom side, The amplitude of the input signal is equal to the amplitude of the input signal regardless of the frequency, and the amount of phase shift is indicated by? 1 shown in FIG. The phase shift amount? 1 changes from 180 to 360. in the clockwise direction (retarded phase) with respect to the input voltage Ei according to the frequency.

Since the output terminal 124 of the error circuit 110C is connected to the output terminal of the operational amplifier 112, if the resistance value of the resistor 121 is R21 and the resistance value of the resistor 123 is R23, then the resistance 120 Eo = (1 + R21 / R23) Eo 'when R21 and R23 are sufficiently small with respect to the resistance value of the resistor R0. Therefore, by adjusting the values of R21 and R23, a gain greater than 1 can be obtained. As shown in Fig. 4, even when the frequency changes, the amplitude of the output voltage Eo is constant and only the phase can be shifted by a predetermined amount.

Similarly, FIG. 5 shows the configuration of the abnormal circuit 130C at the rear end shown in FIG. The abnormal circuit 130C in the subsequent stage shown in the diagram includes an operational amplifier 132, which is a kind of differential amplifier, a capacitor 134, which shifts the phase of a signal input to the input terminal 142 by a predetermined amount and inputs the shifted signal to the noninverting input terminal of the operational amplifier 132, Resistors 141 and 143 constituting a voltage dividing circuit connected to the resistor 138 inserted between the input terminal 142 and the inverting input terminal of the operational amplifier 132 and the output terminal of the operational amplifier 132, And a resistor 140 connected between the inverting input terminal of the operational amplifier 132 and the inverting input terminal of the operational amplifier 132.

In the ideal circuit 130C having such a configuration, the resistance values of the resistors 138 and 140 are set to be the same. The resistance value of the variable resistor 136 is set by applying a control voltage supplied from the outside through a control input terminal 195 shown in FIG. 2 to the gate, the resistance value of which can be changed according to the control voltage from the outside.

When a predetermined AC signal is inputted to the input terminal 142 shown in FIG. 5, a voltage VC2 appearing at both ends of the capacitor 134 is applied to the non-inverted input terminal of the operational amplifier 132. [ At both ends of the resistor 138, a voltage VR2 equal to the voltage VR2 appearing at both ends of the variable resistor 136 appears. Since the same current I flows through the two resistors 138 and 140 and the resistance values of the resistors 138 and 140 are the same as described above, the voltage VR2 appears across the resistor 140 as well. Considering the inverted input terminal (voltage VC2) of the operational amplifier 132 as a reference, the result of vectorially adding the both-end voltage VR2 of the resistor 138 to the input voltage Ei and the voltage VR2 across the resistor 140, (Partial voltage output) Eo 'at the connection point between the resistors 41 and 43.

6 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 130C at the subsequent stage and the voltage appearing on the capacitor or the like.

Considering the voltage VC2 applied to the noninverting input terminal of the operational amplifier 132 as described above, the input voltage Ei and the divided voltage output Eo 'are different in the direction of synthesizing the voltage VR2, and their absolute values are the same. Therefore, the relationship between the magnitude and the phase of the input voltage Ei and the divided voltage output Eo 'can be expressed by an isosceles triangle having the input voltage Ei and the divided voltage output Eo' as the oblique and the voltage VR2 as the base, and the divided voltage Eo ' It can be seen that the amplitude is the same as the amplitude of the input signal regardless of the frequency, and the amount of phase shift is represented by? 2 shown in FIG. This phase shift amount? 2 changes from 0 to 180 in the clockwise direction on the basis of the input voltage Ei according to the frequency.

Since the output terminal 144 of the abnormal circuit 130C is connected to the output terminal of the operational amplifier 132, when the resistance value of the resistor 141 is R41 and the resistance value of the resistor 143 is R43, the output voltage Eo and the above- When R41 and R43 are sufficiently small with respect to the resistance value, there is a relation of Eo = (1 + R41 / R43) Eo '. Therefore, by adjusting the values of R41 and R43, a gain greater than 1 can be obtained. Furthermore, as shown in Fig. 6, even when the frequency changes, the amplitude of the output voltage Eo is constant and only the phase can be shifted by a predetermined amount.

In this manner, the phases are shifted by a predetermined amount in each of the two abnormal circuits 110C and 130C. As shown in Figs. 4 and 6, the phase shift amount in the entire circuit 1 is 360 .

2, the output of the abnormal circuit 130C at the subsequent stage is taken out from the output terminal 192 as an output of the inquiry circuit 1, and the output of the abnormal circuit 130C through the voltage dividing circuit 160 is fed back to the feedback resistor 170 to the input side of the abnormal circuit 110C at the previous stage. Then, the feedback signal is added to the signal input through the input resistor 174, and the added signal is input to the previous stage anomaly circuit 110C.

As described above, the sum of the amounts of phase shift at a predetermined frequency is 360. The two abnormal circuits 110C and 130C cause the sum of the phase shift amounts at the predetermined frequency to be 360. At this time, the two abnormal circuits 110C and 130C, the voltage divider circuit 160, By setting the loop gain to 1 or less, a tuning operation for passing only the signal of the predetermined frequency component is performed.

Since the output of the abnormal circuit 130C before being input to the voltage dividing circuit 160 is extracted from the output terminal 192 of the inquiry circuit 1, it is possible to gain gain in the inversion circuit 1 itself, and at the same time, Lt; / RTI >

7 is a circuit diagram in which the circuit having the transfer function K1 is replaced with a circuit having the entirety of the two abnormal circuits 110C and 130C and the voltage divider circuit 160 having the above-described configuration, and a feedback resistor 170 Is connected in series with an input resistor 174 having an n-fold resistance value nR0 of the feedback resistor 170. [

FIG. 8 is a circuit diagram of the circuit shown in FIG. 7 converted by Mila's theorem. After the conversion,

As shown in FIG.

The transfer function K2 of the preceding stage anomalous circuit 110C is a time constant of the CR circuit constituted by the variable resistor 116 and the capacitor 114 by T ₁ (assuming that the resistance of the variable resistor 116 is R and the capacitance of the capacitor 114 is C, T ₁ = CR ),

. Here, s = jω, a ₁ is the gain of the error circuit 110C, and a ₁ = (1 + R21 / R23)> 1.

The transfer function K3 of the circuit 143C for the subsequent stage is the time constant of the CR circuit consisting of the capacitor 134 and the resistor 136 as T ₂ (the capacitance of the capacitor 134 is C and the resistance of the resistor 136 is R, T ₂ = CR) In other words,

. Here, a ₂ is the gain of the ideal circuit 130C, and a ₂ = (1 + R41 / R43)> 1.

Assuming that the signal amplitude is attenuated to 1 / a ₁ a ₂ by passing through the voltage dividing circuit 160, the overall transfer function K 1 when the two abnormal circuits 110 C, 130 C and the voltage dividing circuit 160 are cascade-

. In order to simplify the calculation, the time constants T ₁ and T ₂ of the respective anomalous circuits are all set to T in the equation (4). When this equation (4) is substituted into the above-mentioned equation (1)

According to the expression (5), A = -1 / (2n + 1) when? = 0 (in the region of the direct current) and the maximum attenuation is given. And, when ω = ∞, A = -1 / (2n + 1) is obtained and the maximum attenuation is given. At the tuning point of ω = 1 / T, A = 1, which is irrelevant to the resistance ratio of the feedback resistor 170 and the input resistor 174. In other words, even if the value of n is changed as shown in Fig. 9, the tuning point is not shifted and the amount of attenuation of the tuning point does not change.

In addition, by varying the resistance values of the variable resistor 116 included in the error circuit 110C at the previous stage and the variable resistor 136 included in the error circuit 130C at the subsequent stage, the time constant of each CR circuit included in the error circuits 110C and 130C can be changed, The frequency? Can be arbitrarily changed within a certain range.

7, when the global pass circuit represented by the transfer function K1 has the input impedance, a voltage divider circuit is formed by the feedback resistor 170 and the input impedance of the global pass circuit, so that the feedback loop including the global pass circuit Is smaller than the absolute value of the transfer function K1. The input impedance of the all-pass circuit is the input impedance of the preceding stage anomaly circuit 110C and the input impedance formed by connecting the series impedance of the CR circuit constituted by the variable resistor 116 and the capacitor 114 to the input resistor 118 of the operational amplifier 112 in parallel . Therefore, in order to compensate for the loss of the loop gain of the feedback loop due to the impedance of the global pass circuit, it is necessary to set the gain of the global pass circuit itself to 1 or more.

For example, considering the above circuit when the resistance 121, bypass the divider circuit by 123 and I included in 110C (partial pressure ratio is of the case of 1, a ₁ in the above-described formula (2) 1 ), The ideal circuit 110C must operate within the range of the inverting amplifier whose gain is -1 times the gain from the 1-fold flow circuit according to the input frequency according to the equation (2). Therefore, the resistance ratio between the resistors 118 and 120 1 is not preferable. If the resistance values of the resistors 118 and 120 are R18 and R20, the gain when the abnormal circuit 110C operates as an inverting amplifier is -R20 / R18, and the gain when operating as a flow circuit is the resistance of the resistors 118 and 120 Even if the resistance ratio of the resistor 118 and the resistor 120 is not 1, the phase of the input / output changes in the entire region where the error circuit 110C operates, and the abnormal condition in which the output amplitude does not change is satisfied It can not be done.

A voltage dividing circuit consisting of a resistor 121 and a resistor 123 is added to the output side of the ideal circuit 110C and feedback is performed to the inverting input terminal of the operational amplifier 112 through this voltage dividing circuit so that the resistance ratio between the resistor 118 and the resistor 120 is maintained at 1 The gain of the circuit 110C can be set to 1 or more. Likewise, a voltage dividing circuit consisting of a resistor 141 and a resistor 143 is added to the output side of the ideal circuit 130C, and the inverting input terminal of the operational amplifier 132 is returned through the voltage dividing circuit to maintain the resistance ratio of the resistor 138 and the resistor 140 at 1 It is possible to set the gain of the excess circuit 130C to 1 or more.

In the formula (2) or (3),? 1 (180.?? 1? 360.) In the clockwise direction (phase slow direction) with reference to the input voltage Ei as shown in FIG. 4 and FIG. Lt; = 180 < = 180 in the clockwise direction as a reference)

.

In the case of T ₁ = T ₂ (= T), the sum of the amounts of phase shift due to the two abnormal circuits 110C and 130C is 360. When? = 1 / T, the above-described tuning operation is performed. ., ≪ / RTI >

10 is a diagram showing the phase relation between signals input to and output from the two abnormal circuits 110C and 130C, and shows a case where the frequency of the signal input to the abnormal circuit 110C at the preceding stage is the same as the tuned frequency.

As shown in Fig. 10 (A), the phase of the output signal S2 of the previous-stage anomaly circuit 110C is shifted in the clockwise direction by? 1 = 270 with reference to the input signal S1. Further, as shown in Fig. 10 (B), the phase of the output signal S3 of the posteriori error circuit 130C is shifted by 90 degrees in the clockwise direction with respect to the input signal S2. Therefore, when the two abnormal circuits 110C and 130C are cascaded, the 360 phase is shifted as a whole as shown in Fig. 10 (C).

However, when the tuning frequency set higher than the frequency of the signal input to the anterior stage circuit 110C at the previous stage is higher, the result obtained by combining? 1 and? 2 does not become 360. However,

11 is a diagram showing the phase relationship between input / output signals of the respective anomalous circuits when the tuning frequency is higher than the frequency of the signal inputted to the preceding-stage fault circuit 110C.

In the case where the frequency of the input signal is relatively lower than the tuning frequency in the case where the tuning frequency is higher than the frequency of the signal inputted to the previous stage of the abnormal circuit 110C, as shown in Figs. 4 and 6, 1 becomes smaller than 270. The phase shift amount PHI 2 of the subsequent error circuit 130C becomes smaller than 90 DEG. 11A and 11B, and the sum of the amount of phase shift when the two abnormal circuits 110C and 130C are cascade-connected is expressed as shown in FIG. 11C Likewise, it becomes smaller than 360.

However, in such a case, it is necessary to increase the above-mentioned? 1 and? 2 in order to bring the tuning frequency close to the frequency of the actually input signal. More specifically, both the voltage VR1 between the variable resistor 116 and the variable resistor 136 VR2 may be increased. For example, when the variable resistor 116 or 136 is formed of an n-channel FET, the gate voltage may be lowered to increase the channel resistance.

On the other hand, even when the tuning frequency is lower than the frequency of the signal input to the previous stage of the anomalous circuit 110C, the sum of the above-described? 1 and? 2 does not reach 360. However,

12 is a diagram showing the phase relationship between the input / output signals of the respective anomalous circuits in the case where the tuned frequency is lower than the signal frequency inputted to the preceding-stage anomaly circuit 110C.

The case where the frequency of the tuning frequency is lower than the frequency of the signal inputted to the previous stage of the error circuit 110C is a case where the frequency of the input signal is relatively higher than the tuning frequency. In this case, as apparent from FIGS. 4 and 6, The phase shift amount PHI 1 of the abnormal circuit 110C becomes larger than 270 DEG and the phase shift amount PHI 2 of the subsequent stage abnormal circuit 130C becomes larger than 90 DEG. Therefore, phi 1 and phi 2 are represented as shown in Figs. 12A and 12B, respectively, and the sum of the amounts of phase shift when the two abnormal circuits 110C and 130C are cascade-connected is shown in Fig. 12C Likewise, it becomes larger than 360.

In order to make the tuning frequency close to the frequency of the actually input signal in such a case, the absolute values of the above-mentioned? 1 and? 2 must be made small. Concretely, the voltage VR1 between both ends of the variable resistor 116 and the variable resistor 136 The both-end voltage VR2 can be reduced. For example, when the variable resistors 116 and 136 are formed of n-channel FETs, the gate voltage may be increased to reduce the channel resistance.

As described above, the resistance values of the resistors 118 and 120 in the abnormal circuit 110C are set to the same value and the resistance values of the resistors 138 and 140 in the abnormal circuit 130C are set to the same value in the above- It is possible to prevent amplitude fluctuation when the tuning frequency is changed and to obtain a tuning output having a substantially constant amplitude.

In particular, by suppressing the amplitude fluctuation of the tuning output, the above-described resistance ratio n can be increased to increase the Q value of the tuning circuit 1. That is, if the loop gain has frequency dependency, Q does not rise even if the resistance ratio n is increased at a low gain frequency, and the loop gain sometimes oscillates at a gain higher than 1 at a high gain. Therefore, when the amplitude fluctuation is large, the resistance ratio n can not be set to a too large value in order to prevent such oscillation, and the Q value of 1 is also reduced.

On the other hand, according to the resonance circuit 1 shown in Fig. 2, even if the resistance ratio n is set to be large, the tuning output of the resonance circuit 1 does not cause amplitude fluctuation, so that the resistance ratio n can be increased and the Q value can be increased.

Then, a signal attenuated through the voltage dividing circuit 160 is used as a feedback signal, and at the same time, the signal before input to the voltage dividing circuit 160 is subtracted to the output of the tuning circuit 1, It is possible to perform a predetermined amplification on the received signal.

2, either one of the voltage dividing circuits connected to the output terminals of the operational amplifier 112 or 132 in each of the abnormal circuits included in the inquiry circuit 1 is omitted, or the voltage dividing ratio May be set to one.

For example, the output terminal of the operational amplifier 112 may be directly connected to one end of the resistor 120 by omitting the voltage dividing circuit in the abnormal circuit 110C.

If the gain of the other abnormal circuit 110C is set to be larger than 1 by setting the gain to 1 by omitting the voltage dividing circuit for one of the two or more cascaded cascade-connected cascaded circuits, A tuning operation is performed.

If the amplifying operation is not necessary, the voltage divider circuit 160 at the rear end of the abnormal circuit 130C may be omitted and the output of the abnormal circuit 130C may be directly fed back to the previous stage. Alternatively, the resistance of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value, and the partial pressure ratio may be set to 1.

[C. Detailed Configuration and Operation of Frequency Control Circuit]

Next, the details of the frequency control circuit 2 shown in Fig. 1 will be described. 13 is a circuit diagram showing the configuration of the frequency control circuit 2 and shows the detailed configuration of the phase difference detection circuit 3 and the control voltage generation circuit 4 included in the frequency control circuit 2.

The phase difference detecting circuit 3 shown in Fig. 13 includes a buffer 30 such as a source flow, two voltage comparators 31 and 32, and an EX-OR (Exclusive OR) gate 33.

The inverting input terminals of the two voltage comparators 31 and 32 are grounded. The non-inverting input terminal of the one voltage comparator 31 is connected to a signal output from the control output terminal 196 of the inverting circuit 1 (The output signal of the subsequent abnormal circuit 130C) is input to the non-inverted input terminal of the other voltage comparator 32 from the control output terminal 197 of the inquiry circuit 1 .

Each of the voltage comparators 31 and 32 outputs a square wave signal having a positive or negative voltage level depending on whether the voltage level of the signal inputted to the non-inverting input terminal is higher or lower than 0V. That is, the voltage comparators 31 and 32 output a square wave signal having the same frequency and phase as those output from the control outputs 196 and 197 of the inquiry channel 1, respectively.

The EX-OR gate 33 receives a rectangular wave signal output from each of the voltage comparators 31 and 32. The voltage level of the positive polarity of each square wave signal is set to the logic H and the voltage level of the negative polarity of each square wave signal is set to the logic L, Obtain the exclusive OR of the two inputs.

Therefore, for example, when the phase difference between the two signals output from the two control output terminals 196 and 197 of the inverse lookup circuit 1 is 90, the phase difference of the square wave signals output from the voltage comparators 31 and 32 is 90. From the EX-OR gate 33, a square wave signal having a frequency twice that of these square wave signals and having a duty ratio of 50% is output.

The control voltage generating circuit 4 shown in Fig. 13 includes a low-pass filter including a resistor 40 and a capacitor 41, a variable resistor 42 for generating a predetermined bias voltage, an operational amplifier 44, a resistor 45 and a resistor 46 And an amplifier.

The low-pass filter removes the high-frequency component from the square-wave signal output from the EX-OR gate 33 in accordance with the time constant determined by the resistor 40 and the capacitor 41. Therefore, the output voltage of the low-pass filter gradually rises when the duty ratio of the square wave signal output from the EX-OR gate 33 is larger than 50% (when the relative ratio of the logic H is large), and conversely, And gradually decreases when the duty ratio of the square wave signal is smaller than 50% (when the relative ratio of the logic L is large). The low-pass filter shown in Fig. 13 is inserted into the front end of the amplifier, but may be integrally formed with the amplifier by connecting a capacitor in parallel with the feedback resistor of the amplifier.

A resistor 45 is connected between the output terminal and the inverting input terminal of the operational amplifier 44, and the inverting input terminal is grounded through the resistor 46. [ With this connection, the operational amplifier 44 functions as an amplifier having an amplification degree corresponding to the resistance ratio of the resistors 45 and 46. The voltage amplified by the operational amplifier 44 is added to a predetermined bias voltage as described below and input to the lookup circuit 1 after the control voltage is generated.

To the inverting input terminal of the operational amplifier 44, the two fixed terminals are connected to the fixed terminal Vdd and the movable terminal of the variable resistor 42 connected to the sub power source Vss through the resistor 43. [ Therefore, the voltage at the output terminal of the operational amplifier 44 is set to a predetermined bias voltage by the bias circuit including the variable resistor. When the variable resistor 42 is actually formed on a semiconductor substrate, it can be formed using an active element such as a FET.

When the tuning frequency of 1 and the frequency of the input signal coincide with each other (that is, when there is no error), the bias circuit outputs the variable resistor 116 included in one of the abnormal circuits 110C and the other Is set to set the voltage applied to each gate of the variable resistor 136 included in the circuit 130C.

When the variable resistors 116 and 136 are formed using FETs, even if the same gate voltage is applied to each FET, the resistance values do not become equal if the source potentials of the FETs are different. Therefore, when actually combining circuits, it is necessary to connect the divider 5, which generates two types of gate voltages that can be changed in synchronization with each other in accordance with the output voltage of the control voltage generating circuit 4, to the control voltage generating circuit 4 desirable. Alternatively, the FETs may be selected so that the resistance values become the same when the same gate voltage is applied. By performing such sorting, the distributor 5 shown in FIG. 13 can be omitted.

The frequency control circuit 2 of the present embodiment has such a detailed configuration, and the detailed operation will be described in some cases.

[C-1. When the tuning frequency is higher than the frequency of the input signal]

14 is a timing chart in the case where the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal inputted to the inquiry furnace 1, and the input / output timings of the respective constituents in the frequency control circuit 2 are displayed. The diagrams (A) to (F) correspond to the symbols A to F shown in the circuit diagram of FIG.

When the tuning frequency is higher than the frequency of the input signal of the inquiry circuit 1, the phase shift amount phi 2 of the posteriori circuit 130C becomes smaller than 90. As shown in Fig. 11, 196 and 197 have the same phase relationship as the control output 1 shown in Fig. 14 (A) and the control output 2 shown in Fig. 14 (B), respectively.

One of the voltage comparators 31 in the phase difference detecting circuit 3 outputs a signal of H level when the voltage level of the control output 1 is higher than 0 V. [ Therefore, as shown in Fig. 14 (C), the voltage comparator 31 outputs a signal having the same frequency and phase as the control output 1, that is, the H level when the voltage level of the control output 1 is positive, And outputs a rectangular wave signal having an L level when the voltage level of the output 1 is negative.

Similarly, the other voltage comparator 32 in the phase difference detecting circuit 3 outputs a signal of H level when the voltage level of the control output 2 described above is higher than 0 V. Therefore, as shown in Fig. 14 (D), the voltage comparator 32 outputs a signal having the same frequency and phase as the control output 2, that is, H level when the voltage level of the control output 2 is positive, 2 is at the negative polarity, a square wave signal having an L level is output.

The EX-OR gate 33 outputs a square wave signal which becomes H level when the respective outputs of the two voltage comparators 31 and 32 are different in logic, and becomes L level when the outputs of the two voltage comparators 31 and 32 are the same. When the tuning frequency is higher than the frequency of the input signal of the inquiry circuit 1, the phase shift amount phi 2 of the posteriori circuit 130C is smaller than 90. Therefore, as shown in Fig. 14 (E) Signal is output.

The square wave signal output from the EX-OR gate 33 is input to the non-inverting input terminal of the operational amplifier 44 through the low-pass filter formed of the resistor 40 and the capacitor 41 in the control voltage generating circuit 4. This low-pass filter is used to remove a high-frequency component from an input square-wave signal. When the duty ratio of the input square-wave signal is smaller than 50%, the output voltage of the low- 0 < / RTI >

The output voltage of the low-pass filter is amplified to a predetermined amplification degree by an amplifier including the operational amplifier 44, and a predetermined bias voltage set by the variable resistor 42 is added. By applying the added voltage to the distributor 5, the respective control voltages applied to the control input terminals 194 and 195 of the inquiry circuit 1 are generated. Therefore, when the duty ratio of the square wave signal output from the EX-OR gate 33 is smaller than 50%, these control voltages also change to lower values.

Thus, even if the control voltage fed back to the inquiry line 1 becomes low, the tuning frequency of the tuning circuit 1 is changed to the low side. This control is repeated until the frequency of the input signal of 1 and the tuning frequency disappear, and the tuning frequency coincides with the frequency of the input signal after a predetermined time elapses.

[C-2. When the tuned frequency is lower than the frequency of the input signal]

15 is a timing chart when the tuning frequency of the tuning circuit 1 is lower than the frequency of the signal inputted to the inquiry furnace 1, and the input / output timings of the respective constituents in the frequency control circuit 2 are displayed. As in Fig. 14, Figs. 15A to 15F correspond to the symbols A to F shown in the circuit diagram of Fig.

If the tuned frequency is lower than the frequency of the input signal of the inquiry circuit 1, the phase shift amount PHI 2 of the posteriori circuit 130C becomes larger than 90. As shown in Fig. 12, since the two control outputs Observing the two signals output from the terminals 196 and 197 has the same phase relationship as the control output 1 shown in Fig. 15 (A) and the control output 2 shown in Fig. 15 (B).

As described above, the voltage comparator 31 in the phase difference detecting circuit 3 outputs a square wave signal having the H level when the voltage level of the control output 1 is higher than 0 V (Fig. 15 (C)), (FIG. 15 (D)) when the voltage level of the voltage level of 2 is higher than 0 V (FIG. 15 (D)).

The EX-OR gate 33 outputs a square wave signal having a high level when the outputs of the two voltage comparators 31 and 32 are different from each other and a low level when the outputs are equal. Therefore, when the tuning frequency is lower than the frequency of the input signal of the inquiry circuit 1, the phase shift amount PHI 2 of the post-stage abnormal circuit 130C is larger than 90. Therefore, the EX-OR gate 33 The duty ratio of the rectangular wave signal to be output becomes larger than 50%.

Therefore, the output voltage of the low-pass filter in the control voltage generating circuit 4 becomes higher than 0 V as shown in Fig. 15 (F). Accordingly, the control voltage generated from the control voltage generating circuit 4 through the distributor 5 Also changes to higher.

Thus, the control voltage fed back to the inquiry line 1 becomes high, and the tuning frequency of the tuning circuit 1 is changed to the high side. This control is repeated until the frequency of the input signal of 1 and the tuning frequency disappear, and the tuning frequency coincides with the frequency of the input signal after a predetermined time elapses.

As described above, according to the tuning mechanism of this embodiment, since the phase difference between the input / output signals of one abnormal circuit 130C of the tuning circuit 1 is controlled to be 90., the tuning frequency always changes following the frequency of the input signal, It must match. Therefore, when the tuning mechanism of this embodiment is applied to, for example, a superheterodyne type receiver, the tuning frequency can be easily matched to the frequency of a carrier wave such as an input broadcast wave.

The tuning circuit 1 and the tuning frequency control circuit 2 included in the tuning mechanism of the present embodiment are constituted by a voltage comparator, a gate or an operational amplifier, a capacitor, a resistor, etc., and any element can be formed on a semiconductor substrate So that the entire tuning mechanism, or the entire tuner including the tuner and its peripheral devices, can be integrated on the semiconductor substrate.

In particular, when the entire tuning mechanism is integrated, it is considered that a large unbalance occurs in the circuit constants for each of the manufactured chips and the frequency characteristics do not coincide. However, even in such a case, according to the tuning mechanism of this embodiment, Since the tuning frequency of the tuning circuit 1 changes according to the signal, even if the characteristics of the circuit elements are unbalanced, stable tuning characteristics can always be obtained without affecting the actual tuning characteristics.

In the case where the entire tuning mechanism is integrated, it is conceivable that various element constants such as resistors change depending on the temperature change during use. In the tuning control system of this embodiment, however, control is always performed so as to coincide with the frequency of the input signal Even when various element constants are changed, appropriate feedback is applied so that either the frequency of the input signal or the tuning frequency is lost.

[D. Other examples of frequency control circuit]

Next, another configuration example of the frequency control circuit 2 shown in Fig. 1 will be described. The phase difference detecting circuit 3 in the frequency control circuit 2 having the detailed configuration shown in Fig. 13 is configured by using the EX-OR gate 33, but other elements may be used.

FIG. 16 is a detailed circuit diagram showing another example of the configuration of the frequency control circuit, and has a configuration in which the phase difference detecting circuit 3 shown in FIG. 13 is replaced by a phase difference detecting circuit 3A.

The phase difference detecting circuit 3A shown in Fig. 16 includes a buffer 30, two voltage comparators 31 and 32, and a tri-state buffer 34 whose operation is controlled in accordance with the output of one voltage comparator 31. [ The phase difference detection circuit 3A has a configuration in which the EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced with a tri-state buffer 34 and the connection of two input terminals of one voltage comparator 32 is changed. The tristate buffer 34 may be replaced with an analog switch.

17 is a timing chart in the case where the tuning frequency is higher than the frequency of the signal inputted to the tuning circuit 1 shown in Fig. 16, and the phase difference detecting circuit 3A and the control voltage generating circuit 4 constituting the frequency controlling circuit The input / output timing in the configuration is displayed. 17A to 17F correspond to the symbols A to F shown in the circuit diagram of Fig.

The timings shown in Figs. 17A to 17C are the same as the timings shown in Figs. 14A to 14C. In the following description, mainly the operation of the tri-state buffer 34 will be described.

As described above, the output signal of one voltage comparator 31 is input to the control terminal of the tri-state buffer 34. The tri-state buffer 34 passes or blocks the output of the voltage comparator 32 in accordance with the voltage level of the control terminal. For example, when the output signal of the voltage comparator 31 is at the H level, the signal outputted from the other voltage comparator 32 is directly passed. On the other hand, when the output of the voltage comparator 31 is at the L level, the signal is in the high impedance state.

However, when the tri-state buffer 34 functions as a buffer when the tuning frequency is higher than the frequency of the input signal of 1, that is, when the output of one voltage comparator 31 is at the H level, the output of the other voltage comparator 32 The period of the L level becomes longer than the period of the H level.

17 (E), when the output of the voltage comparator 31 is at the L level, the output from the tristate buffer 34 becomes 0 V, and when the output of the voltage comparator 31 is at the H level, A signal which becomes H level is outputted.

When the tuning frequency is higher than the frequency of the input signal, the output of the tri-state buffer 34 is longer in the L level than in the H level. Therefore, the output of the tri- As shown in Fig. 17 (F), becomes lower than 0 V, so that the control voltage fed back to the tuning circuit 1 also changes to a lower value.

Since the output of the tri-state buffer 34 is always 0 V in one half of one cycle, as shown in Fig. 13, the detection strength is lower and the response speed of the control is slower than in the case of using the EX-OR gate 33 .

18 is a timing chart in the case where the tuning frequency is lower than the frequency of the signal inputted to the tuning circuit 1 shown in Fig. 16, and the phase difference detecting circuit 3A and the control voltage generating circuit 4 constituting the frequency controlling circuit Output timing in each configuration is displayed. 18 (A) to (F) correspond to the symbols A to F shown in the circuit diagram of Fig.

In the case where the tuning frequency is lower than the frequency of the input signal of 1, the output level of the tri-state buffer 34 becomes different from the above case when the output of the voltage comparator 31 is at the H level. That is, when the output of the voltage comparator 31 is at H level, the output of the tri-state buffer 34 becomes longer in the H level period than in the L level period. When the output of the voltage comparator 31 is at the L level, the output of the tri-state buffer 34 is always 0V.

When the tuning frequency is lower than the frequency of the input signal, the output of the tri-state buffer 34 becomes longer in the H level period than the L level period. Therefore, the resistance 40 in the control voltage generating circuit 4, The output voltage of the filter becomes higher than 0 V as shown in Fig. 18 (F), and accordingly the voltage circuit fed back to the tuning circuit 1 also changes to higher.

Thus, when the tuning frequency is higher than the frequency of the input signal of the tuning circuit 1, the feedback control voltage is lowered to change the tuning frequency to a lower value. On the contrary, when the tuning frequency is lower, the feedback control voltage becomes higher, The control is performed so that the tuning frequency always coincides with the frequency of the input signal.

[E. FM receiver]

Next, the case where the tuning mechanism of the present embodiment described above is applied to an FM receiver will be described. The frequency control circuit 2 shown in Fig. 1 changes the control voltage for changing the frequency of the input signal of the inquiry circuit 1 to follow the frequency change and converting the control voltage fed back to the inquiry circuit 1. Therefore, in principle, this control voltage includes the same frequency component as the modulated signal of the FM wave when the frequency change of the input signal of the inquiry circuit 1, that is, the FM wave as the input signal is considered. In this embodiment, And extracts the frequency component as an FM detection signal.

Fig. 19 is a diagram showing a configuration of a tuning mechanism that also serves as FM detection. Fig. 1, the control voltage generating circuit 4 in the frequency control circuit 2 shown in FIG. 1 is replaced with a control voltage generating circuit 4A, and in parallel with the control voltage fed back from the control voltage generating circuit 4A The FM detection signal is being extracted.

20 is a circuit diagram showing the detailed configuration of the frequency control circuit 2 shown in Fig. The detailed configuration of the phase difference detecting circuit 3 constituting the frequency control circuit 2 is the same as that shown in Fig. 13, and the configuration of the control voltage generating circuit 4A is slightly different from that of the control voltage generating circuit 4 shown in Fig.

The control voltage generating circuit 4A includes a low-pass filter composed of a resistor 40 and a capacitor 41, an operational amplifier 44, and an amplifier composed of resistors 45 and 46, The bias voltage of the control voltage applied to the inversion circuit 1 from the circuit 4A can be arbitrarily changed is the same as the control voltage generating circuit 4 shown in Fig.

The control voltage generating circuit 4A has the same configuration as that of the control voltage generating circuit shown in Fig. 13, and further includes a second low-pass filter composed of a resistor 47 and a capacitor 48 and an operational amplifier 49, 50 and 51 And a second amplifier configured.

The first low-pass filter composed of the resistor 40 and the capacitor 41 is provided to remove the high-frequency component from the rectangular wave signal outputted from the phase difference detecting circuit 3. From the first low-pass filter, a signal whose DC voltage level varies flatly is output by the duty ratio of the rectangular wave signal described above.

On the other hand, the second low-pass filter constituted by the resistor 47 and the capacitor 48 is provided to remove a high frequency component of about 20 kHz or more from the rectangular wave signal outputted from the phase difference detecting circuit 3. From this second low-pass filter, an FM modulated signal such as FM voice is output as an FM detection signal. The FM detection signal is amplified by an amplifier constituted by an operational amplifier 49 and is taken out of the control voltage generating circuit 4A.

FIG. 21 is a diagram showing a configuration of an FM receiver using the tuning mechanism shown in FIG. 19;

The FM receiver shown in Fig. 21 includes the tuning circuit 1 shown in Figs. 19 and 20, a frequency control circuit 2, a high-frequency amplifying circuit 10, a low-frequency amplifying circuit 12, a speaker 14 and an antenna 16.

The high-frequency amplifying circuit 10 high-frequency amplifies the FM wave received by the antenna 16, and inputs the amplified FM wave to the antenna 1. As described above, the tuning circuit 1 performs control for matching the tuning frequency with the frequency of the FM wave inputted in accordance with the control voltage from the frequency control circuit 2. [

The low-frequency amplifying circuit 12 performs low-frequency amplification on the FM detection signal output from the control voltage generating circuit 4A in the frequency control circuit 2 and outputs a voice from the speaker 14. Further, instead of using the speaker 14, the sound may be converted into sound by an earphone or the like.

The FM receiver shown in Fig. 21 extracts the FM wave of the desired frequency directly from the antenna 1 without using the bar code and the LC circuit by the bar-antenna at the input portion from the antenna 16, Can be easily designed. Therefore, the antenna 16 can be formed of a short rod-like or rod-shaped conductive material, and the FM wave can be efficiently received. Specifically, by forming the antenna 16 by a lot antenna used in a car radio or the like, or simply by using the lead portion of the earphone as the antenna 16, it is possible to receive a desired FM wave with high sensitivity, have.

Almost all the constituent circuits of the FM receiver including the tuner 1, the frequency control circuit 2, and the high-frequency amplifier circuit 10 can be integrated on the semiconductor substrate, and the configuration circuit can be integrated on one chip .

Thus, by adjusting the time constant of the low-pass filter included in the control voltage generating circuit 4A, only the FM modulated signal can be easily extracted from the FM modulated signal input to the inquiry circuit 1, and the tuning mechanism shown in Fig. In the case where the present invention is applied to a receiver, an FM detection circuit separately provided at the rear end of the tuning mechanism is unnecessary, thereby simplifying the circuit configuration.

In the conventional FM receiver, the limiter circuit is set by performing the FM detection after eliminating the influence of the amplitude variation between the tuning mechanism and the FM detection circuit. However, in the tuning mechanism shown in Fig. 20, Since the signal is converted into the square wave signal by the comparator, there is no influence on the amplitude fluctuation, and the limiter circuit which is conventionally required is not required.

19 and 20 illustrate the case of extracting the FM detection signal from the control voltage generating circuit 4A in the frequency control circuit 2, it is needless to say that the limiter circuit and various kinds of An FM detection circuit using a detection method may be connected to obtain an FM detection signal.

[F. AM receiver]

Next, the case where the tuning mechanism of the present embodiment described above is applied to an AM receiver will be described. In the tuning circuit 1 according to the present embodiment, 360 phase shifts are performed in total by two or more circuits 110C and 130C at the time of tuning. Therefore, by performing synchronous rectification with respect to the input signal by using the output signal of the reference signal 1 as a reference signal, only the frequency components that are the same as the tuning frequency among the various frequency components included in the input signal are extracted, Can be used.

22 is a diagram showing a configuration of a tuning mechanism that uses AM detection by synchronous rectification in combination. The tuning mechanism shown in the figure includes a synchronous rectification circuit 6 and a low-pass filter (LPF) 6 connected to the subsequent stage in addition to the tuning circuit 1 and the frequency control circuit 2 shown in Fig.

Generally, the operation of switching the input signal in synchronization with a certain reference signal is equivalent to mixing the reference signal and the input signal. Considering the first and second signals whose frequencies are close to each other as input signals, the frequency of the first signal is denoted by f1 and the frequency of the second signal is denoted by f2 (= f1 + DELTA f). The frequency of the reference signal is fr.

If synchronous rectification of the input signal is performed by using such a reference signal, it corresponds to multiplying each signal that can be expressed by a triangular function, so that the sum of the frequencies f1 and f2 of the input signal and fr of the reference signal and The components of the tea are generated. Therefore, by multiplying the first signal in the input signal by the reference signal, the respective frequency components of f1 + fr and f1-fr appear, and by multiplying the second signal in the input signal by the reference signal, f1 + DELTA f + fr and f1 + DELTA f- Each frequency component appears.

Now, when fr = f1, the frequency components of 2f1 and 0 appear by multiplying the first signal by the reference signal, and the frequency components of 2f + DELTA f and DELTA f appear by multiplying the second signal by the reference signal. Therefore, the frequency components of 2f + DELTA f, 2f1, DELTA f, and 0 appear as the synchronous rectified output. Here, the component of frequency 0 is a direct current component. Actually, the direct current component includes a modulating signal. Therefore, this direct current component and the other alternating current components (2f + Δf, 2f1, Δf) are separated to extract only the direct current component The detection using the synchronous rectification and the tuning separation can be performed at the same time.

In the case of domestic AM broadcasting, since Δf described above is 9 kHz, only the desired broadcast wave having the same frequency as the reference signal can be extracted by using the low-pass filter 7 capable of removing the frequency component of 9 kHz or more.

Fig. 23 is a diagram showing the detailed configuration of the synchronous rectification circuit 6 shown in Fig. 22; The synchronous rectification circuit 6 shown in the diagram has a voltage comparator 60 and an analog switch (AS) 61.

In this voltage comparator 60, the inverting input terminal is grounded, and the output signal of the inverting input terminal 1 is input to the non-inverting input terminal. Therefore, the voltage comparator 60 outputs a square wave signal having a predetermined constant voltage when the output signal of the inquiry circuit 1 is at a voltage level higher than 0 V, and a predetermined negative voltage when the output signal is at a voltage level lower than 0 V, on the contrary.

The analog switch 61 changes the switch state according to the voltage level of the square wave signal output from the voltage comparator 60. That is, when the rectangular wave signal outputted from the voltage comparator 60 has a predetermined constant voltage, the input signal of the tuning circuit 1 is passed and the input signal of the tuning circuit 1 is cut off when the rectangular wave signal is a predetermined negative voltage. The output of the analog switch 61 is input to the low-pass filter 7, and the low-pass filter 7 extracts only a frequency component equal to the tuning frequency, thereby obtaining an AM detection signal.

As described above using the detailed configuration shown in Fig. 2, the reference signal 1 used in the present embodiment has theoretically no attenuation of signal amplification, and an output signal of constant amplification can always be obtained even when the tuning frequency changes . However, when simulation is actually carried out in the same circuit 1, there is a case where the output amplification changes slightly due to the change of the tuning frequency, or the output signal is stressed due to the kind of the FETs constituting the variable resistors 116 and 136, . However, as shown in FIG. 22, by performing synchronous rectification on the input signal of the inquiry circuit 1, there is no influence on the AM detection signal due to fluctuation in amplitude or generation of stress due to the operation of the tuning circuit 1, The AM detection signal can be extracted.

In addition, when the synchronous rectified output is used for AM detection, there is no dead band region equal to or less than the forward voltage as in the case of performing AM detection using a diode, for example, and AM reception with good linearity is possible. In particular, when a tuning mechanism including an AM detection circuit is integrated on a semiconductor substrate, a germanium diode having a low forward voltage can not be used and a silicon diode having a high forward voltage is used. Therefore, . Therefore, the tuning mechanism shown in Fig. 22 is particularly effective when integrated.

22, the synchronous rectification is performed with respect to the input signal of the inquiry channel 1. However, as in the conventional receiver, an AM detection circuit using synchronous rectification is connected to the rear end of the inquiry circuit 1, An AM detection signal may be obtained by connecting an AM detection circuit using a detection method of the other to the rear end of the reference signal line 1.

Fig. 24 is a diagram showing the configuration of an AM receiver using the tuning mechanism shown in Fig. 22. Fig.

The AM receiver shown in Fig. 24 includes a high-frequency amplifying circuit 10, a low-pass filter 7, a low-frequency amplifying circuit 12, a speaker 14, and an antenna 16.

The AM wave received by the antenna 16 is high-frequency amplified by the high-frequency amplifying circuit 10, and then inputted to the lookup furnace 1. The tuning frequency of the tuning circuit 1 is controlled by the frequency control circuit 2. Synchronous rectification is performed using the signal outputted from the tuning circuit 1 at this time and the AM detection signal is outputted from the low pass filter 7. [ The AM detection signal is amplified by the low-frequency amplifying circuit 12 and then output from the speaker 14. [

[First Modification of Tuning Circuit]

Although each of the ideal circuits 110C and 130C included in the tuning mechanism shown in FIG. 2 includes a CR circuit, it is also possible to use an ideal circuit in which the CR circuit is replaced by an LR circuit constituted by a resistor and an inductor, .

Fig. 25 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit. Fig. 25 shows a configuration that can be replaced with the abnormal circuit 110C in the preceding stage of the circuit 1 shown in Fig. The abnormal circuit 110L shown in the diagram has a configuration in which the capacitor 114 in the abnormal circuit 110C shown in Fig. 3 and the CR circuit made of the variable resistor 116 are replaced by an LR circuit composed of the variable resistor 116 and the inductor 117. [

Therefore, as shown in the vector diagram of Fig. 26, the relationship of the input / output voltage and the like of the abnormal circuit 110L shown in Fig. 25 is obtained by adding the voltage VC1 shown in Fig. 4 to the voltage VR1 across the variable resistor 116 and the voltage VR1 May be replaced with the voltage VL1 across the inductor 117, respectively.

When the inductance of the inductor 117 is L and the resistance of the variable resistor 116 is R, the phase shift amount? 3 of the anomalous circuit 110L is determined by the LR circuit formed by the inductor 117 and the variable resistor 116, R), it becomes the same as? 1 shown in the above-mentioned expression (6).

Fig. 27 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 130C at the rear stage of the circuit 1 shown in Fig. The abnormal circuit 130L shown in the diagram has a configuration in which the CR circuit constituted by the variable resistor 136 and the capacitor 134 in the abnormal circuit 130C shown in Fig. 5 is replaced with an LR circuit composed of the inductor 137 and the variable resistor 136. [

Therefore, as shown in the vector diagram of Fig. 28, the relationship of the input / output voltage and the like of the abnormal circuit 130L shown in Fig. 27 is obtained by adding the voltage VC2 shown in Fig. 6 to the voltage VR2 across the variable resistor 136 and the voltage VR2 May be replaced with the both-end voltage VL2 of the inductor 137, respectively.

The phase shift amount phi 4 of the anomalous circuit 130L is set so that the time constant of the LR circuit constituted by the variable resistor 136 and the inductor 137 is T2 (the resistance value of the variable resistor 136 is R, and the inductance of the inductor 137 is L, / R), it becomes the same as? 2 shown in the above-mentioned formula (7).

As described above, each of the abnormal circuit 110L shown in Fig. 25 and the abnormal circuit 130L shown in Fig. 27 is equivalent to the abnormal circuits 110C and 130C shown in Fig. 3 or Fig. 5. In the circuit 1 shown in Fig. 2 It is possible to replace the abnormal circuit 110C at the previous stage with the abnormal circuit 110L shown in Fig. 25 and replace the abnormal circuit 130C at the subsequent stage with the abnormal circuit 130L shown in Fig. 27, respectively. The tuning frequency of the tuning circuit including the above-mentioned circuits 110L and 130L is proportional to the reciprocal R / L of the time constant of the LR circuit in each of the abnormal circuits 110L and 130L, for example, the dual inductance L can be easily reduced Therefore, by integrating all of the tuning circuits constituted by the two abnormal circuits 110L and 130L, it becomes easy to increase the frequency of the tuning frequency.

When the abnormal circuits 110C and 130C shown in Fig. 2 are replaced with the abnormal circuit 110L shown in Fig. 25 and the abnormal circuit 130L shown in Fig. 27, respectively, the gate voltages of the FETs forming the variable resistors 116 and 136 are changed The EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced with an EX-NOR (exclusive NOR) gate because the direction of the change in the phase shift amount in the case of FIG. It is necessary to reverse the direction of the change of the control voltage by changing the input of either one of the voltage comparators 31 and 32 or the like.

When the abnormal circuits 110C and 130C in the circuit 1 shown in Fig. 2 are replaced with the abnormal circuits 110L and 130L, the voltage of the one of the voltage dividing circuits connected to the output terminals of the operational amplifier 112 or 132 in each abnormal circuit The voltage dividing circuit may be omitted. Alternatively, it is possible to omit both voltage dividing circuits and to adjust the resistance ratio of the resistors 118 and 120 and the resistance ratio of the resistors 138 and 140 so as to compensate the loss occurring in the feedback loop of the reference circuit 1.

When the amplifying operation is unnecessary, the voltage divider circuit 160 at the rear end of the abnormal circuit at the rear end may be omitted and the output of the abnormal circuit at the rear end may be directly fed back to the front end. Or the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value and the division ratio may be set to 1.

[Second Modification of Tuning Circuit]

29 is a circuit diagram showing a second modification of the tuning circuit; 1A shows two abnormal circuits 210C and 230C, a feedback resistor 170, and an input resistor 174 (refer to FIG. 1B) for performing a 360. phase in total at a predetermined frequency by shifting the phases of AC signals inputted thereto by a predetermined amount (Feedback signal) and the signal (input signal) input to the input terminal 190 to the posteriori abnormality circuit 230C through each of the input terminals of the feedback resistor 170 and the input resistor 174 And the adder circuit is added to the adder circuit.

2, by setting the resistance values of the resistor 118 and the resistor 120 in the anterior error circuit 110C to be the same, it is possible to suppress the amplitude change when the frequency of the input AC signal is changed, The gain of the abnormal circuit 110C is set to a value larger than 1 by connecting a voltage dividing circuit composed of the resistors 121 and 123 to the output side. In contrast, the abnormal circuit 210C in the preceding stage included in the circuit 1A shown in Fig. 29 is not provided with the voltage dividing circuit in the abnormal circuit, and the resistance value of the resistor 120 'is set larger than the resistance value of the resistor 118' Is set to a value greater than one.

The same holds for the abnormal circuit 230C at the subsequent stage. The gain of the abnormal circuit 230C is set to a value larger than 1 by setting the resistance value of the resistor 140 'to be larger than the resistance value of the resistor 138'. A feedback resistor 170, an output terminal 192, and a resistor 178 are connected to the output terminal of the abnormal circuit 230C.

29, the output of the rear-stage abnormal circuit 230C is directly fed back, but the voltage-dividing circuit at the rear end of the rear-stage abnormal circuit 230C is connected to feed back the divided output through the feedback resistor 170 .

Incidentally, when the resistance values are set as described above and the gain of the abnormal circuit is set to a value larger than 1, a gain variation occurs depending on the frequency of the input signal. For example, if the frequency of the input signal is low, the ideal circuit 210C becomes a voltage-phase flow circuit. If the frequency is high, the ideal circuit 210C The gain at this time becomes -m times (m is the resistance ratio of the resistor 120 'and the resistor 180'). When the frequency of the input signal changes, the gain of the error circuit 210C also changes, Lt; / RTI >

Such amplitude fluctuation can be suppressed by connecting a resistor 119 to the inverting input terminal of the operational amplifier 112 and matching the gain when the frequency of the input signal is low and when the frequency is high. Specifically, when the resistance value of the resistor 118 'is r and the resistance value of the resistor 120' is mr, the resistance value of the resistor 119 is set to mr / (m-1) Each gain can be matched. Likewise, by connecting the resistor 139 having a predetermined resistance value to the inverting input terminal of the operational amplifier 132, the amplitude fluctuation of the output signal can be suppressed. Further, one end of the resistor 119 and the resistor 139 may be connected to a fixed potential other than the ground level.

[Third Modification of Tuning Circuit]

Although the example in which the CR circuit is included in the abnormal circuits 210C and 230C in the inquiry furnace 1A shown in Fig. 29 has been described, the same abnormal circuit can be configured even when the LR circuit is included in place of the CR circuit.

30 is a circuit diagram showing the configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 210C in the preceding stage of the circuit 1A shown in Fig. The abnormal circuit 210L shown in the diagram has a configuration in which the capacitor 114 in the preceding-stage abnormal circuit 210C shown in Fig. 29 and the CR circuit constituted by the variable resistor 116 are replaced by the LR circuit constituted by the variable resistor 116 and the inductor 117.

On the other hand, Fig. 31 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 230C at the rear stage of the circuit 1A shown in Fig. The abnormal circuit 230L shown in the diagram has a configuration in which the CR circuit constituted by the variable resistor 136 and the capacitor 134 in the rear stage abnormal circuit 230C shown in Fig. 29 is replaced by an LR circuit composed of the inductor 137 and the variable resistor 136. [

The abnormality circuit 210L shown in Fig. 30 is equivalent to the abnormality circuit 210C at the previous stage shown in Fig. 29, and the abnormality circuit 210C at the previous stage of the inquiry circuit 1A shown in Fig. 29 is replaced with the abnormality circuit 210L shown in Fig. It is possible. Similarly, the abnormal circuit 230L shown in FIG. 31 is equivalent to the abnormal circuit 230C shown in FIG. 29, and is replaced with the abnormal circuit 230L shown in FIG. 31, This is possible.

When the two abnormal circuits 210C and 230C are replaced with the abnormal circuits 210L and 230L, the tuning frequency can be easily increased by integrating the entire tuning circuits.

When the abnormal circuits 210C and 230C shown in FIG. 29 are replaced with the abnormal circuit 210L shown in FIG. 30 and the abnormal circuit 230L shown in FIG. 31, respectively, the gate voltages of the FETs forming the variable resistors 116 and 136 are changed The EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced with the EX-NOR (exclusive NOR) gate because the directions of the changes in the phase shift amounts are opposite to each other It is necessary to reverse the direction of the change of the control voltage by changing the input of either one of the voltage comparators 31 and 32. [

29, the amplitude fluctuation when the tuning frequency is varied is prevented by connecting the resistors 119 and 139 to the two abnormal circuits 210C and 230C, respectively. However, when the variable range of the frequency is narrow It is also possible to construct the tuning circuit by removing the above-described resistors 119 and 139 because the amplitude fluctuation is small. Alternatively, the tuning circuit may be constituted by removing only one resistor 119 or 139.

[Fourth Modification of Tuning Circuit]

In the above-described circuits 1 and 1A, the loss of the loop gain of the feedback circuit made up of the feedback circuit 170 and the all-pass circuit including two abnormal circuits 110C and the like is caused by the input impedance of the preceding- In order to suppress the occurrence of the loss due to the input impedance, a flow circuit of the transistor is inserted before the preceding stage anomaly circuit 110C or the like and a signal to be fed back is sent through this flow circuit to the preceding stage anomaly circuit 110L, etc.).

32 is a circuit diagram showing an example of a tuning circuit including a flow circuit therein. 1B is different from the circuit 1 shown in Fig. 2 in that a flow circuit 150 of a transistor is inserted in the front end side of the preceding-stage abnormal circuit 110C. The flow circuit 150 shown in Fig. 32 is constituted by a so-called source flow circuit, but it may be constituted by a limiter flow circuit. In FIG. 32, the voltage division ratio of the voltage dividing circuit 160 may be set to 1, or the voltage dividing circuit 160 itself may be omitted so that only the tuning operation is performed without performing the amplifying operation as a whole.

When the flow circuit 150 of the transistor is cascade-connected to the front end side of the preceding-stage abnormal circuit 110C or the like, the resistance value of the feedback resistor 170 and the input resistor 174 can be increased as compared with the circuit of FIG. Particularly, in the case where the whole of the semiconductor integrated circuit is integrated with the semiconductor integrated circuit, it is preferable to increase the occupied area of the device in order to reduce the resistance value of the feedback resistor 170 and the like. Therefore, in the case of integration, it is effective to connect the flow circuit 50 shown in Fig. 32 in particular.

[Modified example 5 of the tuning circuit]

2, the phase shift amount by which the two abnormal circuits 110C and 130C are combined is 360. However, a non-inverting circuit that does not shift the phases is connected to the abnormal circuits 110C and 130C connected in cascade, .

33 is a circuit diagram showing a configuration of a 1C circuit which is obtained by connecting a non-inverting circuit 350 to two preceding circuits. As shown in the diagram, the inquiry circuit 1C includes the abnormal circuit 130C having the configuration in which the resistors 121 and 123 are omitted from the abnormal circuit 110C shown in Fig. 3, and the resistors 141 and 143 from the abnormal circuit 130C shown in Fig. An abnormal circuit 330C having an omitted configuration, a non-inverting circuit 350 connected to the previous stage of the abnormal circuit 310C, a voltage dividing circuit 160 composed of resistors 162 and 164, and an adding circuit composed of a feedback resistor 170 and an input resistor 174.

The abnormal circuits 310C and 330C shown in Fig. 33 have the same configuration as the abnormal circuits 110C and 130C shown in Fig. 3 except that no voltage divider circuit is connected to the output terminals of the operational amplifier 112 or 132, And the phase shift amount are the same as those of the abnormal circuits 110C and 130C. However, a ₁ = 1 in equation (2) and a ₂ = 1 in equation (3).

The non-inverting circuit 350 is constituted by an operational amplifier 352 whose inverting input terminal to which the AC signal of the non-inverting input terminal is inputted is grounded via the resistor 354 and a resistor 356 connected between the inverting input terminal and the output terminal of the operational amplifier 352 . The operational amplifier 352 requires a predetermined amplification degree determined by the resistance ratio of the two resistors 354 and 356.

The abnormal circuit 310C has a gain of 1 because the resistance values of the resistors 118 and 120 are the same. Likewise, in the abnormal circuit 330C, since the resistance values of the resistors 138 and 140 are the same, the gain becomes 1. Therefore, in the above-described circuit 1C, the gain of the above-described non-inverting circuit 350 is set to a value larger than 1 instead of making a gain in each of the above-mentioned abnormal circuits.

The non-inverting circuit 350 having such a configuration outputs without changing the phase of the input circuit. By adjusting the gain, it becomes easy to compensate for the attenuation of signal amplification by the voltage dividing circuit 160 and the loss occurring in the feedback loop. The non-inverting circuit 350 also functions as a buffer connected to the previous stage of the preceding-stage abnormal circuit 310C as in the case of the flow circuit by the transistor described above.

Incidentally, the non-inverting circuit 350 shown in Fig. 33 may be connected to the preceding stage of the circuit 1 or 1A shown in Fig. 2 or Fig.

[Sixth Modification of Tuning Circuit]

Although the above-described tuning circuits 1, 1A, 1B and 1C perform predetermined tuning operations at a frequency at which the sum of the phase shift amounts by two or more circuits is 360. However, two or more circuits May be combined to constitute a tuning circuit so that a predetermined tuning operation may be performed at a frequency at which the sum of the amounts of phase shift by two or more circuits becomes 180. [

34 is a circuit diagram showing a sixth modification of the tuning circuit, in which an abnormal circuit 310C is connected in place of the abnormal circuit 330C in the subsequent stage of Fig. 33, and a phase inverting circuit 380 is connected in place of the non-inverting circuit 350. [

The phase inversion circuit 380 receives the AC signal inputted through the resistor 384 at the inverting input terminal and simultaneously connects the op-amp 382 grounded with the non-inverting input terminal and the inverting input terminal and the output terminal of the operational amplifier 382 Resistors 386 and 386 are formed. When an AC signal is input to the inverting input terminal of the operational amplifier 382 through the resistor 384, a reversed phase signal whose phase is inverted is output from the output terminal of the operational amplifier 382, and the opposite phase signal is input to the preceding- The phase inversion circuit 380 has a predetermined amplification degree determined by the resistance ratio of the two resistors 384 and 386, and a gain greater than 1 can be obtained by increasing the resistance value of the resistance 386 rather than the resistance value of the resistance 384.

However, as described above, the phase error is shifted 180 ° to 360 ° in the clockwise direction on the basis of the input voltage Ei as the frequency ω of the input signal changes from 0 to ∞ as described above. When the time constant of the CR circuit in the two abnormal circuits 310C is the same (this is referred to as T), the phase shift amount is 270 in each of the two abnormal circuits 310C at the frequency of? = 1 / T. Therefore, the phase is shifted by 270.x 2 = 540. (= 180.) By the two abnormal circuits 310C as a whole, and the phase is inverted by the phase inverting circuit 380 connected to the previous stage of the two abnormal circuits 310C. A signal whose phase shift amount is 360. in this order is output from the posteriori error circuit 310C.

34, the gain of the above-described phase inversion circuit 380 is set to a value larger than 1, and the attenuation of the signal amplitude by the voltage dividing circuit 160 and the attenuation of the feedback loop It is easy to compensate for the loss occurring in the semiconductor device.

[Seventh Modification of Tuning Circuit]

34 shows an example in which the abnormal circuit 310C is cascade-connected, but it is also possible to perform the tuning operation even when the abnormal circuit 330C shown in Fig. 33 is cascade-connected.

35 is a circuit diagram showing a seventh modification of the tuning circuit; 1E is an example in which the abnormal circuit 330C is cascaded instead of the abnormal circuit 310C shown in Fig.

However, as described above, the error circuit 330C shifts the phase of the input signal Ei in the clockwise direction from 0.degree. To 180.degree. As the frequency .omega. Of the input signal changes from 0 to. When the time constant of the CR circuit in the two abnormal circuits 330C is the same (this is referred to as T), the phase shift amount in each of the two abnormal circuits 330C is 90. at the frequency of? = 1 / T. Accordingly, the phase is shifted 180 degrees by the entirety of the two abnormal circuits 330C, and the phase is inverted by the phase inversion circuit 380 connected to the two stages of the abnormal circuits 330C. Is outputted from the abnormal circuit 330C in the subsequent stage.

34, the gain of the above-described phase inversion circuit 330 is set to a value larger than 1, instead of making a gain in each of the above-mentioned circuits. In the above-described circuit 1E, It is easy to compensate for the attenuation of the signal amplification due to the feedback loop and the loss caused by the feedback loop.

Although the circuits 1C, 1D, and 1E shown in Figs. 33 to 35 include two or more circuits including a CR circuit, they may be configured to include an LR circuit. For example, in the circuit 1C shown in Fig. 33, the abnormal circuit 310C in the preceding stage is replaced with the abnormal circuit in which the voltage dividing circuit is omitted from the abnormal circuit 110L shown in Fig. 25, The abnormal circuit 130L may be replaced with an abnormal circuit which omits the voltage dividing circuit.

In the case where only the tuning operation is performed without amplifying the signal amplitude in 1C, 1D, and 1E shown in Figs. 33 to 35, the voltage dividing circuit 160 may be omitted. A voltage dividing circuit may be connected to at least one output terminal of the operational amplifier in the two or more circuits. For example, when the voltage dividing circuit is connected to the output terminal of the operational amplifier 112 in the preceding-stage abnormal circuit 310C and the output terminal of the operational amplifier 132 in the rear-stage abnormal circuit 330C, respectively, in 1C in Fig. 33, Inverting circuit 350 is connected to the preceding stage of the anomaly circuit 110C at the preceding stage in the 1 st stage.

Incidentally, the circuits 1C, 1D, 1E, etc. shown in Figs. 33 to 35 include two or more abnormal circuits, a non-inverting circuit, two abnormal circuits and a phase inverting circuit, The total phase shift amount at a predetermined frequency is set to 360. Thus, a predetermined tuning operation is performed. Therefore, considering only the amount of phase shift, there is some degree of freedom in order to connect the three circuits, and the connection order can be determined as needed.

[Modification 8 of the tuning circuit]

Although any one of the first through seventh modifications of the above-described tuning circuit includes an operational amplifier in the ideal circuit, it is also possible to configure an ideal circuit using a transistor instead of an operational amplifier.

The synchronizing signal line 1F shown in Fig. 36 includes two more circuits 410C and 430C for performing a total 360 占 phase shift at a predetermined frequency by shifting the phases of the AC signals inputted thereto by a predetermined amount, and an output A noninverting circuit 450 amplifying and outputting a signal at a predetermined amplification degree without changing the phase of the signal, a voltage dividing circuit 160 consisting of resistors 162 and 164 provided at the rear end of the noninverting circuit 450, a feedback resistor 170 and an input resistor 174 (Feedback signal) of the voltage divider circuit 160 and a signal (input signal) input to the input terminal 190 at a predetermined ratio through each of the resistors .

The capacitor 172 connected in series with the feedback resistor 170 and the capacitor 176 inserted between the input resistor 174 and the input terminal 190 are intended to block the direct current and this impedance is extremely small at the operating frequency, Capacity.

Fig. 37 shows the configuration of the abnormal stage circuit 410C of the preceding stage shown in Fig. The anomaly circuit 410C of the former stage shown in the diagram is composed of a FET 412 having a gate connected to the input stage 122, a capacitor 414 connected in series to the source / drain of the FET 412, and a variable resistor 416 and a drain And a resistor 420 connected between the source of the FET 412 and the ground. At least one of the FET 412 and the FET 432 described later may be replaced with a high transistor.

Here, the resistance values of the two resistors 418 and 420 connected to the source and the drain of the FET 412 are set to be substantially equal to each other. Considering the AC component of the input voltage applied to the input terminal 122, And a signal whose phase is inverted (phase shifted by 180.) from the source of the FET 412 is outputted from the drain of the FET 412, respectively.

The resistor 426 in the abnormal circuit 410 shown in FIG. 36 is for applying a proper bias voltage to the FET 412. 37, the channel formed in the source / drain of the junction-type FET is used as a resistor, and the resistance value can be arbitrarily changed within a certain range by varying the gate voltage .

When a predetermined AC signal is input to the input terminal 122, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 412 in the ideal circuit 410C having such a configuration, The alternating voltage appears. Conversely, the drain of the FET 412 shows an AC voltage which is opposite to the input voltage and has the same amplitude as the voltage appearing at the source. The amplitudes of the alternating-current voltage appearing at the source and drain are denoted by Ei.

A series circuit (CR circuit) constituted by a variable resistor 416 and a capacitor 414 is connected between the source and the drain of the FET 412. Therefore, a signal obtained by synthesizing the voltages appearing at the source and the drain of the FET 412 through the variable resistor 416 or the capacitor 414 is output from the output terminal 124.

FIG. 38 is a vector diagram showing the relationship between the input / output voltage of the preceding stage circuit 410C and the voltage appearing on the capacitor or the like.

Since the source and the drain of the FET 412 are in phase and in phase with the input voltage and the alternating voltage of the voltage amplitude Ei appears, the potential difference (alternating current component) between the source and drain becomes 2Ei. The voltage VC1 appearing at both ends of the capacitor 414 and the voltage VR1 appearing at both ends of the variable resistor 416 are out of phase with each other by 90 degrees and the resultant vector is the same as the voltage 2Ei between the source and the drain of the FET 412 .

Therefore, as shown in Fig. 38, a right triangle constituting two sides constituting the two sides of the voltage Ei at right angles and a voltage at both ends VC1 of the capacitor 414 and a voltage at both ends VR1 of the variable resistor 416 are formed. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-end voltage VC1 of the capacitor 414 and the both-end voltage VR1 of the variable resistor 416 change according to the circumference of the semicircle shown in Fig.

However, if the potential difference between the connection point of the capacitor 414 and the variable resistor 416 and the ground level is taken as the output voltage Eo, the output voltage Eo is obtained by crossing the voltage VC1 and the voltage VR1 It can be expressed by a vector having an end point of the circumference as an end point, and its size becomes equal to the radius Ei of the semicircle. In addition, even if the frequency of the input signal changes, the end point of the vector only moves in the circumferential direction, so that a stable output can be obtained in which the output amplitude does not vary according to the frequency.

38, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 412 and the voltage VR1 is theoretically changed from 0 The voltage changes from 270 to 360 in the clockwise direction based on the voltage Ei of the voltage and the in-phase. The phase shift amount? 5 of the entire anomalous circuit 410C changes from 180. to 360. depending on the frequency. Furthermore, by varying the resistance value of the variable resistor 416, the phase shift amount? 5 can be changed.

The transfer function of the abnormal circuit 410C shown in Fig. 37 is a time constant of the CR circuit constituted by the capacitor 414 and the variable resistor 416 as T ₁ (when the capacitance of the capacitor 414 is C and the resistance of the variable resistor 416 is R, T ₁ = CR) speaking, can be applied to K2 shown in equation (2) as and (where, a _{1 <1),} the phase shift amount Φ5 shown in Fig. 38 shown in the above (6) formula Φ1 .

Likewise, FIG. 39 shows the configuration of the rear stage anomaly circuit 430C shown in FIG. The abnormal circuit 430C in the subsequent stage, which is shown in the same figure, includes a FET 432 whose gate is connected to the input terminal 142, a capacitor 434 and a variable resistor 436 connected in series to the source / drain of the FET 432, And a resistor 440 connected between the source of the FET 432 and the ground.

39, the resistance values of the two resistors 438 and 440 connected to the source and the drain of the FET 432 shown in FIG. 39 are set to be substantially the same, and the AC component of the input voltage applied to the input terminal 142 A signal whose phase is inverted from the source of the FET 432 is outputted from the drain of the FET 432, respectively.

The resistor 446 in the abnormal circuit 430C shown in Fig. 36 is for applying a proper bias voltage to the FET 432. Fig. The capacitor 148 provided on the input side of the abnormal circuit 430C is a DC current blocking type excluding the DC component from the output of the abnormal circuit 410C, and only the AC component is inputted to the abnormal circuit 430C.

When a predetermined AC signal is input to the input terminal 142, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 432 in the ideal circuit 430C having the above-described configuration, An alternating voltage appears at the drain of the FET 432. On the other hand, an alternating voltage having the same amplitude and the same voltage appearing as a source opposite to the input voltage appears at the drain of the FET 432. [ The amplitudes of the alternating-current voltage appearing at the source and drain are denoted by Ei.

A series circuit (CR circuit) constituted by a capacitor 434 and a variable resistor 436 is connected between the source and the drain of the FET 432. Therefore, a signal obtained by synthesizing the voltages appearing at the source and the drain of the FET 432 through the capacitor 434 or the variable resistor 436 is output from the output terminal 144.

40 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 430C at the subsequent stage and the voltage appearing in the capacitor or the like.

The potential difference between the source and the drain is 2Ei because the source and drain of the FET 432 exhibit an AC voltage of the same amplitude and opposite phase and voltage amplitude Ei with the input voltage, respectively. The voltage VR2 appearing at both ends of the variable resistor 436 and the voltage VC2 appearing at both ends of the capacitor are 90 degrees out of phase with each other, and the sum of them is equal to the potential difference 2Ei between the source and the drain of the FET 432.

Therefore, as shown in Fig. 40, a right triangle constituting two sides orthogonal to each other is formed by doubling the voltage Ei to the oblique side and the both-end voltage VR2 of the variable resistor 436 and the both-end voltage VC2 of the capacitor 434 at right angles. Therefore, when the amplitude of the input signal is constant and only the frequency is changed, the both-end voltage VR2 of the variable resistor 436 and the both-end voltage VC2 of the capacitor 134 change according to the circumference of the semicircle shown in Fig.

Assuming that the potential difference between the connection point between the variable resistor 436 and the capacitor 434 and the ground level is taken out as the output voltage Eo, this output voltage Eo is obtained by crossing the voltage VR2 and the voltage VC2 with the center point of the semi- It can be expressed by a vector having an end point of the circumference as an end point, and its size becomes equal to the radius Ei of the semicircle. Furthermore, even if the frequency of the input signal changes, the end point of the vector only moves on the circumference, and a stable output can be obtained in which the output amplitude does not change according to the frequency.

40, since the voltage VR2 and the voltage VC2 cross each other at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 432 and the voltage VC2 theoretically becomes zero as the frequency ω changes from 0 to ∞. To 90. &lt; / RTI &gt; The phase shift? 6 of the entire anomalous circuit 430C varies from 0 to 180 according to the frequency.

Further, the transfer function of the one or more circuit 430C shown in Fig. 37 when the time constant of the CR circuit with the capacitor 434 and variable resistor 436 to the capacitance of the T ₂ (the capacitor 434 to the C, R the resistance value of the variable resistor is T ₂ = CR), K3 shown in the expression (3) can be applied as it is (a ₂ <1), and the phase shift amount? 6 shown in FIG. .

Thus, as shown in Figs. 38 and 40, the phase shift amounts of all the two abnormal circuits 410C and 430C are shifted by a predetermined amount, A signal having a total of 360. is output.

In the non-inverting circuit 450 shown in Fig. 36, the FET 452 in which the resistor 454 is connected between the drain and the positive power source and the resistor 456 is connected between the source and the ground is connected to the drain of the FET 452, A transistor 458 connected to the source of the FET 452 through a collector resistor 460, and a resistor 462 for applying a bias voltage suitable for the FET 452. The capacitor 164 provided at the previous stage of the non-inversion circuit 450 shown in Fig. 36 and the output of the subsequent stage anomaly circuit 430C exclude the DC component, and only the AC component is input to the non-inversion circuit 450. [

The FET 452 outputs a reverse-phase signal from the drain when an AC signal is input to the gate. When the phase of the inverted phase signal is input to the base of the transistor 458, that is, the phase of the signal input to the gate of the FET 452 is regarded as a reference, the in-phase signal is output from the collector, Is output from the non-inverting circuit 450.

The output of the non-inverting circuit 450 is taken out from the output terminal 192 as the output of the reference circuit 1F, and the output of the non-inverting circuit 450 is fed through the feedback resistor 170 to the input of the previous- It is returned. Then, the feedback signal is added to the signal input through the input resistor 174, and the voltage of the added signal is applied to the input terminal (input terminal 122 shown in FIG.

The gain of the non-inverting circuit 450 is determined by the resistance values of the resistors 454, 456 and 460. By adjusting the resistance values of the resistors 454, 456 and 460, the two abnormal circuits 410C and 430C, 160, and the loop gain of the whole loop is set to be 1 or less.

Since the output signal of the noninverting circuit 450 before being input to the voltage dividing circuit 160 is taken out from the output terminal 192 of the inquiry circuit 1, the gain of the 1F itself can be made gain and the signal amplitude can be amplified Lt; / RTI &gt;

[Ninth Modification of Tuning Circuit]

Although the tuning circuit shown in Fig. 36 includes a CR circuit in each of the ideal circuits 410C and 430C, it is also possible to constitute a tuning circuit by using an ideal circuit in which the CR circuit is replaced by an LR circuit constituted by a resistor and an inductor .

Fig. 41 is a circuit diagram showing the configuration of the abnormal circuit including the LR circuit, and is shown in a configuration that can be replaced with the abnormal circuit 410C at the preceding stage of the circuit 1F shown in Fig. The abnormal circuit 410L shown in the diagram has a configuration in which a CR circuit constituted by the capacitor 414 and the variable resistor 416 in the preceding stage abnormal circuit 410C shown in Fig. 36 is replaced by an LR circuit composed of the variable resistor 416 and the inductor 417, 418 and the resistance value of the resistance 420 are set to the same value. The capacitor 419 inserted between the inductor 417 and the drain of the FET 412 is for DC current blocking.

The relationship between the input / output voltage of the above-described abnormal circuit 410L and the like is determined by multiplying the voltage VC1 shown in Fig. 38 by the voltage VR1 across the variable resistor 416 and the voltage VR1 shown in Fig. 38 by the voltage VR1 of the inductor 417 End voltage VL1, respectively.

The transfer function of the abnormal circuit 410L shown in FIG. 41 is expressed as T ₁ (the inductance of the inductor 417 is L, the resistance of the variable resistor 416 is R, and the time constant of the LR circuit composed of the inductor 417 and the variable resistor 416 is T ₁ = (A ₁ < 1), the phase shift amount? 7 shown in FIG. 42 can also be obtained by multiplying? 1 and? 2 shown in the above formula (6) .

Therefore, the abnormal circuit 410L shown in FIG. 41 is basically equivalent to the abnormal circuit 410C shown in FIG. 37, and the abnormal circuit 410C shown in FIG. 37 can be replaced with the abnormal circuit 410L shown in FIG.

Fig. 43 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and is shown in a configuration that can be replaced with the abnormal circuit 430C at the rear end of 1F shown in Fig. The abnormal circuit 430L shown in the diagram has a configuration in which the CR circuit constituted by the capacitor 434 and the variable resistor 436 in the rear stage abnormal circuit 430C shown in Fig. 39 is replaced with an LR circuit composed of the variable resistor 436 and the inductor 437, The resistance values of the resistor 440 are set to the same value. The capacitor 439 inserted between the variable resistor 436 and the drain of the FET 432 is for DC current blocking.

The relationship between the input / output voltage of the above-described abnormal circuit 430L is obtained by multiplying the voltage VR2 shown in Fig. 40 by the voltage VL2 across the inductor 437, the voltage VC2 shown in Fig. 40 by the voltage across the variable resistor 436 And the voltage VR2, respectively.

The transfer function of the abnormal circuit 430L shown in FIG. 43 is T ₂ (when the resistance value of the variable resistor 436 is R and the inductance of the inductor 437 is L, T ₂ = (A ₂ < 1), the phase shift amount? 8 shown in FIG. 44 can also be expressed by? ₂ shown in the above-mentioned expression (7) .

Therefore, the abnormal circuit 430L shown in FIG. 43 is basically equivalent to the abnormal circuit 430C shown in FIG. 39, and the abnormal circuit 430C shown in FIG. 39 can be replaced with the abnormal circuit 430L shown in FIG.

Both of the two abnormal circuits 410C and 430C shown in Fig. 36 can be replaced with the abnormal circuits 410L and 430L shown in Figs. 41 and 43. By integrating all of the circuits in question, it is easy to increase the frequency of the tuning frequency do.

When the abnormal circuits 410C and 430C shown in FIG. 36 are replaced by the abnormal circuit 410L shown in FIG. 41 and the abnormal circuit 430L shown in FIG. 43, respectively, the gate voltages of the FETs forming the variable resistors 416 and 436 are changed The EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced with the EX-NOR (exclusive NOR) gate because the direction of the change of the phase shift amount in the case of the EX- It is necessary to reverse the direction of the change of the control voltage, for example, by changing two inputs of one of the voltage comparators 31 and 32. [

In the case where the abnormal circuits 410C and 430C necessary in Fig. 36 are replaced with the abnormal circuits 410L and 430L, respectively, the output of the abnormal circuit at the rear stage may be directly fed back to the preceding stage by omitting the voltage divider circuit 160. [ Alternatively, the resistor 162 in the voltage dividing circuit 160 may be removed to make only the resistor 164. When the voltage dividing circuit 160 is omitted or the resistor 162 is removed, only the tuning operation can be performed.

[Tenth modification of tuning circuit]

45 is a circuit diagram showing another modification of the tuning circuit. The reference numeral 1G denotes two abnormal circuits 410C each performing a phase shift of 180. in total at a predetermined frequency by shifting the phase of an AC signal inputted thereto by a predetermined amount, (Feedback signal) output to the phase inversion circuit 480 and a signal (input signal) input to the input terminal 190 through the feedback resistor 170 and the input resistor 174, respectively, and a phase inverting circuit 480 for inverting the phase of the signal further And an adder circuit for adding in a predetermined ratio.

37 and FIG. 38. For example, assuming that the time constant of the CR circuit constituted by the capacitor 414 and the variable resistor 416 is T ₁ , the phase relationship between the detailed configuration and the input / The phase shift amount PHI _{5 at} the frequency of 1 / T ₁ becomes 270 in the clockwise direction (phase slowing direction).

Therefore, the sum of the amount of phase shift in the phase slowing direction by the entirety of two abnormal circuits 410C becomes? 5 +? 5 = 270. + 270. = 540. (= 180.) At a predetermined frequency.

The error inversion circuit 480 includes a FET 482 having a resistor 484 connected between the drain and the positive power source and a resistor 486 connected between the source and the ground, and a resistor 488 applying a predetermined bias voltage to the gate of the FET 482 Consists of. When an AC signal is input to the gate of the FET 482, a reverse-phase signal inverted in phase is output from the drain of the FET 482. And the phase inversion circuit 480 has a predetermined gain determined by the resistance ratio of the two resistors 484 and 486.

As described above, the phase by the two or more circuits 410C is shifted by 180. At the predetermined frequency, the phase is inverted by the phase inversion circuit 480 connected at the subsequent stage, and the sum of the amounts of phase shift by the entirety of these three circuits is 360. Accordingly, the output of the phase inversion circuit 480 is fed back to the input side of the anomaly circuit 410C at the previous stage through the feedback resistor 170, the signal input through the input resistor 174 is added to the feedback signal, and the gain of the phase inversion circuit 480 is adjusted The same tuning operation as in step 1 is performed.

45, the output of the phase inversion circuit 480 is directly fed back through the feedback resistor 170. However, like the phase inversion circuit 1F shown in Fig. 36, the output of the phase inversion circuit 480 And the partial pressure output may be returned.

[Eleventh Modification of Tuning Circuit]

46 is a circuit diagram showing another modified example of the tuning circuit, and contrary to Fig. 45, the tuning circuit includes a rear stage anomaly circuit 430C shown in Fig.

The 1H circuit shown in FIG. 46 includes two abnormal circuits 430C, each of which performs a phase shift by 180. at a predetermined frequency by shifting the phases of AC signals input thereto by a predetermined amount, and outputs (A feedback signal) output from the phase inversion circuit 480 and a signal (input signal) input to the input terminal 190 through the feedback resistor 170 and the input resistor 174, and a phase inversion circuit 480 for inverting the phase of the signal further And an adder circuit for adding in a predetermined ratio.

39 and 40. For example, assuming that the time constant of the CR circuit constituted by the capacitor 434 and the variable resistor 436 is T ₂ , the phase relationship between the detailed configuration and the input of each ideal circuit 430C is as follows. The phase shift amount phi 6 at the frequency of 1 / T ₂ becomes 90 in the clockwise direction (phase slow direction).

Therefore, the phase is shifted 180 degrees by the two or more circuits 430C at a predetermined frequency, the phase is inverted by the phase inverting circuit 480 connected at the subsequent stage, and the sum of the amounts of phase shift by the three circuits as a whole is 360 . Therefore, the output of the phase inversion circuit 480 is fed back to the input side of the anterior error circuit 430C through the feedback resistor 170, the signal inputted through the input resistor 174 is added to the feedback signal, and the gain of the phase inversion circuit 480 is adjusted The same tuning operation as that of the tuning reference 1 shown in Fig. 2 is performed.

46, the voltage divider circuit 160 may be connected to the rear end of the phase inversion circuit 480 to perform the amplification simultaneously with the tuning.

1F, 1G, 1H, and the like as described above are constituted by two or more abnormal circuits, a non-inverting circuit, two abnormal circuits, and a phase inverting circuit, And the total phase shift amount in the frequency is 360. The predetermined tuning operation is performed. Therefore, if only the amount of phase shift is taken into consideration, there is a certain degree of freedom in how to connect the three circuits in order, and the order of connection can be determined as needed.

45 and Fig. 46, an example in which the CR circuit is included in the abnormal circuit is shown in 1G and 1H. However, even if the tuning circuit is constructed by cascade-connecting the abnormal circuits including the LR circuit do. For example, the abnormality circuit 410L shown in Fig. 41 may be connected instead of two abnormal circuits 410C of 1G as shown in Fig. Alternatively, the abnormal circuit 430L shown in FIG. 43 may be connected to 1H in place of the two or more abnormal circuits 430C.

However, when the abnormal circuit including the CR circuit is replaced with the abnormal circuit including the LR circuit, the direction of the change of the phase shift amount when the gate voltage of the FET forming the variable resistors 416 and 436 is changed is opposite The EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 may be replaced with an EX-NOR (EXCLUSIVE-NOOR) gate, or two inputs of the voltage comparators 31 and 32 shown in FIG. It is necessary to reverse the direction of the change of the control voltage.

In addition, in the above-described embodiments, the 1F, 1G, and 1H circuits are configured with the FET 412 or the FET 432. However, an anomalous circuit may be formed using a high transistor instead of the FET.

[Twelfth Modification of Tuning Circuit]

47 is a circuit diagram showing a twelfth modification of the tuning circuit; The reference numeral 1J denotes a non-inverting circuit 550 that outputs the input AC signal without changing the phase of the input AC signal, and each of the non-inverting circuits 550 shifts the phase of the input signal by a predetermined amount so that a total of 360.phase shifts A feedback resistor 170 and an input resistor 174 (the input resistor 174 is connected to the input terminal of the feedback resistor 170, which is n times as large as the feedback resistor 170), and a voltage divider circuit 160 composed of two abnormal circuits 510C and 530C, (A feedback signal) of the voltage divider circuit 160 and a signal (input signal) input to the input terminal 190 at a predetermined ratio.

The non-inverting circuit 550 functions as a buffer circuit and is provided to prevent signal loss or the like, which occurs when the preceding-stage abnormal circuit 510C and the above-described adding circuit are directly connected. The non-inverting circuit 550 is constituted by, for example, an emitter flow circuit and a source flow circuit. In the case where the element constant of each element is selected as the feedback resistor 170 or the like in order to minimize the loss or the like in the case of direct connection, the noninverting circuit 550 may be omitted to constitute the tuning circuit.

Fig. 48 is a drawing showing the configuration of the preceding stage anomaly circuit 510C shown in Fig. The anomalous circuit 510C of the preceding stage shown in the diagram shows a differential amplifier 512 for amplifying and outputting a differential voltage of two inputs with a predetermined degree of amplification and a differential amplifier 512 for shifting the phase of a signal inputted to the input stage 122 by a predetermined amount and inputting to the non- And a resistor 518 and a resistor 520 for dividing the voltage level of the signal input to the input stage 122 and inputting the divided voltage to the inverting input terminal of the differential amplifier 512 .

The above-described variable resistor 516 is used, for example, as a resistor for a channel formed between source and drain of a junction-type FET, as shown in FIG. 48. It is possible to arbitrarily change the resistance value within a certain range by varying the gate voltage have.

When a predetermined AC signal is input to the input terminal 122 shown in FIG. 48, a voltage obtained by dividing the voltage Ei applied to the input terminal 122 by the resistor 518 and the resistor 520 is applied to the inverting input terminal of the differential amplifier 512.

When the input signal is input to the input terminal 122, a signal appearing at the connection point between the capacitor 514 and the variable resistor 516 is input to the non-inverting input terminal of the differential amplifier 512. Since the input signal is inputted to one end of the CR circuit constituted by the capacitor 514 and the variable resistor 516, the voltage of the signal obtained by shifting the phase of the input signal by a predetermined amount by this CR circuit is applied to the non-inverting input terminal of the differential amplifier 512 do. The differential amplifier 512 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals by a predetermined amplification degree.

Fig. 49 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 510C shown in Fig. 48 and the voltage appearing on the capacitor or the like.

As shown in the figure, the voltage VR1 appearing at both ends of the variable resistor 516 and the voltage VC1 appearing at both ends of the capacitor 514 are shifted by 90 degrees from each other. The input voltage Ei is obtained by adding them vectorially. Therefore, when the amplitude of the input signal is constant and only the frequency is changed, the both-end voltage VR1 of the variable resistor 516 and the both-end voltage VC1 of the capacitor 514 change according to the circumference of the semicircle shown in Fig.

The voltage (the both end voltage Ei / 2 of the voltage 520) applied to the inverting input terminal from the voltage (the both end voltage VR1 of the variable resistor 516) applied to the noninverting input terminal of the differential amplifier 512 is obtained by subtracting the difference voltage Eo '. This differential voltage Eo 'can be expressed by a vector having an origin at a circumferential point where the voltage VR1 and the voltage VC1 intersect with each other at the center point of the semicircle shown in Fig. 49, and the size thereof is represented by the radius Ei / 2 &lt; / RTI &gt;

The output voltage Eo of the differential amplifier 512 is obtained by amplifying the difference voltage Eo 'by a predetermined amplification degree. Therefore, in the above-described abnormal circuit 510C, the output voltage Eo is constant regardless of the frequency of the input signal and operates as a global pass circuit.

49, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VR1 varies in the clockwise direction (phase In the slow direction). The total phase shift amount phi 9 of the error circuit 510C varies from 180 to 360 depending on the frequency.

Likewise, FIG. 50 shows the structure of the rear stage anomaly circuit 530C shown in FIG. An abnormal circuit 530C for displaying on the same diagram a differential amplifier 532 for amplifying and outputting a differential voltage of two inputs with a predetermined degree of amplification and a differential amplifier 532 for inputting a signal to the noninverting input terminal of the differential amplifier 532 And resistors 538 and 540 for dividing the voltage level of the signal by a factor of about 1/2 without inputting the phase of the signal input to the input terminal 142 and inputting it to the inverting input terminal of the differential amplifier 532 .

When a predetermined AC signal is input to the input terminal 142 shown in FIG. 50, a voltage obtained by dividing the voltage Ei applied to the input terminal 142 by the resistor 538 and the resistor 540 is applied to the inverting input terminal of the differential amplifier 532.

When the input signal is input to the input terminal 142, a signal appearing at the connection point between the variable resistor 536 and the capacitor 534 is input to the non-inverting input terminal of the differential amplifier 532. Since the input signal is inputted to one end of the CR circuit constituted by the variable resistor 536 and the capacitor 534, the voltage of the signal obtained by shifting the phase of the input signal by a predetermined amount by this CR circuit is applied to the non-inverting input terminal of the differential amplifier 532 do.

The differential amplifier 532 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals by a predetermined amplification degree.

51 is a vector diagram showing the relationship between the input / output voltage of the error circuit 530C and the voltage appearing on the capacitor or the like.

As shown in the figure, the voltage VC2 appearing at both ends of the capacitor 534 and the voltage VR2 appearing at both ends of the variable resistor 536 are delayed by 90 degrees from each other, and they are vectorially added to become the input voltage Ei. Therefore, when the amplitude of the input signal is constant and only the frequency is changed, the both-end voltage VC2 of the capacitor 534 and the both-end voltage VR2 of the variable resistor 536 change along the circumference of the semicircle shown in Fig.

The voltage (the both end voltage Ei / 2 of the resistor 540) applied to the inverting input terminal from the voltage (the both end voltage VC2 of the capacitor 534) applied to the noninverting input terminal of the differential amplifier 532 is obtained by subtracting the difference voltage Eo ' . This difference voltage Eo 'can be expressed by a vector having a circle at a point where a voltage VC2 and a voltage VR2 intersect with each other at the center point of the semicircle shown in Fig. 51, and the size thereof is represented by the radius Ei / 2 &lt; / RTI &gt;

The output voltage Eo of the differential amplifier 532 is obtained by amplifying the differential voltage Eo 'by a predetermined amplification degree. Therefore, in the above-described abnormal circuit 530C, the output voltage Eo is constant regardless of the frequency of the output signal and operates as a global pass circuit.

51, since the voltage VC2 and the voltage VR2 cross at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VC2 varies from 0 to 90 as the frequency ω varies from 0 to ∞. The phase shift amount? 10 of the whole of the ideal circuit 530C varies from 0 to 180 according to the frequency.

In this way, the phases are shifted by a predetermined amount in each of the two abnormal circuits 510C and 530C, and as shown in FIG. 49 and FIG. 51, the phase shift of the two abnormal circuits 510C and 530C A signal having a total of 360 degrees is output.

The output of the error circuit 530C at the subsequent stage is taken out from the output terminal 192 as the output of the reference 1J and the output of the error circuit 530C is fed back through the feedback resistor 170 to the input side of the non- do. The signal to which the feedback signal is input via the input resistor 174 is added, and the added signal is input to the previous-stage error circuit 510C through the non-inversion circuit 550. [

By adjusting the gains of the above two abnormal circuits 510C and 530C, it is possible to compensate for the loss caused by the attenuation caused by the two abnormal circuits 510C and 530C and the voltage divider circuit 160 shown in FIG. 47 or the feedback loop, So that the total loop gain is set to 1 or less. Instead of adjusting the respective gains of the error circuits 510C and 530C, the non-inverting circuit 550 may have one or more gains to adjust this value.

Since the output of the ideal circuit 530C is taken out from the 1J output terminal 192 before being input to the voltage dividing circuit 190, the gain can be given to the 1J itself, and the signal amplitude can be amplified simultaneously with the tuning operation do.

When the amplitude operation is unnecessary in the tuning circuit shown in Fig. 47, the voltage divider circuit 160 may be omitted and the output of the abnormal circuit 530C may be directly fed back to the previous stage. Alternatively, the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value, and the division ratio may be set to 1.

[Modification 13 of the tuning circuit]

47, each of the ideal circuits 510C and 530C includes a CR circuit. However, a tuning circuit may be constructed by using an ideal circuit in which a CR circuit is replaced by an LR circuit constituted by a resistor and an inductor.

Fig. 52 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 510C of the preceding stage of the circuit 1J shown in Fig. The abnormal circuit 510L shown in the diagram has a configuration in which the CR circuit constituted by the capacitor 514 and the variable resistor 516 in the abnormal circuit 510C shown in FIG. 48 is replaced by an LR circuit composed of the variable resistor 516 and the inductor 517. The capacitor 519 connected in series to the inductor 517 is for direct current blocking, and its impedance is set to be extremely small at the operating frequency, that is, it has a large capacitance.

53 is a vector diagram showing the relationship between the input / output voltage of the error circuit 510L and the voltage appearing in the inductor or the like. The phase shift amount? 11 of the abnormal circuit 510L displayed in the diagram is T ₁ (the resistance value of the variable resistor 516 is R, and the inductance of the inductor 517 is L, which is the time constant of the LR circuit constituted by the variable resistor 516 and the inductor 517, ₁ = L / R), it becomes equal to? 1 shown in the above-mentioned expression (6).

Fig. 54 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 530C in the rear stage of 1J shown in Fig. The abnormal circuit 530L shown in the diagram has a configuration in which a CR circuit constituted by a variable resistor 536 and a capacitor 534 in the abnormal circuit 530C shown in Fig. 50 is replaced with an LR circuit composed of an inductor 537 and a variable resistor 536. [ The capacitor 539 connected in series to the inductor 537 is for direct current blocking, and its impedance is set to be extremely small at the operating frequency, that is, it has a large capacitance.

55 is a vector diagram showing the relationship between the input / output voltage of the error circuit 530L and the voltage appearing in the inductor or the like. The phase shift amount? 12 of the abnormal circuit 530L shown in the diagram is T ₂ (the inductance of the inductor 137 is L, the resistance of the variable resistor 536 is R, and T is the time constant of the LR circuit constituted by the inductor 537 and the variable resistor 536, ₂ = L / R), it becomes the same as? 2 shown in the above-mentioned expression (7).

When the abnormal circuits 510C and 530C shown in Fig. 47 are replaced with the abnormal circuit 510L shown in Fig. 52 and the abnormal circuit 530L shown in Fig. 54, respectively, the case where the gate voltage of the FET forming the variable resistor 536 is changed The EX-NOR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced with the EX-NOR gate because the direction of the change of the phase shift amount is opposite, It is necessary to reverse the direction of the change of the control voltage by changing the two inputs of either one of the comparators 31 and 32. [

As described above, each of the abnormal circuit 510L shown in Fig. 52 and the abnormal circuit 530L shown in Fig. 54 is equivalent to the abnormal circuits 510C and 530C shown in Fig. 48 or Fig. 50, It is possible to replace the abnormal circuit 510C at the preceding stage with the abnormal circuit 510C shown in FIG. 52 and replace the abnormal circuit 530C at the subsequent stage with the abnormal circuit 530L shown in FIG. 54, respectively. In the case where both of the two abnormal circuits 510C and 530C are replaced with the abnormal circuits 510L and 530L, it is easy to increase the frequency of the tuning frequency by integrating the entire circuit.

[Fourteenth modification of the tuning circuit]

Although the tuning circuit 1J shown in Fig. 47 includes two or more circuits differing from each other in the ideal direction, a tuning circuit can be formed by combining two or more circuits having basically the same configuration.

56 is a circuit diagram showing another configuration of the tuning circuit; 1K shows a phase inversion circuit 580 for inverting and outputting the phase of an input AC signal and a phase inversion circuit 580 for shifting the phases of the AC signals inputted thereto by a predetermined amount, (Feedback signal) of the voltage divider circuit 160 by passing through the voltage divider circuit 160 consisting of the two abnormal circuits 510C for performing the voltage divider circuit 160 and the resistors 162 and 164 provided at the rear ends of the rear-stage abnormal circuit 510C, And an adder circuit for adding a signal (input signal) input to the input terminal 190 at a predetermined ratio.

The detailed configuration of the two abnormal circuits 510C and the phase relationship between the input and output signals are as described with reference to Figs. 48 and 49, and the sum of the amounts of phase shift by the two abnormal circuits 510C as a whole is 180. .

The phase inversion circuit 580 connected to the previous stage of the two more circuits 510C inverts the phase of the input AC signal. For example, the phase inversion circuit 580 realizes an emitter ground circuit, a source ground circuit, an operational amplifier, do.

In this manner, the phase is shifted 180 degrees by the two or more circuits 510C at a predetermined frequency, the phase is inverted by the phase inversion circuit 580 connected to the preceding stage, and the sum of the amounts of phase shift by the three circuits as a whole is 360 .

The output of the error circuit 510C at the subsequent stage is taken out from the output terminal 192 as an output of 1K and the output of the error circuit 510C at the subsequent stage is input to the input side of the phase inversion circuit 580 through the feedback resistor 170 Return. Then, the feedback signal is added to the signal input through the input resistor 174, and the added signal is input to the phase inversion circuit 580.

Thus, the output of the voltage divider circuit 160 is fed back to the input side of the phase inverter circuit 580 through the feedback resistor 170, the signal inputted through the input resistor 174 is added to the feedback signal, and the gain of the two- It is possible to perform a tuning operation and an amplification operation in the same manner as in 1J by referring to FIG. 47 by compensating for the loss occurring at the connection portion between the feedback resistor 170 and the input resistor 174. Instead of adjusting each gain of the error circuit 510C, the gain of the phase inversion circuit 580 may be adjusted.

When the amplifying operation is not required in the inquiry circuit 1K shown in FIG. 56, the voltage dividing circuit 160 may be omitted and the output of the abnormal circuit 510C may be directly fed back to the previous stage. Alternatively, the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value, and the division ratio may be set to 1.

[Modification 15 of the tuning circuit]

Fig. 57 is a circuit diagram showing another modified example of the tuning circuit. Contrary to Fig. 56, the tuning circuit includes the following error circuit 530C shown in Fig.

57 includes two abnormal circuits 530C for performing a total 180 占 phase shift at a predetermined frequency by shifting the phases of AC signals input thereto by a predetermined amount, (Feedback signal) output from the phase inversion circuit 580 and a signal (input signal) input to the input terminal 190 by passing through each of the feedback resistor 170 and the input resistor 174, a phase inversion circuit 580 for further inverting the phase of the output signal, In a predetermined ratio.

50 and 51. For example, assuming that the time constant of the CR circuit composed of the capacitor 534 and the variable resistor 536 is T ₂ , the phase relationship between the detailed configuration and the input / output of each ideal circuit 530 C is ω = The phase shift amount PHI 10 at the frequency of 1 / T ₂ becomes 90 in the clockwise direction (phase slowing direction). Therefore, the sum of the amount of phase shift due to the entire two circuits 530C at a predetermined frequency is 180. [

Even when the above-described two abnormal circuits 530C are used, the phase is shifted 180 degrees by two abnormal circuits 530C at a predetermined frequency, the phase is inverted by the phase inversion circuit 580 connected to the preceding stage, The sum of the amount of phase shift due to the entire circuit is 360. [

Therefore, in the above-described circuit 1L, the output of the voltage dividing circuit 160 is fed back to the input side of the phase inversion circuit 580 through the feedback resistor 170, the signal inputted through the input resistor 174 is added to the feedback signal, The gain of the feedback loop is adjusted to compensate for the loss or the like occurring at the junction of the feedback resistor 170 and the input resistor 174, and the loop gain of the feedback loop is set to 1 or less. As a result, It is possible to perform the tuning operation and the amplifying operation.

56 and FIG. 57, 1K and 1L are cascaded with an abnormal circuit including a CR circuit therein. However, the two circuits may include an LR circuit for both of the abnormal circuits.

More specifically, the two abnormal circuits 510C in the 1K circuit shown in FIG. 56 may be replaced by the abnormal circuit 510L shown in FIG. The two abnormal circuits 530C in 1L shown in FIG. 57 may be replaced by the abnormal circuit 530L shown in FIG.

However, when the abnormal circuit including the CR circuit is replaced with the abnormal circuit including the LR circuit, the direction of the change in the phase shift amount when the gate voltage of the FET forming the variable resistor 116 or 136 is changed is opposite The EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced by an EX-NOR (exclusive NOR) gate, or the two inputs of the voltage comparators 31 and 32 shown in FIG. It is necessary to invert the direction of the change of the control voltage.

However, the above-described circuits 1J, 1K, and 1L are configured to include a non-inverting circuit, two or more abnormal circuits, or a phase inverting circuit and two or more abnormal circuits. A predetermined tuning operation is performed by setting the total phase shift amount to 360. FIG. Therefore, considering only the amount of phase shift, there is a certain degree of freedom in which one of the two or more circuits is used in the preceding stage or in which order the three circuits are connected, and the order of connection can be determined if necessary.

In the above-mentioned each tuning circuit, when the abnormal circuit including the CR circuit is replaced with the abnormal circuit including the LR circuit, only one of the two abnormal circuits connected in cascade is replaced with the abnormal circuit including the LR circuit You can. However, in this case, since the control direction of the resistance value of the variable resistor 116 in the abnormal circuit at the previous stage is opposite to the control direction of the resistance value of the variable resistor 136 in the abnormal circuit at the subsequent stage, the output level of the distributor 5 shown in Fig. 13 is inverted A slight modification of the circuit is required. In this way, the ideal circuit including the CR circuit and the ideal circuit including the LR circuit are cascade-connected to constitute a tuning circuit. When the entire circuit is integrated, the so-called temperature compensation Lt; / RTI &gt;

In each of the tuning circuits described above, the phase difference between the input / output signals of the succeeding stage is detected, but the phase difference between the input / output signals of the preceding stage is detected. In this case, the EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is set to the EX-NOR state because the direction of the change in the phase shift amount is opposite to that in the case where the phase difference between the input / A slight circuit modification such as replacement with a gate is required

[J. Other Modifications]

However, the various tuning mechanisms shown in Figs. 1 and 20 are formed by using the junction type FETs in the variable resistors 116 and the like in the two or more circuits constituting the tuning circuit, but the variable resistors may be formed by other elements.

58, the variable resistors 116 and 136 in the abnormal circuits 110C and 130C shown in Fig. 3 are replaced by variable resistors 115 and 135 formed of MOS type FETs, respectively. Thus, the channel formed in the source and drain of the MOS type FET can be used as a resistor. In this case, since the channel resistance of the FET can be changed by changing the control voltage applied to the gate, the tuning frequency of the tuning circuit 1 can be arbitrarily changed within a certain range.

In the above-described abnormal circuit 110C and the like, the entire tuning frequency is changed by changing the resistance value of the variable resistor 116 or the like connected in series with the capacitor 114 or the like to change the amount of phase shift. However, by changing the capacitance of the capacitor 114 or the like May be changed.

FIG. 59 is a diagram showing the configuration of a tuning circuit in which the entire tuning frequency is changed by changing the capacitance of the capacitor. FIG. The reference numeral 1N shown in the figure is based on the abnormal circuits 110C and 130C shown in Fig. 2, but may be configured based on various abnormal circuits shown in Figs. 29 and 46 and the like.

In FIG. 59, the capacitors 128 and 148 connected in series to the variable capacitance diodes 127 and 147 are for blocking the direct current when applying the reverse bias voltage to the variable capacitance diode, and the impedance thereof is extremely small at the operating frequency, That is, it has a large capacitance.

In the tuning circuit shown in Fig. 59, the capacitance is varied by using a variable capacitance diode as the variable capacitance element. However, the FET whose gate voltage can be changed within a certain range in accordance with the control voltage applied to the gate is used as the variable capacitance element .

60 is a circuit diagram showing an example in which elements other than FETs are used as variable resistors in the abnormal circuits 110 and 130 shown in Fig.

The abnormal circuit 110C "shown in FIG. 60 has a configuration in which the variable resistor 116 formed by using the FET in the abnormal circuit 110C shown in FIG. 2 is replaced with a CdS photo cassette 177 which is a CdS photodetector and a light emitting diode. Since the CdS photosensor included in the photo frame 177 has a characteristic that the resistance value becomes smaller as the amount of light emitted from the light emitting diode increases, the CdS photo frame 177 can be used as a variable resistor whose resistance value can be changed according to a control current from the outside.

Similarly, the abnormal circuit 130C "shown in FIG. 60 has a configuration in which the variable resistor 136 formed by using the FET in the abnormal circuit 130C shown in FIG. 2 is replaced with a CdS photo sensor and a CdS photo-clave 179 which is a light-emitting diode.

The control voltage generating circuit 4B shown in Fig. 60 has a configuration in which the control voltage generating circuit 4 shown in Fig. 13 is partially modified, and a bias circuit composed of a variable resistor 42 and a resistor 43 is connected to the control voltage generating circuit 4 But it is removed.

The voltage-current exchange circuit 200 shown in FIG. 60 includes an operational amplifier 204 in which a control voltage, which is an output of the control voltage generating circuit 4B, is input to the inverting input terminal through the resistor 202, and a variable resistor 206, &lt; / RTI &gt;

In the operational amplifier 204, two light emitting diodes in the photo-couplers 177 and 179 are connected in series between the output terminal and the inverting input terminal, and the non-inverting input terminal is grounded. Therefore, when the output voltage (control voltage) of the control voltage generating circuit 4B is determined, a predetermined current determined by the resistance ratio of the resistor 202 and the variable resistor 206 flows into each light emitting diode in the photo couplers 177 and 179, A pair of CdS photo sensors has a constant resistance value in accordance with the quantity of light emitted from the light emitting diode.

Therefore, by lowering the output voltage of the control voltage generating circuit 4B, the current value flowing through the light emitting diode becomes smaller and the light emitting amount becomes smaller, and the resistance value of the CdS photo sensor becomes higher, so that the tuning frequency of the tuning circuit shown in FIG. On the contrary, by increasing the output voltage of the control voltage generating circuit 4B, the current value flowing through the light emitting diode is increased, the amount of emitted light is increased, and the resistance value caused by the CdS photosensor is lowered and the tuning frequency of the tuning circuit 1 becomes higher. This relationship is the same as the relationship between the variable resistor formed by the above-described FET and the control voltage, and the tuning frequency of the tuning circuit 1 can be matched with the frequency of the input signal by exactly the same control procedure. By using the photo couplers 177 and 179 as variable resistors in this way, a tuning circuit for realizing the tuning mechanism of the above-described embodiment can be constituted. When the photo couplers 177 and 179 are used as variable resistors, a constant resistance value can always be obtained irrespective of the voltage across the variable resistor or the like, so that there is an advantage that a coherent output with less stress can be easily obtained. However, since the entire inspection circuit including the photocarves 177 and 179 can not be integrated on the semiconductor substrate, the photoclaves 177 and 179 are connected to each other by using connecting lines or the like.

In each of the above-described tuning circuits, high reliability can be achieved by configuring the tuning circuit 1 using the ideal circuits 110C and 130C using op-amps. In the case of using the same circuits as the abnormal circuits 110 and 130 of this embodiment, Since the voltage or voltage gain does not require high performance, a differential amplifier having a predetermined amplification degree may be used in place of the op-amp in each of the above-mentioned abnormal circuits.

FIG. 61 is a circuit diagram of a portion of an op-amp structure necessary for operation of an abnormal circuit, and the whole circuit operates as a differential amplifier having a predetermined amplification degree. The differential amplifier shown in the diagram is composed of a differential input stage 100 composed of FETs. A constant current circuit 102 for sending a constant current to the differential input stage 100, a bias circuit 104 for applying a predetermined bias voltage to the constant current circuit 102, and an output amplifier 106 connected to the differential input stage 100. It is possible to omit the multi-stage amplifying circuit for obtaining the voltage gain included in the actual op-amp as shown in the diagram, to simplify the configuration of the differential amplifier and to make it wider. Since the upper limit of the operating frequency can be increased by simplifying the circuit in this way, the upper limit of the tuning frequency of the tuning circuit 1 constructed using the differential amplifier can be increased by two.

The present invention is not limited to the above-described various embodiments, and various modifications can be made within the scope of the present invention.

2, for example, a feedback resistor 170 is used as a feedback impedance element and an input resistor 174 is used as an input impedance element. However, it is also possible to change the phase relationship of signals input to the respective elements The feedback impedance element and the input impedance element may be formed by capacitors instead of resistors or the impedance and capacitors may be combined to adjust the ratio of the real number and the odd number simultaneously to the impedance.

At least one of the feedback resistor 170 and the input resistor 114 may be constituted by a variable resistor to vary the tuning bandwidth in the tuning amplifier 1 or the like.

In the abnormal circuit 110 shown in FIG. 2, the variable resistor 116 is composed of one FET, but a P-channel FET and an n-channel FE may be connected in parallel to constitute one variable resistor. By configuring the variable resistors by combining the two FETs as described above, it is possible to improve the non-linear region of the FET, thereby reducing the stress of the tuning output.

As described above, the tuning control system of the present invention can reliably match the tuning frequency to the frequency of the input signal in order to feedback-control the tuning frequency of the tuning circuit so that either the frequency of the input signal or the tuning frequency of the tuning circuit disappears. Therefore, when the entire tuning mechanism is integrated, the tuning characteristics do not change even if the frequency characteristics vary from chip to chip. Even if the element constants of the elements for determining the tuning frequency fluctuate due to temperature or the like, the tuning frequency does not fluctuate and is suitable for integration.

Claims (53)

The output of two or more crossover-connected crossover-connected all-pass circuits and the output of the above-mentioned abnormal circuit as a feedback signal is fed back to the input side of the above-mentioned abnormal circuit at the previous stage, and the feedback signal and the input signal are added to the above- A tuning circuit including an adding circuit for inputting only a signal in the vicinity of a predetermined frequency, Wherein when a signal having a frequency in the vicinity of the predetermined frequency is input to the tuning circuit, a tuning frequency of the tuning circuit based on a phase difference between input / output signals of one of the tuning circuits included in the tuning circuit, And a frequency control circuit which coincides with the frequency, The method according to claim 1, Wherein each of the two abnormal circuits included in the tuning circuit includes a serial circuit whose time constant can be changed, and when the frequency of the input signal of the tuning circuit is different from the tuning frequency of the tuning circuit, Wherein the tuning frequency of the tuning circuit is made to coincide with the frequency of the input signal of the tuning circuit by changing the phase shift amount of each ideal circuit while keeping the time constants of the series circuits of the tuning circuit of the tuning circuit of the tuning circuit of the tuning circuit equal. 3. The method of claim 2, Wherein each of the series circuits comprises a reactance element by a capacitor or an inductor and a first resistor, the time constant of the series circuits of both is changeable by a control signal output from the frequency control circuit, Wherein the control circuit outputs the control signal so that the tuning frequency of the tuning circuit matches the frequency of the input signal of the tuning circuit. The method of claim 3, Wherein the frequency control circuit changes the time constant of the series circuit included in each of the two or more ideal circuits when the phase difference of the input / output circuit of one of the ideal circuits included in the tuning circuit is 90. shifted, And the phase difference of the input / output signal of the ideal circuit of the phase locked loop is controlled to be 90. [ 5. The method of claim 4, A phase difference detecting circuit for outputting a first rectangular wave signal whose duty ratio changes in accordance with a phase difference between input and output signals of one of the abnormal circuits included in the tuning circuit; And a control voltage generating circuit for generating a control voltage whose voltage level changes according to the ratio, and outputs the control voltage as the control signal. 6. The method of claim 5, Wherein the phase difference detection circuit comprises: a first voltage comparator for outputting a second square wave signal synchronized with an input signal of any one of the abnormal circuits included in the tuning circuit; and a third square wave And a square wave synthesizing means for synthesizing the second and third square wave signals and outputting the first square wave signal. The method according to claim 6, Wherein the square wave synthesizing means comprises a logic gate for calculating an exclusive OR of the second and third rectangular wave signals, and the output of the logic gate is the first rectangular wave signal. The method according to claim 6, Wherein the square wave synthesizing means comprises a tri-state buffer for passing or blocking a signal inputted to the input terminal according to the voltage level of the control terminal, and wherein one of the second and third square wave signals is connected to the control terminal And the other side is input to the input terminal, and the output of the tri-state buffer is used as the first square wave signal. 6. The method of claim 5, Wherein the control voltage generating circuit comprises a smoothing circuit for smoothing the first rectangular wave signal outputted from the phase difference detecting circuit and an amplifier for amplifying an output voltage of the smoothing circuit and outputting the control voltage, . The method of claim 3, At least one of the two abnormal circuits included in the tuning circuit includes a differential amplifier having an inverting input terminal to which an AC signal is input via the second resistor connected to one end of a second resistor, And a third resistor connected between the first resistor and the input terminal of the differential amplifier, wherein the series circuit is connected to the other end of the second resistor, and the junction between the first resistor and the reactance element constituting the series circuit Inverting input terminal of the differential amplifier. 11. The method of claim 10, Wherein the tuning circuit includes a non-inverting circuit that outputs the input AC signal without changing the phase of the input AC signal, the non-inverting circuit is inserted into a part of the feedback loop formed by the two cascaded circuits, Wherein the circuit passes only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 11. The method of claim 10, Wherein the tuning circuit has a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Passes only a signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 180. due to the entirety of two or more cascaded circuits connected in cascade. 11. The method of claim 10, And a flow circuit by a transistor is inserted in a front end of the two or more cascaded circuits. 11. The method of claim 10, Wherein a partial voltage circuit is inserted into a part of a feedback loop formed by the two or more cascade-connected cascaded circuits, and the tuning circuit outputs an alternating signal inputted to the voltage dividing circuit as a tuning signal. 11. The method of claim 10, Wherein the first resistor in the series circuit is formed as a variable resistor and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor according to the voltage level of the control signal. 11. The method of claim 10, Wherein the differential amplifier is an operational amplifier. 11. The method of claim 10, Wherein the component parts are integrally formed on a semiconductor substrate. The method of claim 3, At least one of the two abnormal circuits included in the tuning circuit includes a differential amplifier in which an inverted input terminal is connected to a second resistor at one end and an AC signal is input through the second resistor, And a third resistor connected between an output terminal of the first voltage dividing circuit and an inverting input terminal of the differential amplifier, and the other end of the second resistor is connected to the other end of the second resistor, And the connection of the first resistor and the reactance element constituting the series circuit are connected to the non-inverting input terminal of the differential amplifier. 19. The method of claim 18, Wherein the non-inverting circuit is inserted in a part of a feedback loop formed by the two cascaded circuits, and the non-inverting circuit is inserted into a part of the feedback loop formed by the two cascade- Wherein the tuning circuit passes only a signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. due to all of the two or more cascaded circuits connected in cascade. 19. The method of claim 18, Wherein the tuning circuit is provided with a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Passes only a signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 180. due to the entirety of two or more cascaded circuits connected in cascade. 19. The method of claim 18, And a flow circuit by a transistor is inserted in a front end of the two or more cascaded circuits. 19. The method of claim 18, And a second voltage dividing circuit is inserted in a part of a feedback loop formed by the two cascade-connected cascaded circuits, and the tuning circuit outputs an alternating signal inputted to the first voltage dividing circuit as a tuning signal. Control method. 19. The method of claim 18, Wherein the first resistor in the series circuit is formed by a variable resistor and the frequency of the tuning circuit is varied by changing the resistance value of the variable resistor in accordance with the voltage level of the control signal. 19. The method of claim 18, Wherein the differential amplifier is an operational amplifier. 19. The method of claim 18, And the component parts are integrally formed on the semiconductor substrate. The method of claim 3, At least one of the two abnormal circuits included in the tuning circuit includes a differential amplifier in which one end of a second resistor is connected to the inverting input terminal and an AC signal is input through the second resistor, And a fourth resistor having one end connected to the inverting input terminal of the differential amplifier and the other end grounded, and the other end of the second resistor is connected to the other end of the series circuit And the connection of the first resistor and the reactance element constituting the series circuit is connected to the non-inverting input terminal of the differential amplifier. 27. The method of claim 26, Wherein the tuning circuit is equipped with a non-inverting circuit for outputting the input AC signal without changing its phase, the non-inverting circuit being inserted in a part of the feedback loop formed by the two cascaded circuits, Wherein the circuit passes only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 27. The method of claim 26, Wherein the tuning circuit is provided with a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 180. by the entirety of two or more circuits connected in cascade. 27. The method of claim 26, And a flow circuit is inserted by a transistor at the front end of the two or more cascaded circuits. 27. The method of claim 26, Wherein a partial voltage circuit is inserted into a part of a feedback loop formed by the two or more cascade-connected cascaded circuits, and the tuning circuit outputs an alternating signal inputted to the voltage dividing circuit as a tuning signal. 27. The method of claim 26, Wherein the first resistor in the series circuit is formed by a variable resistor and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor according to the voltage level of the control signal. 27. The method of claim 26, Wherein the differential amplifier is an operational amplifier. 27. The method of claim 26, And the component parts are integrally formed on the semiconductor substrate. The method of claim 3, Wherein the tuning circuit has a non-inverting circuit for outputting the input AC signal without changing its phase, the non-inverting circuit being inserted into a part of the feedback loop formed by the two cascaded circuits, At least one of the two or more circuits further comprises: conversion means for converting the input AC signal into an in-phase and reverse-phase AC signal and outputting the converted AC signal; And a synthesizing means for synthesizing the AC signal on the other side of the series circuit through the other end of the series circuit. 35. The method of claim 34, Wherein the tuning circuit passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 35. The method of claim 34, And a voltage dividing circuit is inserted in a part of the feedback loops formed by the cascade-connected two-phase circuit and the non-inverting circuit, and the tuning circuit outputs an AC signal input to the voltage dividing circuit as a tuning signal Tuning control method. 35. The method of claim 34, Wherein said switching means in said at least two circuits comprises a transistor and a second resistor having substantially the same resistance value is connected to the source and the drain or the emitter and the collector of said transistor and an AC signal is applied to the gate or base of said transistor And the series circuit constituting the synthesizing means is connected between the source, drain or emitter of the transistor. 35. The method of claim 34, Wherein the first resistor in the series circuit is formed by a variable resistor and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor according to the voltage level of the control signal. 35. The method of claim 34, Wherein the component parts are integrally formed on a semiconductor substrate. The method of claim 3, Wherein the tuning circuit comprises a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, At least one of the two or more circuits further comprises: conversion means for converting the input AC signal into an in-phase and reverse-phase AC signal and outputting the converted AC signal; And a synthesizing means for synthesizing the AC signal on the other side of the series circuit through the other end of the series circuit. 41. The method of claim 40, Wherein the tuning circuit passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 180. The tuning control method according to claim 1, 41. The method of claim 40, A voltage dividing circuit is inserted in a part of the feedback loop formed by the cascade-connected two-phase circuit and the phase inversion circuit, and the tuning circuit outputs the AC signal input to the voltage dividing circuit as a tuning signal Tuning control method. 41. The method of claim 40, A second resistor having substantially the same resistance value is connected to the source and the drain of the transistor, the emitter and the collector of the transistor, and the alternating current signal And the series circuit constituting the synthesizing means is connected between the source, drain or emitter of the transistor. 41. The method of claim 40, Wherein the first resistor in the series circuit is formed by a variable resistor and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor in accordance with the voltage level of the control signal. 41. The method of claim 40, And the component parts are integrally formed on the semiconductor substrate. The method of claim 3, At least one of the two abnormal circuits included in the tuning circuit includes a first voltage dividing circuit configured by second and third resistors having substantially the same resistance value, And a differential amplifier for amplifying and outputting a difference between the potential of the connection point of the reactance element and the first resistor which is connected to the first resistor and the potential of the connection point of the first resistor and the first resistor, Tuning control method characterized by. 47. The method of claim 46, Wherein the tuning circuit has a non-inverting circuit for outputting the input AC signal without changing its phase, the non-inverting circuit being inserted into a part of the feedback loop formed by the two cascaded circuits, Wherein the tuning circuit passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 47. The method of claim 46, Wherein the tuning circuit has a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Wherein the tuning circuit passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 180. The tuning control method according to claim 1, 47. The method of claim 46, A second voltage division circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Wherein the tuning circuit outputs an AC signal input to the second voltage dividing circuit as a tuning signal. 47. The method of claim 46, Wherein the first resistor in the series circuit is formed by a variable resistor and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor according to the voltage level of the control signal. 47. The method of claim 46, And the component parts are integrally formed on the semiconductor substrate. The method of claim 3, Wherein the tuning circuit includes an input impedance element in which an input signal is inputted at one end and a feedback impedance element in which a feedback signal is inputted at one end, and the addition circuit adds the input signal inputted through the input impedance element and the feedback And said adder circuit adds said feedback signal inputted through an infinite divider. 53. The method of claim 52, Wherein the bandwidth of the tuning circuit is changed by changing the ratio of the element constants of the input impedance element and the feedback impedance element.