KR19980081092A - 집적 회로용 테스트 소자의 인터페이스 회로 및 테스트 신호의선택적 인가 방법 - Google Patents
집적 회로용 테스트 소자의 인터페이스 회로 및 테스트 신호의선택적 인가 방법 Download PDFInfo
- Publication number
- KR19980081092A KR19980081092A KR1019980011964A KR19980011964A KR19980081092A KR 19980081092 A KR19980081092 A KR 19980081092A KR 1019980011964 A KR1019980011964 A KR 1019980011964A KR 19980011964 A KR19980011964 A KR 19980011964A KR 19980081092 A KR19980081092 A KR 19980081092A
- Authority
- KR
- South Korea
- Prior art keywords
- test
- transistor
- input
- output line
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims description 28
- 230000006870 function Effects 0.000 claims description 15
- 230000004044 response Effects 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229920005994 diacetyl cellulose Polymers 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000275 quality assurance Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31924—Voltage or current aspects, e.g. driver, receiver
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/833,412 US5844913A (en) | 1997-04-04 | 1997-04-04 | Current mode interface circuitry for an IC test device |
| US8/833,412 | 1997-04-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980081092A true KR19980081092A (ko) | 1998-11-25 |
Family
ID=25264342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980011964A Withdrawn KR19980081092A (ko) | 1997-04-04 | 1998-04-04 | 집적 회로용 테스트 소자의 인터페이스 회로 및 테스트 신호의선택적 인가 방법 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5844913A (enExample) |
| JP (1) | JPH116865A (enExample) |
| KR (1) | KR19980081092A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100918221B1 (ko) * | 2006-09-28 | 2009-09-21 | 요코가와 덴키 가부시키가이샤 | 반도체 테스트 시스템 |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10223000A (ja) * | 1997-02-04 | 1998-08-21 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6289292B1 (en) * | 1997-10-28 | 2001-09-11 | Micron Technology, Inc. | System for identifying a component with physical characterization |
| US6161052A (en) * | 1997-10-28 | 2000-12-12 | Micron Electronics, Inc. | Method for identifying a component with physical characterization |
| US6028438A (en) * | 1997-10-31 | 2000-02-22 | Credence Systems Corporation | Current sense circuit |
| US6064224A (en) * | 1998-07-31 | 2000-05-16 | Hewlett--Packard Company | Calibration sharing for CMOS output driver |
| US6324485B1 (en) * | 1999-01-26 | 2001-11-27 | Newmillennia Solutions, Inc. | Application specific automated test equipment system for testing integrated circuit devices in a native environment |
| US6546507B1 (en) | 1999-08-31 | 2003-04-08 | Sun Microsystems, Inc. | Method and apparatus for operational envelope testing of busses to identify halt limits |
| US6502212B1 (en) * | 1999-08-31 | 2002-12-31 | Sun Microsystems, Inc. | Method and apparatus for bus parameter optimization using probes of system configurations |
| US6609221B1 (en) | 1999-08-31 | 2003-08-19 | Sun Microsystems, Inc. | Method and apparatus for inducing bus saturation during operational testing of busses using a pattern generator |
| KR100723463B1 (ko) * | 1999-12-24 | 2007-05-30 | 삼성전자주식회사 | 디지털 가변 저항 및 이를 구비하는 디지털 위상 합성기 |
| US6292010B1 (en) | 2000-02-02 | 2001-09-18 | Teradyne, Inc. | Dynamic pin driver combining high voltage mode and high speed mode |
| US6760857B1 (en) * | 2000-02-18 | 2004-07-06 | Rambus Inc. | System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively |
| US6545522B2 (en) * | 2001-05-17 | 2003-04-08 | Intel Corporation | Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting |
| US6982587B2 (en) * | 2002-07-12 | 2006-01-03 | Rambus Inc. | Equalizing transceiver with reduced parasitic capacitance |
| KR100532447B1 (ko) * | 2003-07-11 | 2005-11-30 | 삼성전자주식회사 | 높은 테스트 전류 주입이 가능한 집적 회로 소자의 병렬테스트 장치 및 방법 |
| US7102375B2 (en) * | 2004-12-23 | 2006-09-05 | Teradyne, Inc. | Pin electronics with high voltage functionality |
| US20070024291A1 (en) * | 2005-07-29 | 2007-02-01 | Persons Thomas W | Programmable pin electronics driver |
| KR100690275B1 (ko) * | 2006-01-31 | 2007-03-12 | 삼성전자주식회사 | 테스트 모드에서 전압모드로 동작하는 전류모드 반도체집적회로장치 |
| DE102006051135B4 (de) * | 2006-10-30 | 2016-11-17 | Polaris Innovations Ltd. | Test-Verfahren, sowie Halbleiter-Bauelement, insbesondere Daten-Zwischenspeicher-Bauelement |
| US7848899B2 (en) * | 2008-06-09 | 2010-12-07 | Kingtiger Technology (Canada) Inc. | Systems and methods for testing integrated circuit devices |
| US7928716B2 (en) * | 2008-12-30 | 2011-04-19 | Intel Corporation | Power supply modulation |
| US8356215B2 (en) * | 2010-01-19 | 2013-01-15 | Kingtiger Technology (Canada) Inc. | Testing apparatus and method for analyzing a memory module operating within an application system |
| JP5496859B2 (ja) * | 2010-11-16 | 2014-05-21 | 新電元工業株式会社 | 高圧パルス発生装置 |
| US8724408B2 (en) | 2011-11-29 | 2014-05-13 | Kingtiger Technology (Canada) Inc. | Systems and methods for testing and assembling memory modules |
| US9117552B2 (en) | 2012-08-28 | 2015-08-25 | Kingtiger Technology(Canada), Inc. | Systems and methods for testing memory |
| US8872546B2 (en) | 2012-09-13 | 2014-10-28 | Intel Corporation | Interface circuitry for a test apparatus |
| WO2016044849A1 (en) * | 2014-09-19 | 2016-03-24 | Elevate Semiconductor, Inc. | Parametric pin measurement unit high voltage extension |
| KR20160104845A (ko) * | 2015-02-26 | 2016-09-06 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| US11320480B1 (en) * | 2016-01-22 | 2022-05-03 | Albert Gaoiran | Scalable tester for testing multiple devices under test |
| US10831938B1 (en) * | 2019-08-14 | 2020-11-10 | International Business Machines Corporation | Parallel power down processing of integrated circuit design |
| KR20230030436A (ko) * | 2021-08-25 | 2023-03-06 | 삼성전자주식회사 | 모니터링 회로, 모니터링 회로를 포함하는 집적 회로 및 모니터링 회로의 동작 방법 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0750159B2 (ja) * | 1985-10-11 | 1995-05-31 | 株式会社日立製作所 | テストパタ−ン発生装置 |
| FR2594553B1 (fr) * | 1985-10-16 | 1989-02-03 | Bendix Electronics Sa | Interface de test pour circuit integre en technologie mos |
| JPH04177700A (ja) * | 1990-11-13 | 1992-06-24 | Toshiba Corp | メモリ不良解析装置 |
| US5101153A (en) * | 1991-01-09 | 1992-03-31 | National Semiconductor Corporation | Pin electronics test circuit for IC device testing |
| US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
| US5250854A (en) * | 1991-11-19 | 1993-10-05 | Integrated Device Technology, Inc. | Bitline pull-up circuit operable in a low-resistance test mode |
| US5355391A (en) * | 1992-03-06 | 1994-10-11 | Rambus, Inc. | High speed bus system |
| US5254883A (en) * | 1992-04-22 | 1993-10-19 | Rambus, Inc. | Electrical current source circuitry for a bus |
| US5268639A (en) * | 1992-06-05 | 1993-12-07 | Rambus, Inc. | Testing timing parameters of high speed integrated circuit devices |
-
1997
- 1997-04-04 US US08/833,412 patent/US5844913A/en not_active Expired - Fee Related
-
1998
- 1998-04-01 JP JP10088797A patent/JPH116865A/ja active Pending
- 1998-04-04 KR KR1019980011964A patent/KR19980081092A/ko not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100918221B1 (ko) * | 2006-09-28 | 2009-09-21 | 요코가와 덴키 가부시키가이샤 | 반도체 테스트 시스템 |
Also Published As
| Publication number | Publication date |
|---|---|
| US5844913A (en) | 1998-12-01 |
| JPH116865A (ja) | 1999-01-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19980404 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |