KR19980037653A - Contact formation method of semiconductor device - Google Patents
Contact formation method of semiconductor device Download PDFInfo
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- KR19980037653A KR19980037653A KR1019960056443A KR19960056443A KR19980037653A KR 19980037653 A KR19980037653 A KR 19980037653A KR 1019960056443 A KR1019960056443 A KR 1019960056443A KR 19960056443 A KR19960056443 A KR 19960056443A KR 19980037653 A KR19980037653 A KR 19980037653A
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- forming
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- metal layer
- conductive layer
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title abstract description 26
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims description 48
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 239000007789 gas Substances 0.000 description 11
- 210000002381 plasma Anatomy 0.000 description 11
- 229920000642 polymer Polymers 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 콘택(Contact) 형성방법에 관한 것으로 특히, 포토 레지스트 패턴(Photo Resist Pattern) 형성에 마진(Margin)을 향상시키도록 한 반도체 소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact of a semiconductor device, and more particularly, to a method of forming a contact of a semiconductor device to improve a margin in forming a photo resist pattern.
이와같은 본 발명은 반도체 소자의 콘택 형성방법은 기판을 준비하는 단계; 상기 기판상에 절연막을 형성하는 단계; 상기 절연막의 표면이 일정부분 노출되도록 제1도전층 패턴을 형성하는 단계; 상기 제1도전층 패턴을 마스크로 상기 절연막을 선택적으로 제거하여 상기 기판의 표면이 소정부분 노출되도록 콘택홀을 형성하는 단계; 그리고 상기 콘택홀 내부에 제2도전층 콘택을 형성하는 단계를 포함하여 특징으로 한다.Such a method of forming a contact of a semiconductor device comprises the steps of preparing a substrate; Forming an insulating film on the substrate; Forming a first conductive layer pattern such that a surface of the insulating layer is partially exposed; Selectively removing the insulating layer using the first conductive layer pattern as a mask to form a contact hole to expose a predetermined portion of the surface of the substrate; And forming a second conductive layer contact inside the contact hole.
Description
본 발명은 반도체 소자의 콘택(Contact) 형성방법에 관한 것으로 특히, 포토레지스트 패턴(Photo Resist Pattern) 형성에 마진(Margin)을 향상시키도록 한 반도체 소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact of a semiconductor device, and more particularly, to a method of forming a contact of a semiconductor device to improve a margin in forming a photoresist pattern.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 콘택 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a-도 1e는 종래의 반도체 소자의 콘택 형성방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.
도 1a에 도시된 바와같이 반도체 기판(11)상에 절연막(12)을 형성하고, 상기 절연막(12)상에 제1감광막(Photo Resist)(13)을 도포한 후, 노광 및 현상공정으로 패터닝(Patternign)한다.As shown in FIG. 1A, an insulating film 12 is formed on the semiconductor substrate 11, and a first photoresist film 13 is coated on the insulating film 12, and then patterned by an exposure and development process. (Patternign)
도 1b에 도시된 바와 같이 패터닝된 제1감광막(13)을 마스크로 -10℃~+10℃정도의 저온에서 CF4, CHF3, Ar 등의 가스(Gas)를 이용한 플라즈마(Plasma)로 상기 절연막(12)을 건식식각(Dry Etch) 공정에 의해 선택적으로 제거하므로써 상기 반도체 기판(11) 표면의 소정부분을 노출시켜 콘택홀(14)을 형성한다.As shown in FIG. 1B, the patterned first photoresist layer 13 is used as a mask at a low temperature of about −10 ° C. to + 10 ° C. as a plasma using a gas such as CF 4 , CHF 3 , Ar, or the like. By selectively removing the insulating layer 12 by a dry etching process, the contact hole 14 is formed by exposing a predetermined portion of the surface of the semiconductor substrate 11.
이어서, 상기 패터닝된 제1감광막(13) 마스크로 하여 상기 절연막(12)을 제거시 제1감광막(13)성분에 의해 폴리머(Polymer)가 발생하는데 상기 폴리머를 제거하기 위해 초산, 암모니아, 물의 혼합 용액이나 NH4OH, H2O2, H2O의 혼합 용액으로 제거한다.Subsequently, when the insulating layer 12 is removed using the patterned first photoresist layer 13, a polymer is generated by the first photoresist layer 13 component. In order to remove the polymer, a mixture of acetic acid, ammonia and water is used. Remove with a solution or a mixed solution of NH 4 OH, H 2 O 2 , H 2 O.
도 1c에 도시된 바와 같이 O2와 N2가스를 이용한 플라즈마로 상기 제1감광막(13)을 제거하고, 상기 콘택홀(14)을 포함한 전면에 베리어(Barrier)용 제1금속층(15) 및 콘택용 제2금속층(16)을 형성한다.As shown in FIG. 1C, the first photosensitive layer 13 is removed by a plasma using O 2 and N 2 gases, and a first metal layer 15 for a barrier is formed on the entire surface including the contact hole 14. The second metal layer 16 for contact is formed.
도 1d에 도시된 바와 같이 상기 제2금속층(16)을 10℃-40℃ 정도의 온도에서 SF6, Ar, O2가스를 이용한 플라즈마로 에치백(Etch Back) 공정을 실시하여 상기 콘택홀(14)내부에 제2금속층 콘택(16a)을 형성한다.As shown in FIG. 1D, the second metal layer 16 is subjected to an etch back process using a plasma using SF 6 , Ar, and O 2 gas at a temperature of about 10 ° C.-40 ° C. 14) A second metal layer contact 16a is formed inside.
이어, 상기 제2금속층 콘택(16a)을 포함한 전면에 금속배선용 제3금속층(17) 및 베리어용 제4금속층(18)을 형성한다. 그리고 상기 제4금속층(18)상에 제2감광막(19)을 도포한 후, 노광 및 현상공정으로 패터닝한다.Subsequently, a third metal layer 17 for wiring and a fourth metal layer 18 for barrier are formed on the entire surface including the second metal layer contact 16a. The second photoresist film 19 is coated on the fourth metal layer 18, and then patterned by exposure and development processes.
도 1e에 도시된 바와같이 상기 패터닝된 제2감광막(19)을 마스크로 BCl3와 Cl2가스를 혼용한 플라즈마를 이용하여 건식식각 공정으로 상기 제4금속층(18) 및 제3금속층(17)을 선택적으로 제거하므로써 금속배선을 형성하고, 상기 제2감광막(19)을 제거한다.As shown in FIG. 1E, the fourth metal layer 18 and the third metal layer 17 are subjected to a dry etching process using a plasma in which BCl 3 and Cl 2 gas are mixed using the patterned second photoresist layer 19 as a mask. Is selectively removed to form metal wiring, and the second photosensitive film 19 is removed.
그러나 상기와 같은 종래의 반도체 소자의 콘택 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a contact of a semiconductor device has the following problems.
즉, 감광막을 마스크로 절연막을 선택적으로 제거하여 콘택홀을 형성할 때 폴리머(Polymer)의 형성에 의하여 콘택홀을 막히고, 폴리머를 제거하기 위한 공정을 진행하고 콘택(Contact)을 형성하므로 공정이 복잡하다.That is, when forming the contact hole by selectively removing the insulating film using a photoresist mask as a mask, the contact hole is blocked by the formation of a polymer, the process of removing the polymer, and the contact is formed, which makes the process complicated. Do.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 폴리머의 형성을 방지하도록 한 반도체 소자의 콘택 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact of a semiconductor device to prevent the formation of a polymer to solve the above problems.
도 1a-도 1e는 종래의 반도체 소자의 콘택 형성방법을 나타낸 공정단면도.1A to 1E are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.
도 2a-도 2d는 본 발명의 제1실시예에 따른 반도체 소자의 콘택 형성방법을 나타낸 공정단면도.2A to 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to a first embodiment of the present invention.
도 3a-도 3e는 본 발명의 제2실시예에 따른 반도체 소자의 콘택 형성방법을 나타낸 공정단면도.3A to 3E are cross-sectional views illustrating a method of forming a contact for a semiconductor device according to a second exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21, 31:반도체 기판22, 32:절연막21, 31: semiconductor substrate 22, 32: insulating film
23, 33:제1금속층24, 34:제2금속층23, 33: first metal layer 24, 34: second metal layer
25, 36, 39:감광막35: 제3금속층25, 36, 39: photosensitive film 35: third metal layer
37:콘택홀38:제4금속층37: contact hole 38: the fourth metal layer
23a, 38a:금속층 콘택23a, 38a: metal layer contact
상기와 같은 목적을 달성하기 위한 본 발명의 제1실시예에 따른 반도체 소자의 콘택 형성방법은 기판을 준비하는 단계; 상기 기판상에 절연막을 형성하는 단계; 상기 절연막의 표면이 일정부분 노출되도록 제1도전층 패턴을 형성하는 단계; 상기 제1도전층 패턴을 마스크로 상기 절연막을 선택적으로 제거하여 상기 기판의 표면이 소정부분 노출되도록 콘택홀을 형성하는 단계; 그리고 상기 콘택홀 내부에 제2도전층 코택을 형성하는 단계를 포함하여 형성하며, 본 발명의 제2실시예에 따른 반도체 소자의 콘택 형성방법은 기판을 준비하는 단계; 상기 기판상에 절연막 및 제1, 제2, 제3 도전층을 차례로 형성하는 단계; 상기 절연막의 표면일 질정부분 노출되도록 제1, 제2, 제3도전층을 선택적으로 제거하는 단계; 상기 제1, 제2, 제3도전층을 마스크로 상기 절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 내부에 제4도전층 콘택을 형성하는 단계; 그리고 상기 제4도전층 패턴을 포함하고 상기 절연막의 표면이 노출되도록 상기 제3, 제2 제1금속층을 선택적으로 제거하는 단계를 포함하여 형성함을 특징으로 한다.According to a first aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method including: preparing a substrate; Forming an insulating film on the substrate; Forming a first conductive layer pattern such that a surface of the insulating layer is partially exposed; Selectively removing the insulating layer using the first conductive layer pattern as a mask to form a contact hole to expose a predetermined portion of the surface of the substrate; And forming a second conductive layer contact inside the contact hole. The method of forming a contact of a semiconductor device according to a second embodiment of the present invention includes preparing a substrate; Sequentially forming an insulating film and first, second, and third conductive layers on the substrate; Selectively removing the first, second, and third conductive layers so as to expose the surface of the insulating film; Forming a contact hole by selectively etching the insulating layer using the first, second and third conductive layers as a mask; Forming a fourth conductive layer contact in the contact hole; And removing the third and second first metal layers to include the fourth conductive layer pattern and expose the surface of the insulating layer.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 콘택 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a-도 2d는 본 발명의 제1실시예에 따른 반도체 소자의 콘택 형성방법을 나타낸 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a contact in a semiconductor device according to a first embodiment of the present invention.
도 2a에 도시된 바와 같이 반도체 기판(2)상에 절연막(22)을 형성하고, 상기 절연막(22)상에 제1금속층(23)을 형성한다. 이어, 상기 제1금속층(23)상에 감광막(24)을 도포한 후, 노광 및 현상공정으로 패터닝(Patterning)한다.As shown in FIG. 2A, an insulating film 22 is formed on the semiconductor substrate 2, and a first metal layer 23 is formed on the insulating film 22. Subsequently, the photosensitive film 24 is coated on the first metal layer 23, and then patterned by exposure and development processes.
도 2b에 도시된 바와 같이 상기 패터닝된 감광막(24)을 마스크로 Cl2와 N2가스를 이용한 플라즈마(Plasma)로 건식식각(Dry Etch)하여 상기 제1금속층(23)으로 선택적으로 제거하여 제1금속층 패턴(23a)을 형성한다.As shown in FIG. 2B, the patterned photoresist 24 is dry etched by plasma using Cl 2 and N 2 gas as a mask, and selectively removed by the first metal layer 23. One metal layer pattern 23a is formed.
도 2c에 도시된 바와같이 상기 감광막(24)을 O2나 N2가스를 이용한 플라즈마로 제거하고, 상기 제1금속층 패턴(23a)을 마스크로 CH4, CHF3, Ar 등의 가스를 이용한 플라즈마로 건식식각하여 상기 절연막(22)을 선택적으로 제거하므로써 상기 반도체 기판(21)의 표면이 소정부분 노출되도록 콘택홀(25)을 형성한다.As shown in FIG. 2C, the photoresist layer 24 is removed using a plasma using O 2 or N 2 gas, and the plasma using a gas such as CH 4 , CHF 3 , or Ar is used as the mask as the first metal layer pattern 23a. The contact hole 25 is formed to expose a predetermined portion of the surface of the semiconductor substrate 21 by selectively etching the insulating film 22 by dry etching.
그리고 상기 콘택홀(25)을 포함한 전면에 제2금속층(26)을 형성한다.In addition, a second metal layer 26 is formed on the entire surface including the contact hole 25.
도 2d에 도시된 바와같이 상기 제2금속층(26)의 전면에 SF6, O2, Al 가스를 이용한 플라즈마로 에치백 공정을 실시하여 상기 콘택홀(25)의 내부에 제2금속층 콘택(26a)을 형성한다.As shown in FIG. 2D, an etch back process is performed on the entire surface of the second metal layer 26 using a plasma using SF 6 , O 2 , and Al gas to form a second metal layer contact 26 a inside the contact hole 25. ).
도 3a-도 3e는 본 발명의 제2실시예에 따른 반도체 소자의 콘택 형성방법을 나타낸 공정단면도이다.3A to 3E are cross-sectional views illustrating a method for forming a contact for a semiconductor device according to a second exemplary embodiment of the present invention.
도 3a에 도시된 바와같이 반도체 기판(31)상에 절연막(32) 및 베리어용 제1금속층(33)을 차례로 형성하고, 상기 제1금속층(33)상에 금소배선용 제2금속층(34) 및 베리어용 제3금속층(35)을 형성한다. 이어, 상기 제3금속층(35)상에 제1감광막(36)을 도포한 후, 노광 및 현상공정으로 패터닝한다.As shown in FIG. 3A, the insulating film 32 and the barrier first metal layer 33 are sequentially formed on the semiconductor substrate 31, and the second metal layer 34 for metal wiring is formed on the first metal layer 33. The barrier third metal layer 35 is formed. Subsequently, the first photoresist film 36 is coated on the third metal layer 35, and then patterned by exposure and development processes.
도 3b에 도시된 바와 같이 패터닝된 제1감광막(36)을 마스크로 BCl3와 Cl2가스를 혼용한 플라즈마를 이용하여 건식식각 공정으로 상기 절연막(32)의 표면이 소정부분 노출되도록 상기 제3금속층(35) 및 제2금속층(34) 그리고 제1금속층(33)을 선택적으로 제거한다.As shown in FIG. 3B, the surface of the insulating layer 32 is exposed by a dry etching process using a plasma mixed with BCl 3 and Cl 2 gas using the patterned first photoresist layer 36 as a mask. The metal layer 35, the second metal layer 34, and the first metal layer 33 are selectively removed.
도 3c에 도시된 바와같이 상기 제1감광막(36)을 제거하고, 상기 잔존하는 제3금속층(35) 및 제2금속층(34) 그리고 제1금속층(33)을 마스크로 CHF3와 CF4가스를 혼용한 플라즈마를 이용하여 건식식각 하면 높은 선택비로 상기 절연막(32)을 선택적으로 제거하여 상기 반도체 기판(31)의 표면이 소정부분 노출되도록 콘택홀(37)을 형성한다.As shown in FIG. 3C, the first photosensitive layer 36 is removed, and the remaining third metal layer 35, the second metal layer 34, and the first metal layer 33 are masked with CHF 3 and CF 4 gases. When dry etching is performed using a mixed plasma, the contact hole 37 is formed to selectively expose the surface of the semiconductor substrate 31 by selectively removing the insulating layer 32 at a high selectivity.
이어, 상기 콘택홀(37)을 포함한 전면에 CVD(Chemical Vapor Deposition)법으로 콘택용 제4금속층(38)을 형성한다.Subsequently, a fourth metal layer 38 for contact is formed on the entire surface including the contact hole 37 by CVD (Chemical Vapor Deposition).
도 3d에 도시된 바와같이 상기 제4금속층(38)의 전면에 SF6와 Ar 가스를 플라즈마로 사용하여 건식식각하여 상기 콘택홀(37)내부에 제4금속층 콘택(38a)을 형성한다. 이어, 상기 제4금속층 콘택(38a)을 포함한 전면에 제2감광막(39)을 도포한 후, 노광 및 현상공정으로 패터닝한다.As shown in FIG. 3D, the fourth metal layer contact 38a is formed inside the contact hole 37 by dry etching using SF 6 and Ar gas as plasmas on the entire surface of the fourth metal layer 38. Subsequently, the second photoresist film 39 is coated on the entire surface including the fourth metal layer contact 38a and then patterned by an exposure and development process.
도 3e에 도시된 바와같이 상기 패터닝된 제2감광막(39)을 마스크로 상기 절연막(32)의 표면이 노출되도록 상기 제3금속층(35) 및 제2금속층(34) 그리고 제1금속층(33)을 선택적으로 제거하고, 상기 제2감광막(39)을 제거한다.As shown in FIG. 3E, the third metal layer 35, the second metal layer 34, and the first metal layer 33 are exposed to expose the surface of the insulating layer 32 using the patterned second photoresist layer 39 as a mask. Is selectively removed, and the second photosensitive film 39 is removed.
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 콘택홀 형성방법에 있어서 감광막을 마스크로 콘택홀을 형성하지 않고 금속층을 마스크로 콘택홀을 형성하기 때문에 폴리머가 형성되지 않아 폴리머 제거를 위한 공정이 생략되므로 공정이 간소한 효과가 있다.As described above, in the method for forming a contact hole of the semiconductor device of the present invention, since a contact hole is formed using a metal layer as a mask without forming a contact hole as a mask, a polymer is not formed and a process for removing the polymer is omitted. The process has a simple effect.
Claims (5)
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| KR1019960056443A KR100209709B1 (en) | 1996-11-22 | 1996-11-22 | Method for forming a contact of a semiconductor device |
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| KR1019960056443A KR100209709B1 (en) | 1996-11-22 | 1996-11-22 | Method for forming a contact of a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100807082B1 (en) * | 2001-12-29 | 2008-02-25 | 주식회사 하이닉스반도체 | Method of forming a contact in a semiconductor device |
| KR100894763B1 (en) * | 2002-10-21 | 2009-04-24 | 매그나칩 반도체 유한회사 | Method for reducing plasama charging damage and Method of forming a dual damascene pattern using the same |
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1996
- 1996-11-22 KR KR1019960056443A patent/KR100209709B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100807082B1 (en) * | 2001-12-29 | 2008-02-25 | 주식회사 하이닉스반도체 | Method of forming a contact in a semiconductor device |
| KR100894763B1 (en) * | 2002-10-21 | 2009-04-24 | 매그나칩 반도체 유한회사 | Method for reducing plasama charging damage and Method of forming a dual damascene pattern using the same |
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| KR100209709B1 (en) | 1999-07-15 |
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