KR102839966B1 - 칩 부착 기판의 제조 방법, 및 기판 처리 장치 - Google Patents

칩 부착 기판의 제조 방법, 및 기판 처리 장치

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Publication number
KR102839966B1
KR102839966B1 KR1020227017319A KR20227017319A KR102839966B1 KR 102839966 B1 KR102839966 B1 KR 102839966B1 KR 1020227017319 A KR1020227017319 A KR 1020227017319A KR 20227017319 A KR20227017319 A KR 20227017319A KR 102839966 B1 KR102839966 B1 KR 102839966B1
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KR
South Korea
Prior art keywords
substrate
chips
bonding
chip
bonded
Prior art date
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Active
Application number
KR1020227017319A
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English (en)
Korean (ko)
Other versions
KR20220091511A (ko
Inventor
하야토 타노우에
야스타카 미조모토
요헤이 야마시타
Original Assignee
도쿄엘렉트론가부시키가이샤
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Priority to KR1020257025004A priority Critical patent/KR20250121140A/ko
Publication of KR20220091511A publication Critical patent/KR20220091511A/ko
Application granted granted Critical
Publication of KR102839966B1 publication Critical patent/KR102839966B1/ko
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H01L25/50—
    • H01L21/304—
    • H01L21/31051—
    • H01L21/67121—
    • H01L21/67703—
    • H01L24/799—
    • H01L24/83—
    • H01L24/98—
    • H01L25/0655—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0436—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
    • H10P72/32—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations
    • H10P72/3212—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips or lead frames
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7448—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H01L2224/7999—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7408—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including alignment aids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Manufacturing & Machinery (AREA)
  • Engineering & Computer Science (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Die Bonding (AREA)
KR1020227017319A 2019-10-29 2020-09-03 칩 부착 기판의 제조 방법, 및 기판 처리 장치 Active KR102839966B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020257025004A KR20250121140A (ko) 2019-10-29 2020-09-03 칩 부착 기판의 제조 방법

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019196386 2019-10-29
JPJP-P-2019-196386 2019-10-29
PCT/JP2020/033410 WO2021084902A1 (ja) 2019-10-29 2020-09-03 チップ付き基板の製造方法、及び基板処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020257025004A Division KR20250121140A (ko) 2019-10-29 2020-09-03 칩 부착 기판의 제조 방법

Publications (2)

Publication Number Publication Date
KR20220091511A KR20220091511A (ko) 2022-06-30
KR102839966B1 true KR102839966B1 (ko) 2025-07-29

Family

ID=75714631

Family Applications (2)

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KR1020227017319A Active KR102839966B1 (ko) 2019-10-29 2020-09-03 칩 부착 기판의 제조 방법, 및 기판 처리 장치
KR1020257025004A Pending KR20250121140A (ko) 2019-10-29 2020-09-03 칩 부착 기판의 제조 방법

Family Applications After (1)

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Country Status (6)

Country Link
US (1) US12543522B2 (https=)
JP (1) JP7330284B2 (https=)
KR (2) KR102839966B1 (https=)
CN (2) CN121123034A (https=)
TW (1) TWI874441B (https=)
WO (1) WO2021084902A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI874441B (zh) * 2019-10-29 2025-03-01 日商東京威力科創股份有限公司 附有晶片之基板的製造方法及基板處理裝置
KR20240016994A (ko) * 2021-06-03 2024-02-06 도쿄엘렉트론가부시키가이샤 기판 처리 방법
JP7690038B2 (ja) * 2021-09-06 2025-06-09 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US12610845B2 (en) * 2022-04-22 2026-04-21 Tokyo Electron Limited Method for forming semiconductor packages using dielectric alignment marks and laser liftoff process
US20240178180A1 (en) * 2022-11-30 2024-05-30 Tokyo Electron Limited Systems and methods for bonding semiconductor devices
KR102853614B1 (ko) * 2024-08-07 2025-09-04 (주)에이치아이티에스 칩 본딩 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190035688A1 (en) * 2017-07-26 2019-01-31 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340251A (ja) * 1991-02-07 1992-11-26 Fujitsu Ltd 半導体装置の製造方法
JP4389447B2 (ja) * 2003-01-28 2009-12-24 セイコーエプソン株式会社 電気光学装置の製造方法
JP2004288689A (ja) * 2003-03-19 2004-10-14 Matsushita Electric Ind Co Ltd 電子部品製造方法および電子部品の集合体の製造方法
KR20070018713A (ko) * 2005-08-10 2007-02-14 가부시끼가이샤 르네사스 테크놀로지 반도체 장치의 제조 방법 및 반도체 장치
JP5389490B2 (ja) * 2009-03-23 2014-01-15 東京エレクトロン株式会社 三次元集積回路の製造方法及び装置
JP2011049210A (ja) 2009-08-25 2011-03-10 Seiko Epson Corp 薄膜素子群の転写方法
JP6149277B2 (ja) * 2011-03-30 2017-06-21 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
JP2013182972A (ja) 2012-03-01 2013-09-12 Tokyo Electron Ltd 基板の接合方法及び半導体装置
JP6008940B2 (ja) * 2012-03-13 2016-10-19 シチズンホールディングス株式会社 半導体発光装置及びその製造方法
JP2015046569A (ja) 2013-07-31 2015-03-12 マイクロン テクノロジー， インク． 半導体装置の製造方法
JP6145061B2 (ja) * 2014-03-04 2017-06-07 東京エレクトロン株式会社 接合システムおよび接合方法
JP6300420B2 (ja) * 2014-09-26 2018-03-28 ルネサスエレクトロニクス株式会社 電子装置
KR102413733B1 (ko) * 2016-06-28 2022-06-27 린텍 가부시키가이샤 정렬 지그, 정렬 방법 및 전착 방법
CN106601657B (zh) * 2016-12-12 2019-12-17 厦门市三安光电科技有限公司 微元件的转移系统、转移方法、制造方法、装置和电子设备
CN118737998A (zh) * 2017-03-02 2024-10-01 Ev 集团 E·索尔纳有限责任公司 用于键合芯片的方法和装置
US10403537B2 (en) * 2017-03-10 2019-09-03 Facebook Technologies, Llc Inorganic light emitting diode (ILED) assembly via direct bonding
TWI653694B (zh) * 2017-09-13 2019-03-11 英屬開曼群島商錼創科技股份有限公司 微型發光元件陣列製造方法、轉移載板以及微型發光元件陣列
JP6973927B2 (ja) * 2017-10-24 2021-12-01 株式会社ディスコ チップの製造方法
KR102515684B1 (ko) * 2017-11-16 2023-03-30 린텍 가부시키가이샤 반도체 장치의 제조 방법
US10325791B1 (en) * 2017-12-13 2019-06-18 Facebook Technologies, Llc Formation of elastomeric layer on selective regions of light emitting device
US11227812B2 (en) * 2019-08-28 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method thereof
US11264343B2 (en) * 2019-08-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for semiconductor device and method of forming same
US11557581B2 (en) * 2019-09-23 2023-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US12080672B2 (en) * 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11094672B2 (en) * 2019-09-27 2021-08-17 Intel Corporation Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
TWI874441B (zh) * 2019-10-29 2025-03-01 日商東京威力科創股份有限公司 附有晶片之基板的製造方法及基板處理裝置
US11804469B2 (en) * 2020-05-07 2023-10-31 Invensas Llc Active bridging apparatus
US11631647B2 (en) * 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
CN114597138A (zh) * 2020-12-03 2022-06-07 群创光电股份有限公司 半导体封装的制造方法
US12125820B2 (en) * 2021-02-12 2024-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Through-dielectric vias for direct connection and method forming same
US11664315B2 (en) * 2021-03-11 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure with interconnection die and method of making same
JP2022170858A (ja) * 2021-04-30 2022-11-11 シャープ株式会社 マイクロｌｅｄ実装基板、マイクロｌｅｄディスプレイ及びマイクロｌｅｄ実装基板の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190035688A1 (en) * 2017-07-26 2019-01-31 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures

Also Published As

Publication number Publication date
TWI874441B (zh) 2025-03-01
US20220406603A1 (en) 2022-12-22
US12543522B2 (en) 2026-02-03
JP7330284B2 (ja) 2023-08-21
JPWO2021084902A1 (https=) 2021-05-06
TW202135276A (zh) 2021-09-16
WO2021084902A1 (ja) 2021-05-06
CN121123034A (zh) 2025-12-12
CN114586135A (zh) 2022-06-03
KR20220091511A (ko) 2022-06-30
TW202522760A (zh) 2025-06-01
KR20250121140A (ko) 2025-08-11
CN114586135B (zh) 2025-09-30

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