KR102781731B1 - 리세싱된 피처에서의 상향식 금속화 방법 - Google Patents
리세싱된 피처에서의 상향식 금속화 방법 Download PDFInfo
- Publication number
- KR102781731B1 KR102781731B1 KR1020227008755A KR20227008755A KR102781731B1 KR 102781731 B1 KR102781731 B1 KR 102781731B1 KR 1020227008755 A KR1020227008755 A KR 1020227008755A KR 20227008755 A KR20227008755 A KR 20227008755A KR 102781731 B1 KR102781731 B1 KR 102781731B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- layer
- substrate
- recess
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H01L21/743—
-
- H01L21/76843—
-
- H01L21/76865—
-
- H01L21/76877—
-
- H01L23/5286—
-
- H01L23/53242—
-
- H01L23/535—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
- H10W20/0595—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by using multiple deposition steps separated by etching steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/427—Power or ground buses
-
- H01L2221/1063—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
- H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
- H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962900794P | 2019-09-16 | 2019-09-16 | |
| US62/900,794 | 2019-09-16 | ||
| PCT/US2020/050962 WO2021055399A1 (en) | 2019-09-16 | 2020-09-16 | Method of bottom-up metallization in a recessed feature |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20220079526A KR20220079526A (ko) | 2022-06-13 |
| KR102781731B1 true KR102781731B1 (ko) | 2025-03-13 |
Family
ID=74868656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020227008755A Active KR102781731B1 (ko) | 2019-09-16 | 2020-09-16 | 리세싱된 피처에서의 상향식 금속화 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11450562B2 (https=) |
| JP (1) | JP7554538B2 (https=) |
| KR (1) | KR102781731B1 (https=) |
| CN (1) | CN114600232B (https=) |
| TW (1) | TWI857139B (https=) |
| WO (1) | WO2021055399A1 (https=) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10573522B2 (en) | 2016-08-16 | 2020-02-25 | Lam Research Corporation | Method for preventing line bending during metal fill process |
| KR20210081436A (ko) | 2018-11-19 | 2021-07-01 | 램 리써치 코포레이션 | 텅스텐을 위한 몰리브덴 템플릿들 |
| SG11202108217UA (en) | 2019-01-28 | 2021-08-30 | Lam Res Corp | Deposition of metal films |
| WO2021046058A1 (en) | 2019-09-03 | 2021-03-11 | Lam Research Corporation | Molybdenum deposition |
| CN114667600A (zh) | 2019-10-15 | 2022-06-24 | 朗姆研究公司 | 钼填充 |
| JP7686761B2 (ja) | 2021-02-23 | 2025-06-02 | ラム リサーチ コーポレーション | 3d-nand用の酸化物表面上へのモリブデン膜の堆積 |
| WO2022221210A1 (en) | 2021-04-14 | 2022-10-20 | Lam Research Corporation | Deposition of molybdenum |
| US12588475B2 (en) | 2021-05-14 | 2026-03-24 | Lam Research Corporation | High selectivity doped hardmask films |
| WO2023286192A1 (ja) * | 2021-07-14 | 2023-01-19 | 株式会社日立ハイテク | プラズマ処理方法 |
| US12394660B2 (en) | 2021-11-22 | 2025-08-19 | International Business Machines Corporation | Buried power rail after replacement metal gate |
| WO2023215135A1 (en) * | 2022-05-05 | 2023-11-09 | Lam Research Corporation | Molybdenum halides in memory applications |
| US12506029B2 (en) * | 2022-06-30 | 2025-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap filling method in semiconductor manufacturing process |
| US20240290655A1 (en) * | 2023-02-28 | 2024-08-29 | Applied Materials, Inc. | Selective via-fill with conformal sidewall coverage |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040197541A1 (en) * | 2001-08-02 | 2004-10-07 | Joseph Zahka | Selective electroless deposition and interconnects made therefrom |
| US20070190362A1 (en) * | 2005-09-08 | 2007-08-16 | Weidman Timothy W | Patterned electroless metallization processes for large area electronics |
| DE102007004884A1 (de) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht |
| KR101556238B1 (ko) * | 2009-02-17 | 2015-10-01 | 삼성전자주식회사 | 매립형 배선라인을 갖는 반도체 소자의 제조방법 |
| KR20120033640A (ko) | 2010-09-30 | 2012-04-09 | 주식회사 하이닉스반도체 | 텅스텐 갭필을 이용한 반도체장치 제조 방법 |
| KR101185990B1 (ko) * | 2010-12-20 | 2012-09-25 | 에스케이하이닉스 주식회사 | 반도체 소자의 형성방법 |
| JP5599350B2 (ja) * | 2011-03-29 | 2014-10-01 | 東京エレクトロン株式会社 | 成膜装置及び成膜方法 |
| WO2016204771A1 (en) * | 2015-06-18 | 2016-12-22 | Intel Corporation | Bottom-up fill (buf) of metal features for semiconductor structures |
| US10316406B2 (en) * | 2015-10-21 | 2019-06-11 | Ultratech, Inc. | Methods of forming an ALD-inhibiting layer using a self-assembled monolayer |
| EP3171409B1 (en) * | 2015-11-18 | 2020-12-30 | IMEC vzw | Method for forming a field effect transistor device having an electrical contact |
| KR102432719B1 (ko) * | 2015-12-23 | 2022-08-17 | 에스케이하이닉스 주식회사 | 매립금속게이트구조를 구비한 반도체장치 및 그 제조 방법, 그를 구비한 메모리셀, 그를 구비한 전자장치 |
| JP2018207110A (ja) * | 2017-06-06 | 2018-12-27 | 東京エレクトロン株式会社 | 二重金属電力レールを有する集積回路の製造方法 |
| US10453740B2 (en) * | 2017-06-29 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure without barrier layer on bottom surface of via |
| JP2019106538A (ja) * | 2017-12-07 | 2019-06-27 | マイクロマテリアルズ エルエルシー | 制御可能な金属およびバリアライナー凹部のための方法 |
| US20190198392A1 (en) * | 2017-12-22 | 2019-06-27 | Applied Materials, Inc. | Methods of etching a tungsten layer |
| US10546815B2 (en) * | 2018-05-31 | 2020-01-28 | International Business Machines Corporation | Low resistance interconnect structure with partial seed enhancement liner |
| US10573725B1 (en) * | 2018-09-20 | 2020-02-25 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| US11784091B2 (en) * | 2019-08-30 | 2023-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of chip package with fan-out feature |
-
2020
- 2020-09-15 US US17/021,586 patent/US11450562B2/en active Active
- 2020-09-16 CN CN202080064711.9A patent/CN114600232B/zh active Active
- 2020-09-16 JP JP2022514988A patent/JP7554538B2/ja active Active
- 2020-09-16 TW TW109131845A patent/TWI857139B/zh active
- 2020-09-16 KR KR1020227008755A patent/KR102781731B1/ko active Active
- 2020-09-16 WO PCT/US2020/050962 patent/WO2021055399A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US11450562B2 (en) | 2022-09-20 |
| TWI857139B (zh) | 2024-10-01 |
| CN114600232B (zh) | 2026-01-16 |
| JP7554538B2 (ja) | 2024-09-20 |
| TW202127521A (zh) | 2021-07-16 |
| US20210082750A1 (en) | 2021-03-18 |
| CN114600232A (zh) | 2022-06-07 |
| WO2021055399A1 (en) | 2021-03-25 |
| JP2022547126A (ja) | 2022-11-10 |
| KR20220079526A (ko) | 2022-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102781731B1 (ko) | 리세싱된 피처에서의 상향식 금속화 방법 | |
| TWI693687B (zh) | 三維記憶體裝置的字元線接觸結構及其製作方法 | |
| JP7192121B2 (ja) | 3次元メモリデバイスにおける階段構造の形成 | |
| CN113241350B (zh) | 存储器装置的阶梯结构 | |
| US9343405B2 (en) | Semiconductor device and method of manufacturing the same | |
| TWI464855B (zh) | 包括階梯結構之裝置及其形成之方法 | |
| JP5358848B2 (ja) | 削設構造の側壁に金属をパターニングする方法、及びメモリデバイスの製造方法 | |
| US11990367B2 (en) | Apparatus and memory device including conductive lines and contacts, and methods of forming an apparatus including conductive lines and contacts | |
| TW202017215A (zh) | 整合式晶片及其形成方法 | |
| US9024411B2 (en) | Conductor with sub-lithographic self-aligned 3D confinement | |
| US12052865B2 (en) | Three-dimensional memory devices with channel structures having plum blossom shape and methods for forming the same | |
| TW202143440A (zh) | 用於高密度電路的具有集成堆疊3d金屬線之3d電路的製作方法 | |
| CN112349729A (zh) | 垂直半导体器件 | |
| TWI799144B (zh) | 半導體裝置及其製造方法 | |
| US20240290714A1 (en) | Three-dimensional memory device containing multi-level word line contact wells and methods for manufacturing the same | |
| CN112397519B (zh) | 一种半导体器件及其制备方法 | |
| CN113517218B (zh) | 半导体位线接触件的制造方法、位线的制造方法及存储器 | |
| WO2022146557A1 (en) | Methods for forming conductive vias, and associated devices and systems | |
| JP4695120B2 (ja) | メモリ構造の製造方法 | |
| CN114695356A (zh) | 一种半导体结构及其制备方法 | |
| CN105336676B (zh) | 接触插塞的形成方法 | |
| CN114823336B (zh) | 半导体结构的形成方法 | |
| US10395980B1 (en) | Dual airgap structure | |
| KR20250139342A (ko) | 반도체 구조, 이의 형성 방법 및 반도체 디바이스 | |
| EP3840034A1 (en) | A semiconductor fabrication method for producing nanoscaled electrically conductive lines |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |