JP4695120B2 - メモリ構造の製造方法 - Google Patents
メモリ構造の製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 52
- 229910052710 silicon Inorganic materials 0.000 claims description 52
- 239000010703 silicon Substances 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 45
- 239000002019 doping agent Substances 0.000 claims description 30
- 239000003990 capacitor Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000003139 buffering effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 238000001312 dry etching Methods 0.000 description 11
- 238000001459 lithography Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000007687 exposure technique Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
12 半導体基板
13A、13B ドーパント領域
14、102、122 ワードライン
16、66 窒化シリコン間隙壁
18 窒化シリコン層
20 誘電層の積層体
22、24、28、58 誘電層
26、34 シリコン含有層
26′、34′、50 エッチングマスク
28′ 線状のフォトレジスト層
42、48 ドーパントマスク
44 予定領域
46、106、126 能動領域
50A、50B 誘電ブロック
52A 第一の開口
52B 第二の開口
54 第一の導電プラグ
54A 第一の導電ブロック
54B 第二の導電ブロック
56 第二の導電プラグ
56A 第三の導電ブロック
56B 第四の導電ブロック
60 ビットライン接触プラグ
62、104、124 ビットライン
64 窒化シリコンマスク
68 酸化シリコン層
70 フォトレジスト層
72 線状の開口
74 接触ホール
76、110、130 キャパシタプラグ
78 キャパシタ
100、120 DRAM
108、128 ビットラインプラグ
Claims (19)
- 半導体基板と、複数のワードラインと、複数のビットラインと、複数のキャパシタと、を含むダイナミックランダムアクセスメモリ(DRAM)構造の製造方法であって、
誘電層の積層体を有する基板上に複数の線状のブロックを形成する工程と、
前記線状のブロックの一部を露出する第一のエッチングマスクを形成する工程と、
前記第一のエッチングマスクを用いて前記線状のブロックの前記一部を除去し、第二のエッチングマスクを形成する工程と、
前記第二のエッチングマスクに覆われていない前記誘電層の積層体を局部的に除去し、前記誘電層の積層体に複数の開口を形成する工程と、
前記開口の中に導電プラグを形成する工程と、
を含む、
DRAMの製造方法。 - 前記第一のエッチングマスクを形成する工程は、
前記複数の線状のブロックを覆うシリコン含有層を形成する工程と、
前記シリコン含有層の所定部分の化学性質を変更する工程と、
前記所定部分以外の前記シリコン含有層を除去し、前記所定部分の前記シリコン含有層を前記第一のエッチングマスクとして用いる工程と、
を含み、
前記シリコン含有層の所定部分は、前記線状のブロックの前記一部以外の部分に対応する前記シリコン含有層の部分である、
請求項1に記載のDRAM構造の製造方法。 - 前記所定部分の前記シリコン含有層の化学性質を変更する工程は、ドーピング工程を行い、ドーパントを前記所定部分の前記シリコン含有層に注入する工程を含む、
請求項2に記載のDRAM構造の製造方法。 - 前記所定部分以外の前記シリコン含有層を除去する工程は、前記線状のブロックの側壁における前記シリコン含有層を局部的に除去する工程を含む、
請求項3に記載のDRAM構造の製造方法。 - 前記ドーピング工程は傾斜ドーピング工程を含み、
前記シリコン含有層はポリシリコンを含み、前記ドーパントは二フッ化ボロンを含む、
請求項3に記載のDRAM構造の製造方法。 - 前記所定部分以外の前記シリコン含有層を除去する工程は、アンモニア水を用いたウェットエッチング工程を含む、
請求項5に記載のDRAM構造の製造方法。 - 前記線状のブロックの前記一部を露出する第一のエッチングマスクを形成する工程は、
前記複数の線状のブロックを覆うシリコン含有層を形成する工程と、
前記シリコン含有層の所定領域を覆う第一のドーパントマスクを形成する工程と、
第一の傾斜ドーピング工程を行い、前記所定領域以外の前記シリコン含有層にドーパントを注入し、前記シリコン含有層の所定部分の化学性質を変更する工程と、
を含み、
前記シリコン含有層の所定領域は、前記線状のブロックの前記一部以外の部分に対応する前記シリコン含有層の領域である、
請求項1に記載のDRAM構造の製造方法。 - 前記所定領域内の前記シリコン含有層を露出する第二のドーパントマスクを形成する工程と、
第二の傾斜ドーピング工程を行い、前記所定領域内の前記シリコン含有層にドーパントを注入する工程と、
を含み、
前記第一の傾斜ドーピング工程のドーピング方向は、前記第二の傾斜ドーピング工程のドーピング方向と異なる、
請求項7に記載のDRAM構造の製造方法。 - 前記第一の傾斜ドーピング工程のドーピング方向と前記第二の傾斜ドーピング工程のドーピング方向は、基板平面に対してそれぞれ反対方向に向かっている、
請求項8に記載のDRAM構造の製造方法。 - 前記所定領域内の導電プラグと接続される複数のビットライン接触プラグを形成する工程と、
前記所定領域以外の導電プラグと接続される複数のキャパシタ接触プラグを形成する工程と、
を更に含む、
請求項7に記載のDRAM構造の製造方法。 - 前記線状のブロックの前記一部を除去し、第二のエッチングマスクを形成する工程は、ウェットエッチング工程を実施する工程を含む、
請求項7に記載のDRAM構造の製造方法。 - 前記線状のブロックが誘電材料からなり、且つ前記ウェットエッチング工程がバッファリング酸化物エッチング液を用いて前記線状のブロックの前記一部を除去することである、
請求項11に記載のDRAM構造の製造方法。 - 前記ウェットエッチング工程により前記線状のブロックの幅が縮減される、
請求項11に記載のDRAM構造の製造方法。 - 前記所定部分内の前記線状のブロックの幅の縮減方向は、前記所定部分以外の前記線状のブロックの幅の縮減方向と異なる、
請求項13に記載のDRAM構造の製造方法。 - 前記所定領域内の前記線状のブロックの幅の縮減方向と前記所定領域以外の前記線状のブロックの幅の縮減方向は、基板平面に対してそれぞれ反対方向に向かっている、
請求項14に記載のDRAM構造の製造方法。 - 前記誘電層の積層体上にシリコン含有層を形成し、前記線状のブロックが当該シリコン含有層上に形成される工程を更に含む、
請求項1に記載のDRAM構造の製造方法。 - 前記第二のエッチングマスクに覆われない前記誘電層の積層体を局部的に除去し、前記誘電層の積層体の中で複数の前記開口を形成する工程は、
前記第二のエッチングマスクに覆われない前記シリコン含有層を除去し、第三のエッチングマスクを形成する工程と、
前記第三のエッチングマスクに覆われない前記誘電層の積層体を除去し、複数の開口を形成する工程と、
を含む、
請求項16に記載のDRAM構造の製造方法。 - 前記第二のエッチングマスクは、複数の第一のブロックと複数の第二のブロックを含み、且つ当該第一のブロックと当該第二のブロックとは、千鳥状に配置される、
請求項17に記載のDRAM構造の製造方法。 - 前記複数の開口は、前記第一のブロック間に設置される複数の第一の開口と、前記第二ブロック間に設置される複数の第二の開口と、を含む、
請求項18に記載のDRAM構造の製造方法。
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TW095130947 | 2006-08-23 | ||
TW095130947A TWI306303B (en) | 2006-08-23 | 2006-08-23 | Method for preparing memory structure |
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JP2008053705A JP2008053705A (ja) | 2008-03-06 |
JP4695120B2 true JP4695120B2 (ja) | 2011-06-08 |
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US (1) | US7582524B2 (ja) |
JP (1) | JP4695120B2 (ja) |
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TWI306288B (en) * | 2006-08-18 | 2009-02-11 | Promos Technologies Inc | Memory structure and method for preparing the same |
CN113097146B (zh) * | 2021-03-31 | 2022-06-17 | 长鑫存储技术有限公司 | 半导体结构的制备方法及半导体结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936333A (ja) * | 1995-07-24 | 1997-02-07 | Siemens Ag | 半導体装置内のコンデンサ及びその製造方法 |
JP2000077620A (ja) * | 1998-08-31 | 2000-03-14 | Nec Corp | Dram及びその製造方法 |
JP2001077325A (ja) * | 1999-08-06 | 2001-03-23 | Samsung Electronics Co Ltd | 写真工程の解像度を越えるトレンチを絶縁膜の内に形成する方法 |
JP2001244429A (ja) * | 2000-02-28 | 2001-09-07 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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US6309975B1 (en) * | 1997-03-14 | 2001-10-30 | Micron Technology, Inc. | Methods of making implanted structures |
KR100356775B1 (ko) * | 2000-12-11 | 2002-10-18 | 삼성전자 주식회사 | 2중층의 캐핑 패턴을 사용하여 반도체 메모리소자를형성하는 방법 및 그에 의해 형성된 반도체 메모리소자 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936333A (ja) * | 1995-07-24 | 1997-02-07 | Siemens Ag | 半導体装置内のコンデンサ及びその製造方法 |
JP2000077620A (ja) * | 1998-08-31 | 2000-03-14 | Nec Corp | Dram及びその製造方法 |
JP2001077325A (ja) * | 1999-08-06 | 2001-03-23 | Samsung Electronics Co Ltd | 写真工程の解像度を越えるトレンチを絶縁膜の内に形成する方法 |
JP2001244429A (ja) * | 2000-02-28 | 2001-09-07 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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JP2008053705A (ja) | 2008-03-06 |
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US7582524B2 (en) | 2009-09-01 |
US20080050878A1 (en) | 2008-02-28 |
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