KR102088692B1 - 신뢰성 있는 표면 실장 집적 전력 모듈 - Google Patents

신뢰성 있는 표면 실장 집적 전력 모듈 Download PDF

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KR102088692B1
KR102088692B1 KR1020130090523A KR20130090523A KR102088692B1 KR 102088692 B1 KR102088692 B1 KR 102088692B1 KR 1020130090523 A KR1020130090523 A KR 1020130090523A KR 20130090523 A KR20130090523 A KR 20130090523A KR 102088692 B1 KR102088692 B1 KR 102088692B1
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layer
surface mount
dbc
dielectric
level
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KR20140016204A (ko
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아룬 비루팍스카 고다
폴 알란 맥코넬리
샤크티 싱 챠우한
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제너럴 일렉트릭 캄파니
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8804339B2 (en) * 2011-02-28 2014-08-12 Toyota Motor Engineering & Manufacturing North America, Inc. Power electronics assemblies, insulated metal substrate assemblies, and vehicles incorporating the same
DE102011078811B3 (de) * 2011-07-07 2012-05-24 Semikron Elektronik Gmbh & Co. Kg Leistungselektronisches System mit einer Kühleinrichtung
KR20130129712A (ko) * 2012-05-21 2013-11-29 페어차일드코리아반도체 주식회사 반도체 패키지 및 이의 제조방법
US8941208B2 (en) * 2012-07-30 2015-01-27 General Electric Company Reliable surface mount integrated power module
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
US8987876B2 (en) 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US9312231B2 (en) * 2013-10-31 2016-04-12 Freescale Semiconductor, Inc. Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process
US9659837B2 (en) * 2015-01-30 2017-05-23 Semiconductor Components Industries, Llc Direct bonded copper semiconductor packages and related methods
JP6418126B2 (ja) 2015-10-09 2018-11-07 三菱電機株式会社 半導体装置
US9443792B1 (en) * 2015-10-31 2016-09-13 Ixys Corporation Bridging DMB structure for wire bonding in a power semiconductor device module
JP6403741B2 (ja) * 2016-09-30 2018-10-10 三菱電機株式会社 表面実装型半導体パッケージ装置
US9953917B1 (en) 2016-12-12 2018-04-24 General Electric Company Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof
US9953913B1 (en) 2016-12-12 2018-04-24 General Electric Company Electronics package with embedded through-connect structure and method of manufacturing thereof
TWI648854B (zh) * 2017-06-14 2019-01-21 穩懋半導體股份有限公司 用以減少化合物半導體晶圓變形之改良結構
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement
US10892237B2 (en) * 2018-12-14 2021-01-12 General Electric Company Methods of fabricating high voltage semiconductor devices having improved electric field suppression
DE102019121012B4 (de) * 2019-08-02 2024-06-13 Infineon Technologies Ag Package und Verfahren zum Herstellen eines Packages
US11398445B2 (en) 2020-05-29 2022-07-26 General Electric Company Mechanical punched via formation in electronics package and electronics package formed thereby
CN118451543A (zh) * 2022-03-31 2024-08-06 华为技术有限公司 芯片封装结构、电子设备及芯片封装结构的制备方法
US12431402B2 (en) 2022-07-26 2025-09-30 Avago Technologies International Sales Pte. Limited Stress and warpage improvements for stiffener ring package with exposed die(s)
TWI869906B (zh) * 2023-06-29 2025-01-11 同欣電子工業股份有限公司 預模製直接覆銅基板及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017627A (ja) * 2001-06-28 2003-01-17 Toshiba Corp セラミックス回路基板およびそれを用いた半導体モジュール
US20070235810A1 (en) * 2006-04-07 2007-10-11 Delgado Eladio C Power semiconductor module and fabrication method
JP2010219529A (ja) * 2009-03-13 2010-09-30 General Electric Co <Ge> 両面冷却式電力用被覆層付き電力モジュール

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104078A (en) * 1994-03-09 2000-08-15 Denso Corporation Design for a semiconductor device having elements isolated by insulating regions
US5880530A (en) 1996-03-29 1999-03-09 Intel Corporation Multiregion solder interconnection structure
US6404065B1 (en) 1998-07-31 2002-06-11 I-Xys Corporation Electrically isolated power semiconductor package
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
JP3683179B2 (ja) 2000-12-26 2005-08-17 松下電器産業株式会社 半導体装置及びその製造方法
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
DE10227658B4 (de) * 2002-06-20 2012-03-08 Curamik Electronics Gmbh Metall-Keramik-Substrat für elektrische Schaltkreise -oder Module, Verfahren zum Herstellen eines solchen Substrates sowie Modul mit einem solchen Substrat
CN2613046Y (zh) * 2003-04-17 2004-04-21 威盛电子股份有限公司 芯片封装结构
JP3809168B2 (ja) * 2004-02-03 2006-08-16 株式会社東芝 半導体モジュール
TWI245384B (en) * 2004-12-10 2005-12-11 Phoenix Prec Technology Corp Package structure with embedded chip and method for fabricating the same
US7190581B1 (en) * 2005-01-11 2007-03-13 Midwest Research Institute Low thermal resistance power module assembly
JP4207896B2 (ja) * 2005-01-19 2009-01-14 富士電機デバイステクノロジー株式会社 半導体装置
JP4793622B2 (ja) * 2005-03-04 2011-10-12 日立金属株式会社 セラミックス回路基板およびパワーモジュール並びにパワーモジュールの製造方法
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
TWI279897B (en) * 2005-12-23 2007-04-21 Phoenix Prec Technology Corp Embedded semiconductor chip structure and method for fabricating the same
US8018056B2 (en) 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
CN101401197B (zh) * 2006-03-08 2011-05-18 株式会社东芝 电子元器件模块
US7999369B2 (en) 2006-08-29 2011-08-16 Denso Corporation Power electronic package having two substrates with multiple semiconductor chips and electronic components
KR101391924B1 (ko) 2007-01-05 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지
US20080190748A1 (en) * 2007-02-13 2008-08-14 Stephen Daley Arthur Power overlay structure for mems devices and method for making power overlay structure for mems devices
DE102007041921A1 (de) * 2007-09-04 2009-03-05 Siemens Ag Verfahren zur Herstellung und Kontaktierung von elektronischen Bauelementen mittels einer Substratplatte, insbesondere DCB-Keramik-Substratplatte
US8030752B2 (en) * 2007-12-18 2011-10-04 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing semiconductor package and semiconductor plastic package using the same
CN101971329B (zh) * 2008-03-17 2012-11-21 三菱综合材料株式会社 带散热片的功率模块用基板及其制造方法、以及带散热片的功率模块、功率模块用基板
JP5284155B2 (ja) * 2008-03-24 2013-09-11 日本特殊陶業株式会社 部品内蔵配線基板
JP2010263080A (ja) * 2009-05-07 2010-11-18 Denso Corp 半導体装置
US8409926B2 (en) * 2010-03-09 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer around semiconductor die
CN201667332U (zh) * 2010-03-29 2010-12-08 比亚迪股份有限公司 一种半导体功率模块
US8531027B2 (en) * 2010-04-30 2013-09-10 General Electric Company Press-pack module with power overlay interconnection
JP2011253950A (ja) * 2010-06-02 2011-12-15 Mitsubishi Electric Corp 電力半導体装置
CN102339818B (zh) 2010-07-15 2014-04-30 台达电子工业股份有限公司 功率模块及其制造方法
US8114712B1 (en) * 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package
CN202135401U (zh) * 2011-05-30 2012-02-01 宝鸡市博瑞德金属材料有限公司 高导热型铝基板
US8941208B2 (en) * 2012-07-30 2015-01-27 General Electric Company Reliable surface mount integrated power module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017627A (ja) * 2001-06-28 2003-01-17 Toshiba Corp セラミックス回路基板およびそれを用いた半導体モジュール
US20070235810A1 (en) * 2006-04-07 2007-10-11 Delgado Eladio C Power semiconductor module and fabrication method
JP2010219529A (ja) * 2009-03-13 2010-09-30 General Electric Co <Ge> 両面冷却式電力用被覆層付き電力モジュール

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US9184124B2 (en) 2015-11-10
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CN111508909B (zh) 2024-12-17
SG196753A1 (en) 2014-02-13
CN110060962B (zh) 2023-09-26
TWI587477B (zh) 2017-06-11
KR20140016204A (ko) 2014-02-07
TW201413916A (zh) 2014-04-01
CN110060962A (zh) 2019-07-26
CN103579137B (zh) 2020-03-13
EP2693472A3 (en) 2017-08-09
JP2014027272A (ja) 2014-02-06
EP2693472A2 (en) 2014-02-05
JP6302184B2 (ja) 2018-03-28
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