TWI587477B - 可靠表面安裝積體功率模組 - Google Patents
可靠表面安裝積體功率模組 Download PDFInfo
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- TWI587477B TWI587477B TW102125293A TW102125293A TWI587477B TW I587477 B TWI587477 B TW I587477B TW 102125293 A TW102125293 A TW 102125293A TW 102125293 A TW102125293 A TW 102125293A TW I587477 B TWI587477 B TW I587477B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Combinations Of Printed Boards (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/561,811 US8941208B2 (en) | 2012-07-30 | 2012-07-30 | Reliable surface mount integrated power module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201413916A TW201413916A (zh) | 2014-04-01 |
| TWI587477B true TWI587477B (zh) | 2017-06-11 |
Family
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| TW102125293A TWI587477B (zh) | 2012-07-30 | 2013-07-15 | 可靠表面安裝積體功率模組 |
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| JP (1) | JP6302184B2 (enExample) |
| KR (1) | KR102088692B1 (enExample) |
| CN (3) | CN110060962B (enExample) |
| SG (1) | SG196753A1 (enExample) |
| TW (1) | TWI587477B (enExample) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8804339B2 (en) * | 2011-02-28 | 2014-08-12 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics assemblies, insulated metal substrate assemblies, and vehicles incorporating the same |
| DE102011078811B3 (de) * | 2011-07-07 | 2012-05-24 | Semikron Elektronik Gmbh & Co. Kg | Leistungselektronisches System mit einer Kühleinrichtung |
| KR20130129712A (ko) * | 2012-05-21 | 2013-11-29 | 페어차일드코리아반도체 주식회사 | 반도체 패키지 및 이의 제조방법 |
| US8941208B2 (en) * | 2012-07-30 | 2015-01-27 | General Electric Company | Reliable surface mount integrated power module |
| US10269688B2 (en) | 2013-03-14 | 2019-04-23 | General Electric Company | Power overlay structure and method of making same |
| US8987876B2 (en) | 2013-03-14 | 2015-03-24 | General Electric Company | Power overlay structure and method of making same |
| US9312231B2 (en) * | 2013-10-31 | 2016-04-12 | Freescale Semiconductor, Inc. | Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process |
| US9659837B2 (en) | 2015-01-30 | 2017-05-23 | Semiconductor Components Industries, Llc | Direct bonded copper semiconductor packages and related methods |
| JP6418126B2 (ja) * | 2015-10-09 | 2018-11-07 | 三菱電機株式会社 | 半導体装置 |
| US9443792B1 (en) * | 2015-10-31 | 2016-09-13 | Ixys Corporation | Bridging DMB structure for wire bonding in a power semiconductor device module |
| JP6403741B2 (ja) * | 2016-09-30 | 2018-10-10 | 三菱電機株式会社 | 表面実装型半導体パッケージ装置 |
| US9953917B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof |
| US9953913B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect structure and method of manufacturing thereof |
| TWI648854B (zh) * | 2017-06-14 | 2019-01-21 | 穩懋半導體股份有限公司 | 用以減少化合物半導體晶圓變形之改良結構 |
| US10541153B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
| US10804115B2 (en) | 2017-08-03 | 2020-10-13 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
| US10541209B2 (en) | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
| US10332832B2 (en) | 2017-08-07 | 2019-06-25 | General Electric Company | Method of manufacturing an electronics package using device-last or device-almost last placement |
| US10892237B2 (en) * | 2018-12-14 | 2021-01-12 | General Electric Company | Methods of fabricating high voltage semiconductor devices having improved electric field suppression |
| DE102019121012B4 (de) * | 2019-08-02 | 2024-06-13 | Infineon Technologies Ag | Package und Verfahren zum Herstellen eines Packages |
| US11398445B2 (en) | 2020-05-29 | 2022-07-26 | General Electric Company | Mechanical punched via formation in electronics package and electronics package formed thereby |
| CN118451543A (zh) * | 2022-03-31 | 2024-08-06 | 华为技术有限公司 | 芯片封装结构、电子设备及芯片封装结构的制备方法 |
| US12431402B2 (en) | 2022-07-26 | 2025-09-30 | Avago Technologies International Sales Pte. Limited | Stress and warpage improvements for stiffener ring package with exposed die(s) |
| TWI869906B (zh) * | 2023-06-29 | 2025-01-11 | 同欣電子工業股份有限公司 | 預模製直接覆銅基板及其製造方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
| US20060103005A1 (en) * | 2002-06-20 | 2006-05-18 | Jurgen Schulz-Harder | Metal-ceramic substrate for electric circuits or modules, method for producing one such substrate and module comprising one such substrate |
| US20060128069A1 (en) * | 2004-12-10 | 2006-06-15 | Phoenix Precision Technology Corporation | Package structure with embedded chip and method for fabricating the same |
| US7190581B1 (en) * | 2005-01-11 | 2007-03-13 | Midwest Research Institute | Low thermal resistance power module assembly |
| US20100230800A1 (en) * | 2009-03-13 | 2010-09-16 | Richard Alfred Beaupre | Double side cooled power module with power overlay |
Family Cites Families (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6104078A (en) * | 1994-03-09 | 2000-08-15 | Denso Corporation | Design for a semiconductor device having elements isolated by insulating regions |
| US5880530A (en) | 1996-03-29 | 1999-03-09 | Intel Corporation | Multiregion solder interconnection structure |
| US6404065B1 (en) | 1998-07-31 | 2002-06-11 | I-Xys Corporation | Electrically isolated power semiconductor package |
| JP3683179B2 (ja) | 2000-12-26 | 2005-08-17 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
| JP4969738B2 (ja) * | 2001-06-28 | 2012-07-04 | 株式会社東芝 | セラミックス回路基板およびそれを用いた半導体モジュール |
| US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
| CN2613046Y (zh) * | 2003-04-17 | 2004-04-21 | 威盛电子股份有限公司 | 芯片封装结构 |
| JP3809168B2 (ja) * | 2004-02-03 | 2006-08-16 | 株式会社東芝 | 半導体モジュール |
| JP4207896B2 (ja) * | 2005-01-19 | 2009-01-14 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
| JP4793622B2 (ja) * | 2005-03-04 | 2011-10-12 | 日立金属株式会社 | セラミックス回路基板およびパワーモジュール並びにパワーモジュールの製造方法 |
| US20070126085A1 (en) * | 2005-12-02 | 2007-06-07 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| TWI279897B (en) * | 2005-12-23 | 2007-04-21 | Phoenix Prec Technology Corp | Embedded semiconductor chip structure and method for fabricating the same |
| US8018056B2 (en) | 2005-12-21 | 2011-09-13 | International Rectifier Corporation | Package for high power density devices |
| EP2006895B1 (en) * | 2006-03-08 | 2019-09-18 | Kabushiki Kaisha Toshiba | Electronic component module |
| US8049338B2 (en) * | 2006-04-07 | 2011-11-01 | General Electric Company | Power semiconductor module and fabrication method |
| US7999369B2 (en) | 2006-08-29 | 2011-08-16 | Denso Corporation | Power electronic package having two substrates with multiple semiconductor chips and electronic components |
| KR101391924B1 (ko) | 2007-01-05 | 2014-05-07 | 페어차일드코리아반도체 주식회사 | 반도체 패키지 |
| US20080190748A1 (en) * | 2007-02-13 | 2008-08-14 | Stephen Daley Arthur | Power overlay structure for mems devices and method for making power overlay structure for mems devices |
| DE102007041921A1 (de) * | 2007-09-04 | 2009-03-05 | Siemens Ag | Verfahren zur Herstellung und Kontaktierung von elektronischen Bauelementen mittels einer Substratplatte, insbesondere DCB-Keramik-Substratplatte |
| US8030752B2 (en) * | 2007-12-18 | 2011-10-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package and semiconductor plastic package using the same |
| EP2259308B1 (en) * | 2008-03-17 | 2022-06-15 | Mitsubishi Materials Corporation | Substrate for power module with heat sink and method for producing the same, power module with heat sink, and substrate for power module |
| JP5284155B2 (ja) * | 2008-03-24 | 2013-09-11 | 日本特殊陶業株式会社 | 部品内蔵配線基板 |
| JP2010263080A (ja) * | 2009-05-07 | 2010-11-18 | Denso Corp | 半導体装置 |
| US8409926B2 (en) * | 2010-03-09 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer around semiconductor die |
| CN201667332U (zh) * | 2010-03-29 | 2010-12-08 | 比亚迪股份有限公司 | 一种半导体功率模块 |
| US8531027B2 (en) * | 2010-04-30 | 2013-09-10 | General Electric Company | Press-pack module with power overlay interconnection |
| JP2011253950A (ja) * | 2010-06-02 | 2011-12-15 | Mitsubishi Electric Corp | 電力半導体装置 |
| CN102339818B (zh) | 2010-07-15 | 2014-04-30 | 台达电子工业股份有限公司 | 功率模块及其制造方法 |
| US8114712B1 (en) * | 2010-12-22 | 2012-02-14 | General Electric Company | Method for fabricating a semiconductor device package |
| CN202135401U (zh) * | 2011-05-30 | 2012-02-01 | 宝鸡市博瑞德金属材料有限公司 | 高导热型铝基板 |
| US8941208B2 (en) * | 2012-07-30 | 2015-01-27 | General Electric Company | Reliable surface mount integrated power module |
-
2012
- 2012-07-30 US US13/561,811 patent/US8941208B2/en active Active
-
2013
- 2013-07-15 TW TW102125293A patent/TWI587477B/zh active
- 2013-07-17 JP JP2013148095A patent/JP6302184B2/ja active Active
- 2013-07-24 EP EP13177852.4A patent/EP2693472B1/en active Active
- 2013-07-25 SG SG2013056916A patent/SG196753A1/en unknown
- 2013-07-30 CN CN201811531761.4A patent/CN110060962B/zh active Active
- 2013-07-30 KR KR1020130090523A patent/KR102088692B1/ko active Active
- 2013-07-30 CN CN202010096033.6A patent/CN111508909B/zh active Active
- 2013-07-30 CN CN201310324485.5A patent/CN103579137B/zh active Active
-
2014
- 2014-11-19 US US14/547,667 patent/US9184124B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
| US20060103005A1 (en) * | 2002-06-20 | 2006-05-18 | Jurgen Schulz-Harder | Metal-ceramic substrate for electric circuits or modules, method for producing one such substrate and module comprising one such substrate |
| US20060128069A1 (en) * | 2004-12-10 | 2006-06-15 | Phoenix Precision Technology Corporation | Package structure with embedded chip and method for fabricating the same |
| US7190581B1 (en) * | 2005-01-11 | 2007-03-13 | Midwest Research Institute | Low thermal resistance power module assembly |
| US20100230800A1 (en) * | 2009-03-13 | 2010-09-16 | Richard Alfred Beaupre | Double side cooled power module with power overlay |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2693472A3 (en) | 2017-08-09 |
| JP6302184B2 (ja) | 2018-03-28 |
| US20150069612A1 (en) | 2015-03-12 |
| JP2014027272A (ja) | 2014-02-06 |
| EP2693472B1 (en) | 2022-12-14 |
| US20140029234A1 (en) | 2014-01-30 |
| CN110060962B (zh) | 2023-09-26 |
| KR20140016204A (ko) | 2014-02-07 |
| CN103579137A (zh) | 2014-02-12 |
| US8941208B2 (en) | 2015-01-27 |
| CN111508909B (zh) | 2024-12-17 |
| US9184124B2 (en) | 2015-11-10 |
| SG196753A1 (en) | 2014-02-13 |
| CN110060962A (zh) | 2019-07-26 |
| CN103579137B (zh) | 2020-03-13 |
| TW201413916A (zh) | 2014-04-01 |
| KR102088692B1 (ko) | 2020-03-13 |
| EP2693472A2 (en) | 2014-02-05 |
| CN111508909A (zh) | 2020-08-07 |
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