KR101972286B1 - Soi 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 soi 구조체 - Google Patents

Soi 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 soi 구조체 Download PDF

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KR101972286B1
KR101972286B1 KR1020187012785A KR20187012785A KR101972286B1 KR 101972286 B1 KR101972286 B1 KR 101972286B1 KR 1020187012785 A KR1020187012785 A KR 1020187012785A KR 20187012785 A KR20187012785 A KR 20187012785A KR 101972286 B1 KR101972286 B1 KR 101972286B1
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wafer
silicon
handle wafer
dielectric layer
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KR20180052773A (ko
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존 에이. 피트니
이찌로 요시무라
루 페이
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썬에디슨, 인크.
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    • H01L21/02024
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L21/02041
    • H01L21/76254
    • H01L21/84
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/10Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12Preparing bulk and homogeneous wafers
    • H10P90/129Preparing bulk and homogeneous wafers by polishing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020187012785A 2010-02-25 2011-02-07 Soi 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 soi 구조체 Active KR101972286B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US30818510P 2010-02-25 2010-02-25
US61/308,185 2010-02-25
PCT/US2011/023937 WO2011106144A1 (en) 2010-02-25 2011-02-07 Methods for reducing the width of the unbonded region in soi structures and wafers and soi structures produced by such methods

Related Parent Applications (1)

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KR1020127022324A Division KR101882026B1 (ko) 2010-02-25 2011-02-07 Soi 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 soi 구조체

Publications (2)

Publication Number Publication Date
KR20180052773A KR20180052773A (ko) 2018-05-18
KR101972286B1 true KR101972286B1 (ko) 2019-04-24

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KR1020187012785A Active KR101972286B1 (ko) 2010-02-25 2011-02-07 Soi 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 soi 구조체
KR1020127022324A Active KR101882026B1 (ko) 2010-02-25 2011-02-07 Soi 구조체 및 웨이퍼 내 미접합 영역의 폭을 줄이는 방법 및 그러한 방법에 의해 생성된 soi 구조체

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Country Status (8)

Country Link
US (2) US8330245B2 (https=)
EP (1) EP2539928B1 (https=)
JP (1) JP6066729B2 (https=)
KR (2) KR101972286B1 (https=)
CN (1) CN102770955B (https=)
SG (2) SG183175A1 (https=)
TW (1) TWI518779B (https=)
WO (1) WO2011106144A1 (https=)

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US8637381B2 (en) * 2011-10-17 2014-01-28 International Business Machines Corporation High-k dielectric and silicon nitride box region
US8796054B2 (en) * 2012-05-31 2014-08-05 Corning Incorporated Gallium nitride to silicon direct wafer bonding
US8896964B1 (en) 2013-05-16 2014-11-25 Seagate Technology Llc Enlarged substrate for magnetic recording medium
JP6314019B2 (ja) * 2014-03-31 2018-04-18 ニッタ・ハース株式会社 半導体基板の研磨方法
US10128146B2 (en) 2015-08-20 2018-11-13 Globalwafers Co., Ltd. Semiconductor substrate polishing methods and slurries and methods for manufacturing silicon on insulator structures
JP6749394B2 (ja) 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. 滑らかな半導体表面の製造方法
US9806025B2 (en) 2015-12-29 2017-10-31 Globalfoundries Inc. SOI wafers with buried dielectric layers to prevent Cu diffusion
US10679908B2 (en) * 2017-01-23 2020-06-09 Globalwafers Co., Ltd. Cleave systems, mountable cleave monitoring systems, and methods for separating bonded wafer structures
KR102904959B1 (ko) 2017-03-02 2025-12-31 에베 그룹 에. 탈너 게엠베하 칩들을 본딩하기 위한 방법 및 디바이스
CN109425315B (zh) * 2017-08-31 2021-01-15 长鑫存储技术有限公司 半导体结构的测试载具及测试方法
EP4210092A1 (en) 2018-06-08 2023-07-12 GlobalWafers Co., Ltd. Method for transfer of a thin layer of silicon
JP7067465B2 (ja) * 2018-12-27 2022-05-16 株式会社Sumco 半導体ウェーハの評価方法及び半導体ウェーハの製造方法

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JP2004186226A (ja) * 2002-11-29 2004-07-02 Shin Etsu Handotai Co Ltd Soiウエーハの製造方法

Also Published As

Publication number Publication date
SG183175A1 (en) 2012-09-27
US8440541B2 (en) 2013-05-14
CN102770955A (zh) 2012-11-07
US8330245B2 (en) 2012-12-11
KR20120121905A (ko) 2012-11-06
TWI518779B (zh) 2016-01-21
WO2011106144A1 (en) 2011-09-01
CN102770955B (zh) 2015-06-17
EP2539928A1 (en) 2013-01-02
SG189816A1 (en) 2013-05-31
JP2013520838A (ja) 2013-06-06
EP2539928B1 (en) 2016-10-19
JP6066729B2 (ja) 2017-01-25
KR101882026B1 (ko) 2018-07-25
US20110207246A1 (en) 2011-08-25
KR20180052773A (ko) 2018-05-18
US20110204471A1 (en) 2011-08-25
TW201140694A (en) 2011-11-16

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