KR101671367B1 - 멀티-칩 모듈 및 이를 제조하는 방법 - Google Patents

멀티-칩 모듈 및 이를 제조하는 방법 Download PDF

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KR101671367B1
KR101671367B1 KR1020157010779A KR20157010779A KR101671367B1 KR 101671367 B1 KR101671367 B1 KR 101671367B1 KR 1020157010779 A KR1020157010779 A KR 1020157010779A KR 20157010779 A KR20157010779 A KR 20157010779A KR 101671367 B1 KR101671367 B1 KR 101671367B1
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die
fuse
chip module
node
esd
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KR20150064117A (ko
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브라이언 엠. 헨더슨
치우-구안 탄
그레고리 에이. 유비에그하라
레자 잘리리제인알리
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퀄컴 인코포레이티드
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
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    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020157010779A 2012-10-05 2013-10-03 멀티-칩 모듈 및 이를 제조하는 방법 Active KR101671367B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/646,109 2012-10-05
US13/646,109 US9184130B2 (en) 2012-10-05 2012-10-05 Electrostatic protection for stacked multi-chip integrated circuits
PCT/US2013/063297 WO2014055777A1 (en) 2012-10-05 2013-10-03 Electrostatic protection for stacked multi-chip integrated circuits

Publications (2)

Publication Number Publication Date
KR20150064117A KR20150064117A (ko) 2015-06-10
KR101671367B1 true KR101671367B1 (ko) 2016-11-01

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Country Status (6)

Country Link
US (1) US9184130B2 (enExample)
EP (1) EP2904638B1 (enExample)
JP (1) JP5972473B2 (enExample)
KR (1) KR101671367B1 (enExample)
CN (1) CN104737288B (enExample)
WO (1) WO2014055777A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9184130B2 (en) * 2012-10-05 2015-11-10 Qualcomm Incorporated Electrostatic protection for stacked multi-chip integrated circuits
JP5543567B2 (ja) * 2012-10-22 2014-07-09 誠 雫石 半導体素子の製造方法
KR102341750B1 (ko) 2015-06-30 2021-12-23 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR102482023B1 (ko) * 2016-01-28 2022-12-28 삼성전자주식회사 적층 메모리 칩 전기적 단락 검출 장치 및 방법
US10147688B2 (en) 2016-02-25 2018-12-04 Allegro Microsystems, Llc Integrated circuit device with overvoltage discharge protection
CN107622999B (zh) * 2016-07-15 2020-06-02 中芯国际集成电路制造(上海)有限公司 静电放电保护电路
US10145904B2 (en) * 2016-08-24 2018-12-04 Allegro Microsystems, Llc Multi-die integrated circuit device with overvoltage protection
US9941224B2 (en) 2016-08-24 2018-04-10 Allegro Microsystems, Llc Multi-die integrated circuit device with capacitive overvoltage protection
CN107799502B (zh) * 2016-09-05 2020-03-10 中芯国际集成电路制造(上海)有限公司 保护电路和集成电路
US10325906B2 (en) * 2016-09-23 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. ESD testing structure, method of using same and method of forming same
JP2018133503A (ja) 2017-02-16 2018-08-23 東芝メモリ株式会社 半導体記憶装置
US10552564B1 (en) * 2018-06-19 2020-02-04 Cadence Design Systems, Inc. Determining worst potential failure instances using full chip ESD analysis
US11437708B2 (en) * 2020-03-31 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit
DE102021101251A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Schutz vor antenneneffekten und schutz vor elektrostatischen entladungen für dreidimensionale integrierte schaltkreise
FR3109666A1 (fr) * 2020-04-27 2021-10-29 3D Plus Procédé de fabrication d’un module électronique compatible hautes fréquences
CN112349655B (zh) * 2020-10-21 2021-10-19 长江存储科技有限责任公司 一种半导体器件及其安装结构、封装模具和制作方法
US11973057B2 (en) 2020-12-15 2024-04-30 Analog Devices, Inc. Through-silicon transmission lines and other structures enabled by same
FR3120160B1 (fr) * 2021-02-23 2023-11-03 Commissariat Energie Atomique Procédé de protection d’un étage supérieur de composants électroniques d’un circuit intégré contre l’effet d’antenne

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US6243283B1 (en) 1999-04-30 2001-06-05 International Business Machines Corporation Impedance control using fuses
US6556409B1 (en) 2000-08-31 2003-04-29 Agere Systems Inc. Integrated circuit including ESD circuits for a multi-chip module and a method therefor
JP2010129958A (ja) 2008-12-01 2010-06-10 Seiko Epson Corp 半導体装置及び半導体装置の製造方法

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US6327125B1 (en) 1999-12-22 2001-12-04 Philips Electronics North America Corporation Integrated circuit with removable ESD protection
JP2003324151A (ja) 2002-04-26 2003-11-14 Toshiba Microelectronics Corp 半導体集積回路装置、実装基板装置、及び実装基板装置の配線切断方法
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US9184130B2 (en) * 2012-10-05 2015-11-10 Qualcomm Incorporated Electrostatic protection for stacked multi-chip integrated circuits

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Publication number Priority date Publication date Assignee Title
US6243283B1 (en) 1999-04-30 2001-06-05 International Business Machines Corporation Impedance control using fuses
US6556409B1 (en) 2000-08-31 2003-04-29 Agere Systems Inc. Integrated circuit including ESD circuits for a multi-chip module and a method therefor
JP2010129958A (ja) 2008-12-01 2010-06-10 Seiko Epson Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
JP2015532534A (ja) 2015-11-09
WO2014055777A1 (en) 2014-04-10
US9184130B2 (en) 2015-11-10
EP2904638B1 (en) 2020-05-27
CN104737288B (zh) 2017-09-26
CN104737288A (zh) 2015-06-24
KR20150064117A (ko) 2015-06-10
EP2904638A1 (en) 2015-08-12
US20140098448A1 (en) 2014-04-10
JP5972473B2 (ja) 2016-08-17

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