KR101661705B1 - Ｓｏｉ 기판의 제작 방법 및 반도체 장치의 제작 방법 - Google Patents

Ｓｏｉ 기판의 제작 방법 및 반도체 장치의 제작 방법 Download PDF

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Publication number
KR101661705B1
KR101661705B1 KR1020100000892A KR20100000892A KR101661705B1 KR 101661705 B1 KR101661705 B1 KR 101661705B1 KR 1020100000892 A KR1020100000892 A KR 1020100000892A KR 20100000892 A KR20100000892 A KR 20100000892A KR 101661705 B1 KR101661705 B1 KR 101661705B1
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South Korea
Prior art keywords
single crystal
substrate
crystal semiconductor
semiconductor layer
etching
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Expired - Fee Related
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KR1020100000892A
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English (en)
Korean (ko)
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KR20100085840A (ko
Inventor
코세이 노다
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020100000892A 2009-01-21 2010-01-06 Ｓｏｉ 기판의 제작 방법 및 반도체 장치의 제작 방법 Expired - Fee Related KR101661705B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009011425 2009-01-21
JPJP-P-2009-011425 2009-01-21

Publications (2)

Publication Number Publication Date
KR20100085840A KR20100085840A (ko) 2010-07-29
KR101661705B1 true KR101661705B1 (ko) 2016-09-30

Family

ID=42337296

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100000892A Expired - Fee Related KR101661705B1 (ko) 2009-01-21 2010-01-06 Ｓｏｉ 기판의 제작 방법 및 반도체 장치의 제작 방법

Country Status (4)

Country Link
US (2) US8053332B2 (enExample)
JP (1) JP5667767B2 (enExample)
KR (1) KR101661705B1 (enExample)
SG (2) SG163481A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012139627A1 (de) 2011-04-11 2012-10-18 Ev Group E. Thallner Gmbh Biegsame trägerhalterung, vorrichtung und verfahren zum lösen eines trägersubstrats
FR2978604B1 (fr) * 2011-07-28 2018-09-14 Soitec Procede de guerison de defauts dans une couche semi-conductrice
JP5797504B2 (ja) * 2011-09-16 2015-10-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN103999205B (zh) 2011-12-22 2017-12-01 Ev 集团 E·索尔纳有限责任公司 柔性的基片支架、用于分离第一基片的装置和方法
US8842358B2 (en) 2012-08-01 2014-09-23 Gentex Corporation Apparatus, method, and process with laser induced channel edge
US9029809B2 (en) * 2012-11-30 2015-05-12 Ultratech, Inc. Movable microchamber system with gas curtain
TWI834972B (zh) * 2020-05-29 2024-03-11 日商國際電氣股份有限公司 基板處理方法、半導體裝置之製造方法、基板處理裝置及程式

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252244A (ja) * 2004-02-03 2005-09-15 Ishikawajima Harima Heavy Ind Co Ltd 半導体基板の製造方法
JP2005251912A (ja) * 2004-03-03 2005-09-15 Seiko Epson Corp 複合半導体基板の製造方法、複合半導体基板、電気光学装置および電子機器
JP2009010353A (ja) * 2007-06-01 2009-01-15 Semiconductor Energy Lab Co Ltd 半導体基板の作製方法及び半導体装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
US5166097A (en) * 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
JP3649797B2 (ja) * 1995-12-01 2005-05-18 株式会社半導体エネルギー研究所 半導体装置製造方法
JP3324469B2 (ja) 1997-09-26 2002-09-17 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5968847A (en) * 1998-03-13 1999-10-19 Applied Materials, Inc. Process for copper etch back
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
US6423644B1 (en) * 2000-07-12 2002-07-23 Applied Materials, Inc. Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures
KR100567885B1 (ko) * 2003-12-30 2006-04-04 동부아남반도체 주식회사 반도체 소자의 실리사이드막 제조 방법
JP5127176B2 (ja) * 2005-07-29 2013-01-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
KR101400699B1 (ko) * 2007-05-18 2014-05-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판 및 반도체 장치 및 그 제조 방법
JP5415676B2 (ja) * 2007-05-30 2014-02-12 信越化学工業株式会社 Ｓｏｉウェーハの製造方法
JP5527956B2 (ja) * 2007-10-10 2014-06-25 株式会社半導体エネルギー研究所 半導体基板の製造方法
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP2009135448A (ja) * 2007-11-01 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体基板の作製方法及び半導体装置の作製方法
US8093136B2 (en) * 2007-12-28 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252244A (ja) * 2004-02-03 2005-09-15 Ishikawajima Harima Heavy Ind Co Ltd 半導体基板の製造方法
JP2005251912A (ja) * 2004-03-03 2005-09-15 Seiko Epson Corp 複合半導体基板の製造方法、複合半導体基板、電気光学装置および電子機器
JP2009010353A (ja) * 2007-06-01 2009-01-15 Semiconductor Energy Lab Co Ltd 半導体基板の作製方法及び半導体装置

Also Published As

Publication number Publication date
US20100184269A1 (en) 2010-07-22
US8338270B2 (en) 2012-12-25
US20120077330A1 (en) 2012-03-29
SG178765A1 (en) 2012-03-29
US8053332B2 (en) 2011-11-08
JP5667767B2 (ja) 2015-02-12
KR20100085840A (ko) 2010-07-29
JP2010192884A (ja) 2010-09-02
SG163481A1 (en) 2010-08-30

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