KR101642335B1 - 반도체 기판의 제조방법 - Google Patents

반도체 기판의 제조방법 Download PDF

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Publication number
KR101642335B1
KR101642335B1 KR1020090047957A KR20090047957A KR101642335B1 KR 101642335 B1 KR101642335 B1 KR 101642335B1 KR 1020090047957 A KR1020090047957 A KR 1020090047957A KR 20090047957 A KR20090047957 A KR 20090047957A KR 101642335 B1 KR101642335 B1 KR 101642335B1
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South Korea
Prior art keywords
semiconductor layer
flash lamp
single crystal
substrate
semiconductor substrate
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KR1020090047957A
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English (en)
Korean (ko)
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KR20090127065A (ko
Inventor
코이치로 타나카
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Publication of KR20090127065A publication Critical patent/KR20090127065A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020090047957A 2008-06-04 2009-06-01 반도체 기판의 제조방법 Expired - Fee Related KR101642335B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2008-146914 2008-06-04
JP2008146914 2008-06-04

Publications (2)

Publication Number Publication Date
KR20090127065A KR20090127065A (ko) 2009-12-09
KR101642335B1 true KR101642335B1 (ko) 2016-07-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090047957A Expired - Fee Related KR101642335B1 (ko) 2008-06-04 2009-06-01 반도체 기판의 제조방법

Country Status (5)

Country Link
US (1) US7883988B2 (https=)
JP (1) JP5554014B2 (https=)
KR (1) KR101642335B1 (https=)
CN (1) CN101599453B (https=)
TW (1) TWI445060B (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102077318B (zh) * 2008-06-26 2013-03-27 株式会社Ihi 激光退火方法及装置
JP5540476B2 (ja) * 2008-06-30 2014-07-02 株式会社Ｉｈｉ レーザアニール装置
US8907258B2 (en) * 2010-04-08 2014-12-09 Ncc Nano, Llc Apparatus for providing transient thermal profile processing on a moving substrate
WO2012014786A1 (en) * 2010-07-30 2012-02-02 Semiconductor Energy Laboratory Co., Ltd. Semicondcutor device and manufacturing method thereof
EP2490073B1 (en) 2011-02-18 2015-09-23 ASML Netherlands BV Substrate holder, lithographic apparatus, and method of manufacturing a substrate holder
US10150230B2 (en) * 2011-04-08 2018-12-11 Ncc Nano, Llc Method for drying thin films in an energy efficient manner
EP3683627A1 (en) 2012-02-03 2020-07-22 ASML Netherlands B.V. Substrate holder and lithographic apparatus
US20130344688A1 (en) * 2012-06-20 2013-12-26 Zhiyuan Ye Atomic Layer Deposition with Rapid Thermal Treatment
US9496257B2 (en) 2014-06-30 2016-11-15 International Business Machines Corporation Removal of semiconductor growth defects
US11469079B2 (en) * 2017-03-14 2022-10-11 Lam Research Corporation Ultrahigh selective nitride etch to form FinFET devices
JP6421901B1 (ja) 2018-03-26 2018-11-14 三菱電機株式会社 半導体装置の製造方法
US20220234957A1 (en) * 2019-03-01 2022-07-28 Kyocera Corporation Ceramic structure and supporting mechanism which is provided with said ceramic structure

Citations (3)

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JP2000331899A (ja) * 1999-05-21 2000-11-30 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
JP2005142344A (ja) * 2003-11-06 2005-06-02 Toshiba Corp 半導体装置の製造方法および半導体製造装置
JP2006216661A (ja) 2005-02-02 2006-08-17 Sumco Corp 半導体ウェーハの製造方法

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JPS6235512A (ja) 1985-08-09 1987-02-16 Agency Of Ind Science & Technol 半導体単結晶薄膜の製造方法
JPH05218367A (ja) 1992-02-03 1993-08-27 Sharp Corp 多結晶シリコン薄膜用基板および多結晶シリコン薄膜の作製方法
JPH10275905A (ja) * 1997-03-31 1998-10-13 Mitsubishi Electric Corp シリコンウェーハの製造方法およびシリコンウェーハ
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH1197379A (ja) 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4379943B2 (ja) 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
JP4529036B2 (ja) * 1999-09-24 2010-08-25 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体用薄膜ウェハの製造方法
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
TWI313059B (https=) * 2000-12-08 2009-08-01 Sony Corporatio
JP2003209054A (ja) * 2001-11-12 2003-07-25 Dainippon Screen Mfg Co Ltd 基板の熱処理方法および熱処理装置
JP4342429B2 (ja) * 2004-02-09 2009-10-14 株式会社東芝 半導体装置の製造方法
JP3910603B2 (ja) * 2004-06-07 2007-04-25 株式会社東芝 熱処理装置、熱処理方法及び半導体装置の製造方法
JP4594121B2 (ja) 2005-02-03 2010-12-08 信越化学工業株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US7829436B2 (en) * 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
KR100972213B1 (ko) * 2005-12-27 2010-07-26 신에쓰 가가꾸 고교 가부시끼가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
JP2008112848A (ja) * 2006-10-30 2008-05-15 Shin Etsu Chem Co Ltd 単結晶シリコン太陽電池の製造方法及び単結晶シリコン太陽電池

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000331899A (ja) * 1999-05-21 2000-11-30 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
JP2005142344A (ja) * 2003-11-06 2005-06-02 Toshiba Corp 半導体装置の製造方法および半導体製造装置
JP2006216661A (ja) 2005-02-02 2006-08-17 Sumco Corp 半導体ウェーハの製造方法

Also Published As

Publication number Publication date
US20090305483A1 (en) 2009-12-10
CN101599453A (zh) 2009-12-09
JP2010016356A (ja) 2010-01-21
TW201017729A (en) 2010-05-01
CN101599453B (zh) 2013-10-16
TWI445060B (zh) 2014-07-11
JP5554014B2 (ja) 2014-07-23
KR20090127065A (ko) 2009-12-09
US7883988B2 (en) 2011-02-08

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