KR101638184B1 - 비오티 장치 및 이를 포함하는 테스트 시스템 - Google Patents
비오티 장치 및 이를 포함하는 테스트 시스템 Download PDFInfo
- Publication number
- KR101638184B1 KR101638184B1 KR1020090109438A KR20090109438A KR101638184B1 KR 101638184 B1 KR101638184 B1 KR 101638184B1 KR 1020090109438 A KR1020090109438 A KR 1020090109438A KR 20090109438 A KR20090109438 A KR 20090109438A KR 101638184 B1 KR101638184 B1 KR 101638184B1
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- test
- signals
- determination
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/54—Arrangements for designing test circuits, e.g. design for test [DFT] tools
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090109438A KR101638184B1 (ko) | 2009-11-13 | 2009-11-13 | 비오티 장치 및 이를 포함하는 테스트 시스템 |
| US12/900,748 US8604813B2 (en) | 2009-11-13 | 2010-10-08 | Built-off test device and test system including the same |
| JP2010238361A JP2011107132A (ja) | 2009-11-13 | 2010-10-25 | Bot装置及びこれを含むテストシステム |
| US14/084,224 US9285415B2 (en) | 2009-11-13 | 2013-11-19 | Built-off test device and test system including the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090109438A KR101638184B1 (ko) | 2009-11-13 | 2009-11-13 | 비오티 장치 및 이를 포함하는 테스트 시스템 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20110052777A KR20110052777A (ko) | 2011-05-19 |
| KR101638184B1 true KR101638184B1 (ko) | 2016-07-21 |
Family
ID=44010858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020090109438A Expired - Fee Related KR101638184B1 (ko) | 2009-11-13 | 2009-11-13 | 비오티 장치 및 이를 포함하는 테스트 시스템 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US8604813B2 (https=) |
| JP (1) | JP2011107132A (https=) |
| KR (1) | KR101638184B1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190140561A (ko) * | 2018-06-12 | 2019-12-20 | 삼성전자주식회사 | 테스트 인터페이스 보드, 이를 포함하는 테스트 시스템 및 이의 동작 방법 |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101638184B1 (ko) * | 2009-11-13 | 2016-07-21 | 삼성전자주식회사 | 비오티 장치 및 이를 포함하는 테스트 시스템 |
| DE102012104778A1 (de) * | 2012-06-01 | 2013-12-05 | Dspace Digital Signal Processing And Control Engineering Gmbh | Vorrichtung zum Testen einer elektrischen Komponente |
| KR102377362B1 (ko) | 2015-07-08 | 2022-03-23 | 삼성전자주식회사 | 보조 테스트 장치, 그것을 포함하는 테스트 보드 및 그것의 테스트 방법 |
| KR102329802B1 (ko) * | 2015-07-23 | 2021-11-22 | 삼성전자주식회사 | 테스트 인터페이스 보드, 테스트 장비, 테스트 시스템 및 테스트 방법 |
| KR102425472B1 (ko) * | 2015-08-06 | 2022-07-28 | 에스케이하이닉스 주식회사 | 복수의 반도체 장치를 테스트할 수 있는 테스트 장치 및 시스템 |
| KR102409926B1 (ko) * | 2015-08-18 | 2022-06-16 | 삼성전자주식회사 | 테스트 장치 및 이를 포함하는 테스트 시스템 |
| KR102401093B1 (ko) * | 2015-09-17 | 2022-05-24 | 에스케이하이닉스 주식회사 | 반도체 메모리 및 이를 이용한 메모리 시스템 |
| CN105866663B (zh) * | 2016-06-03 | 2019-03-01 | 珠海格力电器股份有限公司 | 测试工装及测试系统 |
| CN111273157B (zh) * | 2020-02-24 | 2022-07-08 | 上海御渡半导体科技有限公司 | 一种芯片共享资源串行测试装置及方法 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008180616A (ja) | 2007-01-25 | 2008-08-07 | Kawasaki Microelectronics Kk | 半導体デバイスのテスト補助回路およびテスト方法 |
| JP2008224585A (ja) | 2007-03-15 | 2008-09-25 | Yokogawa Electric Corp | 半導体試験装置 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0454472A (ja) * | 1990-06-25 | 1992-02-21 | Oki Electric Ind Co Ltd | 半導体試験装置 |
| JPH0599989A (ja) * | 1991-10-07 | 1993-04-23 | Nec Corp | ゲートアレイ付ram用テスト回路 |
| JPH10240560A (ja) * | 1997-02-26 | 1998-09-11 | Toshiba Corp | 波形信号処理装置 |
| JPH11237433A (ja) | 1998-02-19 | 1999-08-31 | Ando Electric Co Ltd | 半導体デバイス試験装置及び半導体デバイス試験方法 |
| JP2001004716A (ja) * | 1999-06-24 | 2001-01-12 | Matsushita Electric Ind Co Ltd | Lsiの検査方法 |
| JP2001142733A (ja) * | 1999-11-18 | 2001-05-25 | Matsushita Electric Ind Co Ltd | 内部信号観測装置 |
| KR100441684B1 (ko) * | 2001-12-03 | 2004-07-27 | 삼성전자주식회사 | 반도체 집적 회로를 위한 테스트 장치 |
| JP2006030166A (ja) | 2004-06-18 | 2006-02-02 | Yokogawa Electric Corp | Icテスタ |
| JP2008145266A (ja) | 2006-12-11 | 2008-06-26 | Yokogawa Electric Corp | デバイステスタ |
| KR20100068670A (ko) * | 2008-12-15 | 2010-06-24 | 삼성전자주식회사 | 채널 스큐 보상 기능을 갖는 인터페이스 회로, 이를 구비한통신 시스템 및 채널 스큐 보상 방법 |
| KR101535228B1 (ko) * | 2009-05-13 | 2015-07-08 | 삼성전자주식회사 | 빌트 오프 테스트 장치 |
| KR101638184B1 (ko) * | 2009-11-13 | 2016-07-21 | 삼성전자주식회사 | 비오티 장치 및 이를 포함하는 테스트 시스템 |
-
2009
- 2009-11-13 KR KR1020090109438A patent/KR101638184B1/ko not_active Expired - Fee Related
-
2010
- 2010-10-08 US US12/900,748 patent/US8604813B2/en not_active Expired - Fee Related
- 2010-10-25 JP JP2010238361A patent/JP2011107132A/ja active Pending
-
2013
- 2013-11-19 US US14/084,224 patent/US9285415B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008180616A (ja) | 2007-01-25 | 2008-08-07 | Kawasaki Microelectronics Kk | 半導体デバイスのテスト補助回路およびテスト方法 |
| JP2008224585A (ja) | 2007-03-15 | 2008-09-25 | Yokogawa Electric Corp | 半導体試験装置 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190140561A (ko) * | 2018-06-12 | 2019-12-20 | 삼성전자주식회사 | 테스트 인터페이스 보드, 이를 포함하는 테스트 시스템 및 이의 동작 방법 |
| KR102583174B1 (ko) * | 2018-06-12 | 2023-09-26 | 삼성전자주식회사 | 테스트 인터페이스 보드, 이를 포함하는 테스트 시스템 및 이의 동작 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011107132A (ja) | 2011-06-02 |
| KR20110052777A (ko) | 2011-05-19 |
| US9285415B2 (en) | 2016-03-15 |
| US8604813B2 (en) | 2013-12-10 |
| US20140074423A1 (en) | 2014-03-13 |
| US20110115517A1 (en) | 2011-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101638184B1 (ko) | 비오티 장치 및 이를 포함하는 테스트 시스템 | |
| US8423315B2 (en) | Digital waveform generation and measurement in automated test equipment | |
| EP0130610B1 (en) | System data path stressing | |
| KR20080069393A (ko) | 메모리 소자의 페일 비트 검증 회로 및 검증 방법 | |
| US6331958B2 (en) | Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test | |
| US6807116B2 (en) | Semiconductor circuit device capable of accurately testing embedded memory | |
| KR100411469B1 (ko) | 동기형반도체메모리장치 | |
| US5869983A (en) | Method and apparatus for controlling compensated buffers | |
| US20030120989A1 (en) | Method and circuit to implement double data rate testing | |
| US20090174425A1 (en) | Test circuit for a semiconductor integrated circuit | |
| KR100513406B1 (ko) | 반도체 시험장치 | |
| US8341477B2 (en) | Test board having a plurality of test modules and a test system having the same | |
| US7783942B2 (en) | Integrated circuit device with built-in self test (BIST) circuit | |
| JP2008097699A (ja) | 半導体記憶装置 | |
| US7948912B2 (en) | Semiconductor integrated circuit with test mode | |
| KR100851914B1 (ko) | 반도체 장치 | |
| US9207281B2 (en) | Channel control circuit and semiconductor device having the same | |
| KR100355232B1 (ko) | 지연펄스발생회로를 구비하는 반도체 메모리 장치 | |
| US8754667B2 (en) | Semiconductor device test method and semiconductor device | |
| KR100997436B1 (ko) | 반도체 메모리장치의 펄스생성회로 및 방법 | |
| KR100706241B1 (ko) | 테스트 핀을 사용하지 않고 테스트할 수 있는 시스템-온-칩 및 테스트 방법 | |
| JP2000090700A (ja) | 半導体集積回路装置 | |
| JP2008287462A (ja) | エミュレータ及びエミュレーション方法 | |
| Low | An integrated low-cost functional tester for CMOS logic | |
| JP2019114313A (ja) | 半導体集積回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| A201 | Request for examination | ||
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U11-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9 |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20250705 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| H13 | Ip right lapsed |
Free format text: ST27 STATUS EVENT CODE: N-4-6-H10-H13-OTH-PC1903 (AS PROVIDED BY THE NATIONAL OFFICE); TERMINATION CATEGORY : DEFAULT_OF_REGISTRATION_FEE Effective date: 20250705 |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20250705 |