KR101567928B1 - 발진기 기반 주파수 동기 루프 - Google Patents

발진기 기반 주파수 동기 루프 Download PDF

Info

Publication number
KR101567928B1
KR101567928B1 KR1020147015523A KR20147015523A KR101567928B1 KR 101567928 B1 KR101567928 B1 KR 101567928B1 KR 1020147015523 A KR1020147015523 A KR 1020147015523A KR 20147015523 A KR20147015523 A KR 20147015523A KR 101567928 B1 KR101567928 B1 KR 101567928B1
Authority
KR
South Korea
Prior art keywords
controlled oscillator
digitally controlled
time period
oscillation
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020147015523A
Other languages
English (en)
Korean (ko)
Other versions
KR20140100509A (ko
Inventor
마틴 세인트-라우렌트
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20140100509A publication Critical patent/KR20140100509A/ko
Application granted granted Critical
Publication of KR101567928B1 publication Critical patent/KR101567928B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Apparatuses For Generation Of Mechanical Vibrations (AREA)
KR1020147015523A 2011-11-08 2012-11-07 발진기 기반 주파수 동기 루프 Expired - Fee Related KR101567928B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/291,206 2011-11-08
US13/291,206 US8994458B2 (en) 2011-11-08 2011-11-08 Oscillator based frequency locked loop
PCT/US2012/063967 WO2013070783A2 (en) 2011-11-08 2012-11-07 Oscillator based frequency locked loop

Publications (2)

Publication Number Publication Date
KR20140100509A KR20140100509A (ko) 2014-08-14
KR101567928B1 true KR101567928B1 (ko) 2015-11-10

Family

ID=47326319

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147015523A Expired - Fee Related KR101567928B1 (ko) 2011-11-08 2012-11-07 발진기 기반 주파수 동기 루프

Country Status (8)

Country Link
US (1) US8994458B2 (https=)
EP (1) EP2777156B1 (https=)
JP (2) JP5917709B2 (https=)
KR (1) KR101567928B1 (https=)
CN (1) CN103947115B (https=)
CY (1) CY1116856T1 (https=)
IN (1) IN2014CN03165A (https=)
WO (1) WO2013070783A2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994458B2 (en) * 2011-11-08 2015-03-31 Qualcomm Incorporated Oscillator based frequency locked loop
US9548747B2 (en) 2015-05-15 2017-01-17 Intel Corporation Glitch-free digitally controlled oscillator code update
US10050634B1 (en) * 2017-02-10 2018-08-14 Apple Inc. Quantization noise cancellation for fractional-N phased-locked loop
TWI656742B (zh) * 2018-07-31 2019-04-11 慧榮科技股份有限公司 振盪器裝置
EP4699223A1 (en) * 2023-04-21 2026-02-25 Analog Devices International Unlimited Company Circuits and methods for generating an oscillator signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7705687B1 (en) * 2006-12-21 2010-04-27 Marvell International, Ltd. Digital ring oscillator

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124333A (ja) * 1982-01-20 1983-07-23 Hitachi Ltd 発振装置
JP2953821B2 (ja) * 1991-06-24 1999-09-27 日本電気アイシーマイコンシステム株式会社 リングオシレータ回路
US5805909A (en) 1995-08-03 1998-09-08 Texas Instruments Incorporated Microprocessors or microcontroller utilizing FLL clock having a reduced power state
US5900757A (en) 1996-05-01 1999-05-04 Sun Microsystems, Inc. Clock stopping schemes for data buffer
CN1111953C (zh) * 1998-04-25 2003-06-18 普诚科技股份有限公司 振荡器内建于集成电路内的频率调整方法与装置
JP3633374B2 (ja) * 1999-06-16 2005-03-30 株式会社デンソー クロック制御回路
US6625559B1 (en) 2000-05-01 2003-09-23 Hewlett-Packard Development Company, L.P. System and method for maintaining lock of a phase locked loop feedback during clock halt
US6504442B2 (en) * 2001-04-05 2003-01-07 International Busisness Machines Corporation Digitally controlled oscillator with recovery from sleep mode
US6809605B2 (en) * 2002-01-10 2004-10-26 Fujitsu Limited Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit
CN100470656C (zh) * 2003-10-31 2009-03-18 宇田控股有限公司 摆动时钟信号的产生方法和产生装置
ITMI20050138A1 (it) 2005-01-31 2006-08-01 St Microelectronics Srl Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio
US7605666B2 (en) * 2007-08-22 2009-10-20 Chris Karabatsos High frequency digital oscillator-on-demand with synchronization
JP4618642B2 (ja) * 2005-05-17 2011-01-26 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7667549B2 (en) * 2007-04-26 2010-02-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US7746178B1 (en) 2007-12-21 2010-06-29 Rf Micro Devices, Inc. Digital offset phase-locked loop
JP5290589B2 (ja) 2008-02-06 2013-09-18 ルネサスエレクトロニクス株式会社 半導体集積回路
US7764132B2 (en) 2008-07-30 2010-07-27 International Business Machines Corporation All digital frequency-locked loop circuit method for clock generation in multicore microprocessor systems
CN102130667A (zh) * 2011-01-18 2011-07-20 浙江大学 一种数字真随机振荡信号发生器
US8471614B2 (en) * 2011-06-14 2013-06-25 Globalfoundries Singapore Pte. Ltd. Digital phase locked loop system and method
US8994458B2 (en) * 2011-11-08 2015-03-31 Qualcomm Incorporated Oscillator based frequency locked loop

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7705687B1 (en) * 2006-12-21 2010-04-27 Marvell International, Ltd. Digital ring oscillator

Also Published As

Publication number Publication date
WO2013070783A2 (en) 2013-05-16
KR20140100509A (ko) 2014-08-14
CN103947115B (zh) 2018-04-17
CY1116856T1 (el) 2017-04-05
JP6438429B2 (ja) 2018-12-12
EP2777156B1 (en) 2015-08-05
EP2777156A2 (en) 2014-09-17
JP2016158275A (ja) 2016-09-01
US20130113530A1 (en) 2013-05-09
US8994458B2 (en) 2015-03-31
WO2013070783A3 (en) 2013-11-28
JP5917709B2 (ja) 2016-05-18
IN2014CN03165A (https=) 2015-07-31
CN103947115A (zh) 2014-07-23
JP2015502700A (ja) 2015-01-22

Similar Documents

Publication Publication Date Title
KR101894868B1 (ko) 회로의 주파수 범위 확장 및 오버-클록킹 또는 언더-클록킹을 위한 장치 및 방법
US9628089B1 (en) Supply voltage tracking clock generator in adaptive clock distribution systems
KR101567928B1 (ko) 발진기 기반 주파수 동기 루프
US9778676B2 (en) Power distribution network (PDN) droop/overshoot mitigation in dynamic frequency scaling
JP2007221750A (ja) パワーダウンモードの間、周期的にロッキング動作を実行する機能を有するdll及びそのロッキング動作方法
JP2011188077A (ja) 位相同期回路及びその制御方法
JP7818608B2 (ja) Pll回路および送信システム
JP2010056594A (ja) パルス生成装置
CN103843264A (zh) 用于执行扩频时钟控制的装置和方法
KR101406087B1 (ko) 분주기 및 분주기의 분주 방법
US8427252B2 (en) Oscillators with low power mode of operation
TWI436596B (zh) 具有自我校準的延遲鎖相迴路系統
JP2006191372A (ja) デュアルループpllおよび逓倍クロック発生装置
CN111565041B (zh) 一种快速起振电路及快速起振方法
KR100996176B1 (ko) 반도체 메모리 장치 및 그에 구비되는 지연 고정 루프의 제어 방법
CN120200599A (zh) 切换电路以及时脉供给电路
JP5567389B2 (ja) クロック発生回路
TWI424305B (zh) 時脈產生器、時脈產生方法、與行動通訊裝置
JP2008060895A (ja) 位相同期回路
US10560053B2 (en) Digital fractional frequency divider
KR101418519B1 (ko) 분주기 및 분주기의 분주 방법
JP2004086645A (ja) マイクロコンピュータ
CN120200587A (zh) 控制装置及微控制电路
JP2009284196A (ja) 発振回路、発振回路を備えた電子機器及び発振回路の制御方法
JPH10200397A (ja) クロック生成回路、pll及びこのpllを含む半導体集積回路

Legal Events

Date Code Title Description
A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20180928

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20190924

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20201105

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20201105