ITMI20050138A1 - Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio - Google Patents

Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio

Info

Publication number
ITMI20050138A1
ITMI20050138A1 IT000138A ITMI20050138A ITMI20050138A1 IT MI20050138 A1 ITMI20050138 A1 IT MI20050138A1 IT 000138 A IT000138 A IT 000138A IT MI20050138 A ITMI20050138 A IT MI20050138A IT MI20050138 A1 ITMI20050138 A1 IT MI20050138A1
Authority
IT
Italy
Prior art keywords
lock loop
fll
brief
system frequency
locking time
Prior art date
Application number
IT000138A
Other languages
English (en)
Inventor
Carmelo Burgio
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000138A priority Critical patent/ITMI20050138A1/it
Priority to US11/344,972 priority patent/US8325853B2/en
Publication of ITMI20050138A1 publication Critical patent/ITMI20050138A1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
IT000138A 2005-01-31 2005-01-31 Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio ITMI20050138A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000138A ITMI20050138A1 (it) 2005-01-31 2005-01-31 Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio
US11/344,972 US8325853B2 (en) 2005-01-31 2006-01-31 Fully digital frequency locked loop/phase locked loop method and system having a short locking time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000138A ITMI20050138A1 (it) 2005-01-31 2005-01-31 Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio

Publications (1)

Publication Number Publication Date
ITMI20050138A1 true ITMI20050138A1 (it) 2006-08-01

Family

ID=36970880

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000138A ITMI20050138A1 (it) 2005-01-31 2005-01-31 Metodo e sistema fll-pll frequency lock loop-phase lock loop completamente digitale a brevissimo tempo di bloccaggio

Country Status (2)

Country Link
US (1) US8325853B2 (it)
IT (1) ITMI20050138A1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4186083B2 (ja) * 2006-10-03 2008-11-26 日本電気株式会社 クロック同期回路
US8428212B2 (en) * 2008-01-30 2013-04-23 Intel Mobile Communications GmbH Frequency synthesis using upconversion PLL processes
KR101109198B1 (ko) 2009-01-22 2012-01-30 서울대학교산학협력단 디지털 클록 데이터 복원기 및 이를 적용한 트랜시버
US9134813B2 (en) 2009-03-31 2015-09-15 Koninklijke Philips N.V. System for demodulating a signal
US8994458B2 (en) 2011-11-08 2015-03-31 Qualcomm Incorporated Oscillator based frequency locked loop
FR2992073B1 (fr) 2012-06-19 2014-07-11 Commissariat Energie Atomique Dispositif d'alimentation d'un circuit electronique
CN103427975B (zh) * 2013-07-26 2017-08-01 硅谷数模半导体（北京）有限公司 数据流采样频率调节方法和采样装置
US9455721B2 (en) * 2014-10-09 2016-09-27 Texas Instruments Incorporated FLL oscillator/clock with an FLL control loop including a switched capacitor resistive divider
CN107544617A (zh) * 2017-07-27 2018-01-05 宏祐图像科技(上海)有限公司 一种用于serdes芯片的本地时钟产生方法及电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2281522C (en) * 1999-09-10 2004-12-07 Philsar Electronics Inc. Delta-sigma based two-point angle modulation scheme
FI108688B (fi) * 2000-06-30 2002-02-28 Nokia Corp Menetelmä ja järjestely taajuuden asettamiseksi
US7170964B2 (en) * 2002-08-07 2007-01-30 Broadcom Corporation Transition insensitive timing recovery method and apparatus
US7177611B2 (en) * 2004-07-07 2007-02-13 Texas Instruments Incorporated Hybrid control of phase locked loops
US7330079B2 (en) * 2005-10-31 2008-02-12 Texas Instruments Incorporated Method and apparatus for rapid local oscillator frequency calibration

Also Published As

Publication number Publication date
US20060203937A1 (en) 2006-09-14
US8325853B2 (en) 2012-12-04

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