DE602004009620D1 - Digitaler Phasenregelkreis und Verfahren - Google Patents

Digitaler Phasenregelkreis und Verfahren

Info

Publication number
DE602004009620D1
DE602004009620D1 DE602004009620T DE602004009620T DE602004009620D1 DE 602004009620 D1 DE602004009620 D1 DE 602004009620D1 DE 602004009620 T DE602004009620 T DE 602004009620T DE 602004009620 T DE602004009620 T DE 602004009620T DE 602004009620 D1 DE602004009620 D1 DE 602004009620D1
Authority
DE
Germany
Prior art keywords
locked loop
digital phase
digital
phase
locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004009620T
Other languages
English (en)
Inventor
Ramanand Venkata
Chong H Lee
Henry Lui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of DE602004009620D1 publication Critical patent/DE602004009620D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE602004009620T 2003-01-21 2004-01-20 Digitaler Phasenregelkreis und Verfahren Expired - Lifetime DE602004009620D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/349,541 US7138837B2 (en) 2003-01-21 2003-01-21 Digital phase locked loop circuitry and methods

Publications (1)

Publication Number Publication Date
DE602004009620D1 true DE602004009620D1 (de) 2007-12-06

Family

ID=32594930

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004009620T Expired - Lifetime DE602004009620D1 (de) 2003-01-21 2004-01-20 Digitaler Phasenregelkreis und Verfahren

Country Status (4)

Country Link
US (1) US7138837B2 (de)
EP (1) EP1441443B1 (de)
CN (1) CN100483946C (de)
DE (1) DE602004009620D1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
CA2415598A1 (en) * 2002-01-11 2003-07-11 Nec Corporation Multiplex communication system and method
US7046174B1 (en) 2003-06-03 2006-05-16 Altera Corporation Byte alignment for serial data receiver
US6980023B1 (en) * 2003-09-22 2005-12-27 Altera Corporation Dynamically adjustable signal detector
US7443922B1 (en) 2003-11-14 2008-10-28 Altera Corporation Circuitry for padded communication protocols
US7940877B1 (en) 2003-11-26 2011-05-10 Altera Corporation Signal edge detection circuitry and methods
US7143312B1 (en) 2003-12-17 2006-11-28 Altera Corporation Alignment of recovered clock with data signal
US7196557B1 (en) * 2004-01-13 2007-03-27 Altera Corporation Multitap fractional baud period pre-emphasis for data transmission
US7773668B1 (en) 2004-01-21 2010-08-10 Altera Corporation Adaptive equalization methods and apparatus for programmable logic devices
US7509562B1 (en) 2004-04-09 2009-03-24 Altera Corporation Maintaining data integrity for extended drop outs across high-speed serial links
US7440532B1 (en) 2004-04-21 2008-10-21 Altera Corporation Bit slip circuitry for serial data signals
US7453968B2 (en) * 2004-05-18 2008-11-18 Altera Corporation Dynamic phase alignment methods and apparatus
US7598779B1 (en) 2004-10-08 2009-10-06 Altera Corporation Dual-mode LVDS/CML transmitter methods and apparatus
US7240133B1 (en) 2004-10-12 2007-07-03 Altera Corporation Reduced-area architecture for padded-protocol interface
US7151470B1 (en) 2004-10-20 2006-12-19 Altera Corporation Data converter with multiple conversions for padded-protocol interface
US7064685B1 (en) 2004-10-20 2006-06-20 Altera Corporation Data converter with reduced component count for padded-protocol interface
US7680232B2 (en) * 2005-01-21 2010-03-16 Altera Corporation Method and apparatus for multi-mode clock data recovery
CN100379193C (zh) * 2005-03-02 2008-04-02 威盛电子股份有限公司 在时钟数据再生系统中时钟的撷取方法和撷取电路
US7681063B2 (en) * 2005-03-30 2010-03-16 Infineon Technologies Ag Clock data recovery circuit with circuit loop disablement
US7365570B2 (en) * 2005-05-25 2008-04-29 Micron Technology, Inc. Pseudo-differential output driver with high immunity to noise and jitter
US7743288B1 (en) * 2005-06-01 2010-06-22 Altera Corporation Built-in at-speed bit error ratio tester
US7265587B1 (en) 2005-07-26 2007-09-04 Altera Corporation LVDS output buffer pre-emphasis methods and apparatus
US8743943B2 (en) 2005-07-28 2014-06-03 Altera Corporation High-speed data reception circuitry and methods
US7804892B1 (en) * 2006-02-03 2010-09-28 Altera Corporation Circuitry for providing programmable decision feedback equalization
US8122275B2 (en) * 2006-08-24 2012-02-21 Altera Corporation Write-leveling implementation in programmable logic devices
US7460040B1 (en) * 2007-05-29 2008-12-02 Altera Corporation High-speed serial interface architecture for a programmable logic device
US7733118B2 (en) * 2008-03-06 2010-06-08 Micron Technology, Inc. Devices and methods for driving a signal off an integrated circuit
US20100266081A1 (en) * 2009-04-21 2010-10-21 International Business Machines Corporation System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation
US8222920B2 (en) * 2009-12-18 2012-07-17 Meta Systems Dynamic phase alignment
US8896357B2 (en) * 2012-05-04 2014-11-25 Finisar Corporation Integrated processor and CDR circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6125157A (en) 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6100735A (en) * 1998-11-19 2000-08-08 Centillium Communications, Inc. Segmented dual delay-locked loop for precise variable-phase clock generation
IT1311463B1 (it) 1999-12-31 2002-03-12 Cit Alcatel Metodo di recupero del segnale d'orologio in un sistema ditelecomunicazioni e relativo circuito.
US7227918B2 (en) 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US6650140B2 (en) 2001-03-19 2003-11-18 Altera Corporation Programmable logic device with high speed serial interface circuitry
DE10130122B4 (de) 2001-06-22 2006-01-19 Infineon Technologies Ag Verzögerungsregelkreis
TWI237946B (en) 2001-07-06 2005-08-11 Via Tech Inc Clock output circuit free of glitch and method thereof
US6750675B2 (en) 2001-09-17 2004-06-15 Altera Corporation Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
US7397788B2 (en) * 2002-07-02 2008-07-08 Emulex Design & Manufacturing Corporation Methods and apparatus for device zoning in fibre channel arbitrated loop systems

Also Published As

Publication number Publication date
CN1518228A (zh) 2004-08-04
CN100483946C (zh) 2009-04-29
EP1441443A2 (de) 2004-07-28
EP1441443B1 (de) 2007-10-24
EP1441443A3 (de) 2004-10-06
US20040140837A1 (en) 2004-07-22
US7138837B2 (en) 2006-11-21

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Legal Events

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