FI20065365A0 - Vaihelukitussilmukan virittäminen ja elektroniikkalaite - Google Patents

Vaihelukitussilmukan virittäminen ja elektroniikkalaite

Info

Publication number
FI20065365A0
FI20065365A0 FI20065365A FI20065365A FI20065365A0 FI 20065365 A0 FI20065365 A0 FI 20065365A0 FI 20065365 A FI20065365 A FI 20065365A FI 20065365 A FI20065365 A FI 20065365A FI 20065365 A0 FI20065365 A0 FI 20065365A0
Authority
FI
Finland
Prior art keywords
electronic device
phase lock
lock loop
loop tuning
tuning
Prior art date
Application number
FI20065365A
Other languages
English (en)
Swedish (sv)
Inventor
Juha Hallivuori
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Priority to FI20065365A priority Critical patent/FI20065365A0/fi
Publication of FI20065365A0 publication Critical patent/FI20065365A0/fi
Priority to US11/477,765 priority patent/US7508244B2/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
FI20065365A 2006-05-31 2006-05-31 Vaihelukitussilmukan virittäminen ja elektroniikkalaite FI20065365A0 (fi)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI20065365A FI20065365A0 (fi) 2006-05-31 2006-05-31 Vaihelukitussilmukan virittäminen ja elektroniikkalaite
US11/477,765 US7508244B2 (en) 2006-05-31 2006-06-30 Tuning of a phase-locked loop, and an electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20065365A FI20065365A0 (fi) 2006-05-31 2006-05-31 Vaihelukitussilmukan virittäminen ja elektroniikkalaite

Publications (1)

Publication Number Publication Date
FI20065365A0 true FI20065365A0 (fi) 2006-05-31

Family

ID=36540068

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20065365A FI20065365A0 (fi) 2006-05-31 2006-05-31 Vaihelukitussilmukan virittäminen ja elektroniikkalaite

Country Status (2)

Country Link
US (1) US7508244B2 (fi)
FI (1) FI20065365A0 (fi)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100869227B1 (ko) * 2007-04-04 2008-11-18 삼성전자주식회사 프리 캘리브레이션 모드를 가진 위상동기루프 회로 및위상동기루프 회로의 프리 캘리브레이션 방법
US7817750B2 (en) * 2007-05-21 2010-10-19 Seiko Epson Corporation Radio receiver including a delay-locked loop (DLL) for phase adjustment
US9966965B2 (en) * 2016-06-10 2018-05-08 Silicon Laboratories Inc. Apparatus for low power signal generator and associated methods

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI113112B (fi) 2000-12-22 2004-02-27 Nokia Corp Menetelmä oskillaattorin säätämiseksi
US7015738B1 (en) * 2003-06-18 2006-03-21 Weixun Cao Direct modulation of a voltage-controlled oscillator (VCO) with adaptive gain control
US6952124B2 (en) * 2003-09-15 2005-10-04 Silicon Bridge, Inc. Phase locked loop circuit with self adjusted tuning hiep the pham
US7148760B2 (en) * 2004-12-30 2006-12-12 Nokia Corporation VCO gain tuning using voltage measurements and frequency iteration

Also Published As

Publication number Publication date
US7508244B2 (en) 2009-03-24
US20070279110A1 (en) 2007-12-06

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Legal Events

Date Code Title Description
FD Application lapsed