KR101503969B1 - 반도체 디바이스 형성 방법 - Google Patents

반도체 디바이스 형성 방법 Download PDF

Info

Publication number
KR101503969B1
KR101503969B1 KR1020117006359A KR20117006359A KR101503969B1 KR 101503969 B1 KR101503969 B1 KR 101503969B1 KR 1020117006359 A KR1020117006359 A KR 1020117006359A KR 20117006359 A KR20117006359 A KR 20117006359A KR 101503969 B1 KR101503969 B1 KR 101503969B1
Authority
KR
South Korea
Prior art keywords
precursor
aluminum
carbonitride
substrate
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020117006359A
Other languages
English (en)
Korean (ko)
Other versions
KR20110069015A (ko
Inventor
도시오 하세가와
게릿 제이 로이싱크
Original Assignee
도쿄엘렉트론가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 도쿄엘렉트론가부시키가이샤 filed Critical 도쿄엘렉트론가부시키가이샤
Publication of KR20110069015A publication Critical patent/KR20110069015A/ko
Application granted granted Critical
Publication of KR101503969B1 publication Critical patent/KR101503969B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/669—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020117006359A 2008-08-25 2009-08-22 반도체 디바이스 형성 방법 Expired - Fee Related KR101503969B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/197,756 US7985680B2 (en) 2008-08-25 2008-08-25 Method of forming aluminum-doped metal carbonitride gate electrodes
US12/197,756 2008-08-25
PCT/US2009/054707 WO2010027715A1 (en) 2008-08-25 2009-08-22 Method for forming aluminum-doped metal carbonitride gate electrodes

Publications (2)

Publication Number Publication Date
KR20110069015A KR20110069015A (ko) 2011-06-22
KR101503969B1 true KR101503969B1 (ko) 2015-03-24

Family

ID=41696772

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020117006359A Expired - Fee Related KR101503969B1 (ko) 2008-08-25 2009-08-22 반도체 디바이스 형성 방법

Country Status (7)

Country Link
US (1) US7985680B2 (https=)
JP (1) JP5529134B2 (https=)
KR (1) KR101503969B1 (https=)
CN (1) CN102132389B (https=)
DE (1) DE112009002118B4 (https=)
TW (1) TWI438832B (https=)
WO (1) WO2010027715A1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100102393A1 (en) * 2008-10-29 2010-04-29 Chartered Semiconductor Manufacturing, Ltd. Metal gate transistors
JP2014222723A (ja) * 2013-05-14 2014-11-27 独立行政法人産業技術総合研究所 電界効果型半導体装置及びその製造方法
US9552979B2 (en) * 2013-05-31 2017-01-24 Asm Ip Holding B.V. Cyclic aluminum nitride deposition in a batch reactor
US9224594B2 (en) 2013-11-18 2015-12-29 Intermolecular, Inc. Surface preparation with remote plasma
US9607888B2 (en) 2014-02-03 2017-03-28 Tokyo Electron Limited Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling
US10163644B2 (en) 2014-02-07 2018-12-25 Taiwan Semiconductor Manufacturing Company Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same
TWI556429B (zh) 2014-07-10 2016-11-01 台灣積體電路製造股份有限公司 積體電路裝置與其形成方法
DE102014119644B4 (de) 2014-07-10 2024-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Metalgatestapel mit TiAICN als Arbeitsfunktionsschicht und/oder Sperr/Benetzungsschicht und Verfahren
KR102216575B1 (ko) * 2014-10-23 2021-02-18 에이에스엠 아이피 홀딩 비.브이. 티타늄 알루미늄 및 탄탈륨 알루미늄 박막들
CN109285879B (zh) * 2017-07-20 2021-06-08 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10665685B2 (en) 2017-11-30 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication method thereof
JP2020056104A (ja) 2018-10-02 2020-04-09 エーエスエム アイピー ホールディング ビー．ブイ． 選択的パッシベーションおよび選択的堆積
US12482648B2 (en) 2018-10-02 2025-11-25 Asm Ip Holding B.V. Selective passivation and selective deposition
US11251261B2 (en) * 2019-05-17 2022-02-15 Micron Technology, Inc. Forming a barrier material on an electrode
US11456177B2 (en) * 2020-09-22 2022-09-27 Nanya Technology Corporation Method of manufacturing semiconductor device
TW202248447A (zh) * 2021-03-08 2022-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於形成包含有鋁、鈦、與碳之層的方法及系統

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766143A (ja) * 1993-08-25 1995-03-10 Sony Corp 半導体装置におけるバリアメタル層の形成方法
JPH11145077A (ja) * 1997-10-31 1999-05-28 Texas Instr Inc <Ti> 膜及びその製法
US20070059929A1 (en) * 2004-06-25 2007-03-15 Hag-Ju Cho Method of forming a tantalum carbon nitride layer and method of manufacturing a semiconductor device using the same
JP2008172227A (ja) * 2007-01-04 2008-07-24 Interuniv Micro Electronica Centrum Vzw 電子デバイスおよびその製造プロセス

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4116682A (en) 1976-12-27 1978-09-26 Polk Donald E Amorphous metal alloys and products thereof
US6445023B1 (en) 1999-03-16 2002-09-03 Micron Technology, Inc. Mixed metal nitride and boride barrier layers
US6627995B2 (en) 2000-03-03 2003-09-30 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US6455421B1 (en) 2000-07-31 2002-09-24 Applied Materials, Inc. Plasma treatment of tantalum nitride compound films formed by chemical vapor deposition
US6444263B1 (en) 2000-09-15 2002-09-03 Cvc Products, Inc. Method of chemical-vapor deposition of a material
US6630201B2 (en) 2001-04-05 2003-10-07 Angstron Systems, Inc. Adsorption process for atomic layer deposition
JP3963078B2 (ja) 2000-12-25 2007-08-22 株式会社高純度化学研究所 ターシャリーアミルイミドトリス（ジメチルアミド）タンタルとその製造方法及びそれを用いたｍｏｃｖｄ用原料溶液並びにそれを用いた窒化タンタル膜の形成方法
US6861334B2 (en) 2001-06-21 2005-03-01 Asm International, N.V. Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition
US7098131B2 (en) 2001-07-19 2006-08-29 Samsung Electronics Co., Ltd. Methods for forming atomic layers and thin films including tantalum nitride and devices including the same
KR100434697B1 (ko) 2001-09-05 2004-06-07 주식회사 하이닉스반도체 반도체소자의 제조방법
KR100805843B1 (ko) 2001-12-28 2008-02-21 에이에스엠지니텍코리아 주식회사 구리 배선 형성방법, 그에 따라 제조된 반도체 소자 및구리 배선 형성 시스템
JP3556206B2 (ja) 2002-07-15 2004-08-18 沖電気工業株式会社 金属配線の形成方法
US20040036129A1 (en) 2002-08-22 2004-02-26 Micron Technology, Inc. Atomic layer deposition of CMOS gates with variable work functions
JP2004095893A (ja) 2002-08-30 2004-03-25 Nec Electronics Corp 半導体記憶装置及びその制御方法と製造方法
US6955986B2 (en) 2003-03-27 2005-10-18 Asm International N.V. Atomic layer deposition methods for forming a multi-layer adhesion-barrier layer for integrated circuits
US7186446B2 (en) 2003-10-31 2007-03-06 International Business Machines Corporation Plasma enhanced ALD of tantalum nitride and bilayer
US20050221021A1 (en) 2004-03-31 2005-10-06 Tokyo Electron Limited Method and system for performing atomic layer deposition
US7453149B2 (en) 2004-08-04 2008-11-18 Taiwan Semiconductor Manufacturing Co., Ltd. Composite barrier layer
US7300869B2 (en) 2004-09-20 2007-11-27 Lsi Corporation Integrated barrier and seed layer for copper interconnect technology
US20060113675A1 (en) 2004-12-01 2006-06-01 Chung-Liang Chang Barrier material and process for Cu interconnect
US20060210723A1 (en) 2005-03-21 2006-09-21 Tokyo Electron Limited Plasma enhanced atomic layer deposition system and method
US7341959B2 (en) 2005-03-21 2008-03-11 Tokyo Electron Limited Plasma enhanced atomic layer deposition system and method
US8486845B2 (en) 2005-03-21 2013-07-16 Tokyo Electron Limited Plasma enhanced atomic layer deposition system and method
US7314835B2 (en) 2005-03-21 2008-01-01 Tokyo Electron Limited Plasma enhanced atomic layer deposition system and method
US8974868B2 (en) 2005-03-21 2015-03-10 Tokyo Electron Limited Post deposition plasma cleaning system and method
US7422636B2 (en) 2005-03-25 2008-09-09 Tokyo Electron Limited Plasma enhanced atomic layer deposition system having reduced contamination
US20060213437A1 (en) 2005-03-28 2006-09-28 Tokyo Electron Limited Plasma enhanced atomic layer deposition system
US20070059502A1 (en) 2005-05-05 2007-03-15 Applied Materials, Inc. Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer
US20060251872A1 (en) 2005-05-05 2006-11-09 Wang Jenn Y Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof
DE102005023122A1 (de) 2005-05-19 2006-11-23 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Schichtstapel und Verfahren
US7550385B2 (en) 2005-09-30 2009-06-23 Intel Corporation Amine-free deposition of metal-nitride films
CN100565930C (zh) * 2005-10-14 2009-12-02 株式会社东芝 非易失性半导体存储装置
US7897217B2 (en) 2005-11-18 2011-03-01 Tokyo Electron Limited Method and system for performing plasma enhanced atomic layer deposition
US20070116888A1 (en) 2005-11-18 2007-05-24 Tokyo Electron Limited Method and system for performing different deposition processes within a single chamber
US7727912B2 (en) 2006-03-20 2010-06-01 Tokyo Electron Limited Method of light enhanced atomic layer deposition
US7645484B2 (en) 2006-03-31 2010-01-12 Tokyo Electron Limited Method of forming a metal carbide or metal carbonitride film having improved adhesion
JP5114714B2 (ja) 2006-09-13 2013-01-09 エントーネ ゲーエムベーハー 導電性重合体と貴金属／準貴金属の塗膜を持つ物品およびその製造方法
US20080132050A1 (en) 2006-12-05 2008-06-05 Lavoie Adrien R Deposition process for graded cobalt barrier layers
US20080141937A1 (en) 2006-12-19 2008-06-19 Tokyo Electron Limited Method and system for controlling a vapor delivery system
JP2008205012A (ja) * 2007-02-16 2008-09-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7829158B2 (en) 2007-05-07 2010-11-09 Tokyo Electron Limited Method for depositing a barrier layer on a low dielectric constant material
JP5513767B2 (ja) 2008-06-25 2014-06-04 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置および半導体装置
US8557702B2 (en) * 2009-02-02 2013-10-15 Asm America, Inc. Plasma-enhanced atomic layers deposition of conductive material over dielectric layers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766143A (ja) * 1993-08-25 1995-03-10 Sony Corp 半導体装置におけるバリアメタル層の形成方法
JPH11145077A (ja) * 1997-10-31 1999-05-28 Texas Instr Inc <Ti> 膜及びその製法
US20070059929A1 (en) * 2004-06-25 2007-03-15 Hag-Ju Cho Method of forming a tantalum carbon nitride layer and method of manufacturing a semiconductor device using the same
JP2008172227A (ja) * 2007-01-04 2008-07-24 Interuniv Micro Electronica Centrum Vzw 電子デバイスおよびその製造プロセス

Also Published As

Publication number Publication date
JP5529134B2 (ja) 2014-06-25
DE112009002118T5 (de) 2011-07-28
CN102132389B (zh) 2013-07-10
US7985680B2 (en) 2011-07-26
DE112009002118B4 (de) 2013-03-07
KR20110069015A (ko) 2011-06-22
WO2010027715A1 (en) 2010-03-11
TW201021099A (en) 2010-06-01
US20100048009A1 (en) 2010-02-25
CN102132389A (zh) 2011-07-20
JP2012501093A (ja) 2012-01-12
TWI438832B (zh) 2014-05-21

Similar Documents

Publication Publication Date Title
KR101503969B1 (ko) 반도체 디바이스 형성 방법
KR102662958B1 (ko) 원자층 퇴적에 의한 기판 상의 전이 금속 질화물 막의 형성 방법 및 관련 반도체 소자 구조물들
KR102712252B1 (ko) 금속 카바이드 재료를 포함하는 구조물, 그 구조물을 포함하는 디바이스, 및 그의 형성 방법
TWI730987B (zh) ＮｂＭＣ層
US7776733B2 (en) Method for depositing titanium nitride films for semiconductor manufacturing
US7531452B2 (en) Strained metal silicon nitride films and method of forming
US7772073B2 (en) Semiconductor device containing a buried threshold voltage adjustment layer and method of forming
CN101460658B (zh) 通过原子层沉积形成混合稀土氧化物和铝酸盐薄膜的方法
EP2011145B1 (en) Method of forming films of mixed rare earth aluminates by atomic layer deposition
US9136180B2 (en) Process for depositing electrode with high effective work function
US20110165328A1 (en) Method of forming mixed rare earth oxide and aluminate films by atomic layer deposition
TW202538087A (zh) 生長低電阻率含金屬膜之方法
US7494937B2 (en) Strained metal silicon nitride films and method of forming
KR20250053037A (ko) 반응 챔버에서 주기적 증착 공정에 의해 기판 상에 하프늄 란타늄 산화물 막을 증착하는 방법
JP2023537931A (ja) 不純物を含まない金属合金膜を形成するための方法
US7713868B2 (en) Strained metal nitride films and method of forming
US7589020B2 (en) Method for depositing titanium nitride films for semiconductor manufacturing
US8178446B2 (en) Strained metal nitride films and method of forming
US7759746B2 (en) Semiconductor device with gate dielectric containing aluminum and mixed rare earth elements
CN114628232A (zh) 形成用于阈值电压控制的结构的方法
US7816737B2 (en) Semiconductor device with gate dielectric containing mixed rare earth elements
CN115613006A (zh) 用于形成包含过渡金属和第13族元素的层的方法和系统

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180313

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180313

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000