KR101174937B1 - 엘리먼트를 감지하기 위한 웨이퍼 레벨 칩 스케일 패키지를 갖는 방법 및 장치 - Google Patents

엘리먼트를 감지하기 위한 웨이퍼 레벨 칩 스케일 패키지를 갖는 방법 및 장치 Download PDF

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KR101174937B1
KR101174937B1 KR1020077016574A KR20077016574A KR101174937B1 KR 101174937 B1 KR101174937 B1 KR 101174937B1 KR 1020077016574 A KR1020077016574 A KR 1020077016574A KR 20077016574 A KR20077016574 A KR 20077016574A KR 101174937 B1 KR101174937 B1 KR 101174937B1
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sacrificial layer
wafer
layer material
depositing
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Korean (ko)
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KR20070095959A (ko
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윌리엄 지. 맥도날드
스티븐 알. 후퍼
아르빈드 에스. 세일리언
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프리스케일 세미컨덕터, 인크.
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261Processes for packaging MEMS devices
    • B81C1/00309Processes for packaging MEMS devices suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/05Temporary protection of devices or parts of the devices during manufacturing
    • B81C2201/053Depositing a protective layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
KR1020077016574A 2005-01-20 2005-12-14 엘리먼트를 감지하기 위한 웨이퍼 레벨 칩 스케일 패키지를 갖는 방법 및 장치 Expired - Lifetime KR101174937B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/039,688 US7109055B2 (en) 2005-01-20 2005-01-20 Methods and apparatus having wafer level chip scale package for sensing elements
US11/039,688 2005-01-20

Publications (2)

Publication Number Publication Date
KR20070095959A KR20070095959A (ko) 2007-10-01
KR101174937B1 true KR101174937B1 (ko) 2012-08-17

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KR1020077016574A Expired - Lifetime KR101174937B1 (ko) 2005-01-20 2005-12-14 엘리먼트를 감지하기 위한 웨이퍼 레벨 칩 스케일 패키지를 갖는 방법 및 장치

Country Status (7)

Country Link
US (1) US7109055B2 (enExample)
EP (1) EP1842224A4 (enExample)
JP (1) JP2008529273A (enExample)
KR (1) KR101174937B1 (enExample)
CN (1) CN101065826A (enExample)
TW (1) TWI392032B (enExample)
WO (1) WO2006078374A1 (enExample)

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US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
JP5357100B2 (ja) * 2010-04-09 2013-12-04 アルプス電気株式会社 フォースセンサパッケージ及びその製造方法
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
DE102011083719B4 (de) * 2011-09-29 2022-12-08 Robert Bosch Gmbh Verfahren zur Herstellung einer Zweichipanordnung
AU2013208114B2 (en) * 2012-01-10 2014-10-30 Hzo, Inc. Masks for use in applying protective coatings to electronic assemblies, masked electronic assemblies and associated methods
JP5999302B2 (ja) * 2012-02-09 2016-09-28 セイコーエプソン株式会社 電子デバイスおよびその製造方法、並びに電子機器
JP5983912B2 (ja) * 2012-02-09 2016-09-06 セイコーエプソン株式会社 電子デバイスおよびその製造方法、並びに電子機器
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
WO2013184145A1 (en) 2012-06-08 2013-12-12 Intel Corporation Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer
WO2013192222A2 (en) 2012-06-18 2013-12-27 Hzo, Inc. Systems and methods for applying protective coatings to internal surfaces of fully assembled electronic devices
US10449568B2 (en) 2013-01-08 2019-10-22 Hzo, Inc. Masking substrates for application of protective coatings
US9894776B2 (en) 2013-01-08 2018-02-13 Hzo, Inc. System for refurbishing or remanufacturing an electronic device
BR112014005790A2 (pt) 2013-01-08 2017-03-28 Hzo Inc remoção de partes selecionadas de revestimentos de proteção de substratos
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
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Also Published As

Publication number Publication date
JP2008529273A (ja) 2008-07-31
TWI392032B (zh) 2013-04-01
CN101065826A (zh) 2007-10-31
EP1842224A4 (en) 2012-07-04
KR20070095959A (ko) 2007-10-01
TW200711007A (en) 2007-03-16
US20060160264A1 (en) 2006-07-20
EP1842224A1 (en) 2007-10-10
US7109055B2 (en) 2006-09-19
WO2006078374A1 (en) 2006-07-27

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