KR101155620B1 - Power control circuit, power supply unit, and power controller control method - Google Patents

Abstract

The power supply control circuit detects the reference voltage VD which is an intermediate voltage between the "Hi Side FET" and the "Lo Side FET" at the time of the short circuit failure of the "Lo Side FET", and uses a comparator COMP to generate a threshold value. Compare "VIN-VrefH" with VD. And if the reference voltage VD is smaller than the threshold value "VIN-VrefH", and the switching control signal Hi Dr is ON, it determines with a short circuit fault. Similarly, the power supply control circuit detects the reference voltage VD of the "Hi Side FET" and the "Lo Side FET" at the time of short circuit failure of the "Hi Side FET", and uses the comparator COMP to determine the threshold value ". VrefL ”and VD are compared. And if the reference voltage VD is larger than threshold value "VrefL" and the switching control signal Lo Dr is ON, it determines with a short circuit fault.

Description

Power control circuit, power supply unit, and control method of power control unit {POWER CONTROL CIRCUIT, POWER SUPPLY UNIT, AND POWER CONTROLLER CONTROL METHOD}

The present invention relates to a power supply control circuit, a power supply device, a power supply system and a control method of the power supply control device.

Conventionally, rectification FETs (Field Effect Transistors) such as "Hi Side FET" and "Lo Side FET" have been used for power supplies used in products such as various electronic devices including information processing apparatuses.

Specifically, for example, as shown in FIG. 27, a non-isolated DC-DC converter step-down circuit having an input power supply, an input capacitor, a smoothing inductor, a smoothing capacitor, a load, a Hi Side FET, a Lo Side FET, and an inverter (switching control). System) and the like. This non-isolated DC-DC converter step-down circuit turns the input current ON / OFF by a switching control signal (Hi Dr or Lo Dr) output from a Hi driver or a Lo driver, and applies a voltage by a smoothing inductor, a smoothing capacitor, and a load. Output the averaged current.

Here, an input power supply is a power supply which supplies electric power to the said non-insulation type DC-DC converter voltage reduction circuit, and an input capacitor is a capacitor which accumulates or discharges the electrical energy supplied by an input power supply. In addition, the smooth inductor is an inductor used for noise suppression, rectification, and smoothing in the non-isolated DC-DC converter step-down circuit described above, and the smoothing capacitor is used to charge electricity when the voltage is high and to lower the voltage. The inductor has a function of smoothing the voltage by discharging, that is, reducing the fluctuation (ripple voltage) of the voltage.

By the way, in a power supply (for example, a non-isolated DC-DC converter step-down circuit, etc.) in which a rectification FET is used, when a short circuit such as a rectification FET occurs, a large current flows through the entire circuit, and thus the power supply and the power supply. This causes a failure of the connected device (connected device).

Therefore, when a short circuit occurs, the protection circuit shown in FIG. 28 is used as a method of protecting the whole circuit. In this protection circuit, when the excess current flowing from the input side of the power supply is detected using the current sense resistor Rsense1, it is determined that the short circuit failure of the "Hi Side FET" is made, and the "Breaker FET1" is opened. The process of separating a location is performed. Similarly, in the protection circuit, when an excess current flowing from the output side of the power supply is detected using the current sense resistor Rsense2, a short circuit failure of the "Lo Side FET" is determined, and the "Breaker FET2" is opened. Process to isolate the fault location.

In addition, the protection circuit detects a small voltage generated by the current sense resistor Rsense1, amplifies it in the amplifier AMP1, and performs a filtering voltage for ignoring the transient peak in the delay circuit DELAY1, and a reference voltage. A comparison is made using a comparator COMP1. When the voltage obtained by filtering is larger than the reference voltage, the protection circuit detects the short circuit failure of the "Hi Side FET". Similarly, the protection circuit detects the minute voltage generated in the current sense resistor Rsense2, amplifies it in the amplifier AMP2, and compares the reference voltage with the filtered voltage that ignores the transient peak in the delay circuit DELAY2. As a result of comparison using (COMP2), if the voltage obtained by filtering is larger than the reference voltage, a short circuit fault of the "Lo Side FET" is detected.

Japanese Patent Application Laid-Open No. 05-146049

However, the above-described prior art has a problem that short circuit failure cannot be detected accurately. Specifically, in the above protection circuit, when the power supply is turned on under the condition that the capacity of the output capacitor is large, or when the load suddenly changes from the light load to the heavy load, excess current may occur even in a normal state. In addition, when the power was turned on under the condition that the voltage remained at the output, or when the load suddenly changed from the heavy load to the light load, the reverse current might occur even in a normal state. By the way, in the conventional protection circuit, when reverse current due to excess current occurs, it is not possible to determine whether or not reverse current due to a failure occurs, so that the reverse current due to the excess current generated in the above-mentioned normal state is also determined. It was judged to be a malfunction.

In the conventional protection circuit, a comparison is made with a reference voltage by using a comparator. However, in order to prevent false detection, a threshold margin is increased by increasing the reference voltage by several tens of percent from the original voltage to be detected. It took time to perform filtering by the delay circuit DELAY. Therefore, it took a long time to detect a failure and open the "Breaker FET" and isolate the failure point. The input voltage of the power supply was reduced, and the voltage of the entire apparatus was also reduced. That is, there was a possibility that the short circuit failure would spread and the whole apparatus would stop.

In addition, in the conventional protection circuit, when an impedance failure occurs, the impedance failure cannot be detected because the voltage effect of the current sense resistor Rsense1 (or current sense resistor Rsense2) is very small or does not occur. . As a result, there has been a problem that heat generation is caused. In addition, the impedance failure refers to a state in which the FET fails due to a certain resistance value in which the short circuit condition in the FEC is not complete, in other words, a middle failure between the short failure and the open failure.

Accordingly, an object of the present invention is to provide a power supply control circuit, a power supply device, a power supply system, and a control method for the power supply control device, which have been made to solve the above-described problems of the prior art, and which make it possible to accurately detect a short circuit failure. It is done.

In order to solve the above-mentioned problems and achieve the object, in the power supply control circuit disclosed by the present application, an input terminal is connected to a first electrode of an input power source, and the input power source is based on a cutoff control signal input to a control terminal. A first current interrupting circuit for interrupting current from the first terminal; an input terminal connected to an output terminal of the first current interrupting circuit; an output terminal connected to a reference node; and a first switching control signal input to a control terminal. On the basis of this, a first switching circuit for switching the current flowing out to the reference node or the current flowing from the reference node, an input terminal is connected to the reference node, and an output terminal is connected to the second electrode of the input power source. And a current flowing from the reference node or the reference node based on the second switching control signal input to the control terminal. A second switching circuit for switching the output current, a second current interrupting circuit for connecting an output terminal to the load and cutting off the current flowing from the reference node based on the interruption control signal input to the control terminal; As a result of comparing the voltage of the reference node with the first reference voltage, when the voltage of the reference node is lower than the first reference voltage, when the first switching control signal is on or the reference node A blocking control signal generation circuit outputting the blocking control signal when the second switching control signal is on when the voltage of the reference node is higher than the second reference voltage as a result of comparing the voltage of Characterized in having a.

According to the power supply control apparatus disclosed by this application, it becomes possible to detect a short circuit failure correctly.

1 shows a DDC converter including a power supply control circuit according to the first embodiment.
2 is a block diagram showing a configuration of a power supply control circuit according to the first embodiment.
FIG. 3 is a diagram illustrating a thinking manner of setting thresholds VIN-VrefH. FIG.
4 is a diagram illustrating a way of thinking of setting the threshold value VrefL.
5 is a diagram showing a normal operating waveform when the load current is large.
6 is a diagram showing a normal operating waveform when the load current is small.
Fig. 7 is a diagram for explaining a short circuit failure time of the “Hi Side FET”.
Fig. 8 is a diagram showing an operation waveform when a short failure of the "Hi Side FET" occurs when the load current is large.
Fig. 9 is a view showing an operation waveform when a low impedance failure of the "Hi Side FET" occurs when the load current is large.
Fig. 10 is a diagram showing an operating waveform at the time of a high impedance failure of the "Hi Side FET" generated when the load current is large.
Fig. 11 is a view showing an operating waveform at the time of an open failure of the "Hi Side FET" generated when the load current is large.
Fig. 12 is a diagram showing an operation waveform when a short failure of the "Hi Side FET" occurs when the load current is small.
Fig. 13 is a view showing an operating waveform at the time of low impedance failure of the “Hi Side FET” generated when the load current is small.
Fig. 14 is a view showing an operating waveform at the time of high impedance failure of the "Hi Side FET" generated when the load current is small.
Fig. 15 is a view showing an operating waveform at the time of an open failure of the "Hi Side FET" generated when the load current is small.
Fig. 16 is a diagram for explaining a short circuit failure time of the “Lo Side FET”;
Fig. 17 is a diagram showing an operating waveform when a short failure of the "Lo Side FET" occurred when the load current is large.
Fig. 18 is a view showing an operating waveform at the time of low impedance failure of “Lo Side FET” generated when the load current is large.
Fig. 19 is a diagram showing an operating waveform at the time of a high impedance failure of the "Lo Side FET" generated when the load current is large.
Fig. 20 is a view showing an operating waveform at the time of open failure of the "Lo Side FET" generated when the load current is large.
Fig. 21 is a diagram showing an operation waveform when a short failure of the "Lo Side FET" occurred when the load current is small.
Fig. 22 is a view showing an operating waveform at the time of low impedance failure of "Lo Side FET" generated when the load current is small;
Fig. 23 is a diagram showing an operating waveform at the time of high impedance failure of the “Lo Side FET” generated when the load current is small;
Fig. 24 is a view showing operating waveforms at the time of open failure of the "Lo Side FET" generated when the load current is small.
Fig. 25 is a diagram showing an example in which n + 1 units in parallel are connected to a DDC to which the power supply control circuit disclosed in the present application is applied;
Fig. 26 is a diagram illustrating an example in which a failure occurs in a configuration in which n + 1 units of DDCs to which the power supply control circuit shown in the present application is connected are connected in parallel;
27 shows an example of a DC-DC converter according to the prior art.
Fig. 28 is a diagram showing a short circuit protection configuration of a DC-DC converter according to the prior art.

 EMBODIMENT OF THE INVENTION Hereinafter, with reference to an accompanying drawing, embodiment of the control method of a power supply control circuit, a power supply device, a power supply system, and a power supply control device which concerns on this invention is described in detail.

Example 1

[Summary of Power Supply Control Circuit]

First, the outline | summary of the power supply control circuit which concerns on Example 1 is demonstrated using FIG. 1 is a diagram illustrating a DDC converter including a power supply control circuit according to the first embodiment.

As shown in Fig. 1, the DDC converter is a device that converts an input voltage VIN into a VOUT (load current IOUT) by a DC-DC voltage converter and outputs a low voltage according to the progress of miniaturization. DC-DC converters (DC-DC converters) that realize power savings, compactness, and lightening of mobile devices such as information processing devices using advanced LSIs and mobile devices, such as high-performance mobile phones, and electronic devices. For example, a switching DC-DC converter.

In the DC-DC voltage converter, an error amplifier for controlling the error voltage signal (Error Voltage) by amplifying the error while always comparing the reference voltage (GND) and the output voltage (VOUT), which are ground potentials, is used. And "PWM COMPARATOR" for modulating the pulse width based on the output from "Error AMP" and the output from the oscillator. Further, based on the pulse width output from the PWM COMPARATOR, "Hi Dr (" first switching control signal "described in the claims) and" Lo Dr ("second switching control signal described in the claims) "Signal generating circuit" for generating ") "

Note that the above-mentioned "PWM COMPARATOR", "Error AMP", and "signal generation circuit" are circuits which a general DC-DC comparator has, and detailed description is abbreviate | omitted here. In addition, "DC" is "Direct Current: DC", and "PWM COMPARATOR" is "Pulse Width Modulation COMPARATOR" (pulse width modulation comparator).

Therefore, the power supply control circuit shown in this embodiment is compared with the "Breaker FET: circuit breaker transistor" connected to the input side of the DC-DC voltage converter, the "Breaker FET: circuit breaker transistor" connected to the output side, and each FET connected. With the circuit group, it is possible to accurately detect a short circuit failure.

Specifically, the power supply control circuit according to the first embodiment has a reference voltage VD of the "Hi Side FET" and the "Lo Side FET" at the time of short circuit failure of the "Lo Side FET" (" Voltage of the reference node ") and compares the threshold value " VIN-VrefH " and VD using a comparator (COMP). And if the reference voltage VD is smaller than the threshold value "VIN-VrefH", and the switching control signal Hi Dr is ON, it determines with a failure.

Similarly, the power supply control circuit according to the first embodiment detects the reference voltage VD of the "Hi Side FET" and the "Lo Side FET" at the time of short circuit failure of the "Hi Side FET", and sets the comparator COMP. The threshold value "VrefL" is compared with VD using this. And if a reference voltage VD is larger than threshold value "VrefL" and the switching control signal Lo Dr is ON, it determines with a failure.

Thus, the power supply control circuit which concerns on Example 1 can detect a short circuit fault with high precision and high speed by using a comparator for detection of a short circuit fault. In addition, by using AND logic to determine the short circuit failure, the short circuit failure can be accurately determined without false detection.

[Configuration of Power Supply Control Circuit]

Next, the structure of the power supply control circuit shown in FIG. 1 is demonstrated using FIG. 2 is a block diagram showing the configuration of a power supply control circuit according to the first embodiment. The power supply control circuit shown in FIG. 2 is a circuit which is assembled to the DDC, and is a non-isolated DC-DC converter step-down circuit (see FIG. 27) in which the "Breaker FET" 20 and the "Breaker FET" 30 are compared. It is a circuit which connected the group 40.

As described above, the non-isolated DC-DC converter step-down circuit in the power supply control circuit shown in FIG. 2 includes the input power supply 10, the input capacitor 11, the smoothing inductor 12, the smoothing capacitor 13, The load 14, the "Hi Side FET" 15, the "Lo Side FET" 16, the Hi driver 17, and the Lo driver 18 are provided. The DC-DC converter step-down circuit described above is based on a switching control signal (Hi Dr or Lo Dr) output from the Hi driver 17 or the Lo driver 18, and the "Hi Side FET" 15 or the "Lo Dr." The input current is turned ON / OFF by the Side FET ”16, and the smoothing inductor 12, the smoothing capacitor 13, and the load 14 are averaged and output.

Among these, the input power supply 10 supplies electric power to the non-isolated DC-DC converter step-down circuit described above, and the input capacitor 11 is a capacitor that accumulates or emits electrical energy supplied by the input power supply. . The smoothing inductor 12 is an inductor used for noise suppression, rectification, and smoothing in the non-isolated DC-DC converter step-down circuit described above, and the smoothing capacitor 13 charges electricity when the voltage is high. The inductor has a function of smoothing the voltage by discharging when the voltage is low, that is, reducing the variation (ripple voltage) of the voltage.

In the "Hi Side FET" 15, an input terminal is connected to an output terminal of the "Breaker FET" 20, an output terminal is connected to a reference node (VD node), and a switching control inputted to a control terminal. Based on the signal Hi Dr, the current flowing into the reference node or the current flowing from the reference node is switched.

In the "Lo Side FET" 16, an input terminal is connected to a reference node (VD node), an output terminal is connected to a second electrode of the input power supply 10, and a switching control signal Lo input to the control terminal (Lo). According to Dr), the current flowing from the reference node or the current flowing out of the reference node is switched.

In addition, the switching control signal Hi Dr and the switching control signal Lo Dr may be controlled to be turned ON mutually exclusively.

The "Breaker FET" 20 is connected to a first electrode of the input power source 10 and receives current from the input power source based on a cutoff control signal input from the inverter 47 to the control terminal described later. It is a circuit to cut off. In the "Breaker FET" 30, the output terminal is connected to the load 14, and based on the cutoff control signal input from the inverter 47 to the control terminal, the current flowing from the reference node (VD node) is cut off. Circuit.

The comparison circuit group 40 compares the voltage VD of the reference node (VD node) with the threshold value VIN-VrefH, and when the "VD" is lower than "VIN-VrefH", the switching control signal. This circuit outputs a cutoff control signal when (Hi Dr) is ON. In addition, the comparison circuit group 40 compares the voltage VD of the reference node (VD node) with the threshold value VrefL, and when the "VD" is higher than "VrefL", the switching control signal Lo Even when Dr) is ON, a cutoff control signal is output.

As a circuit structure of the comparison circuit group 40, for example, a comparison circuit COMPP 41, an AND circuit 42 (AND circuit 42), a comparison circuit COMP 43, and an AND circuit ( The AND circuit 44, the OR circuit 45 (OR circuit 45), the FF (flip-flop) circuit 46, and the inverter 47 can be configured.

Such a comparison circuit (COMP 41) is a comparison circuit for comparing the reference node (VD node) and the threshold value "VIN-VrefH", and the AND circuit 42 outputs from the comparison circuit (COMP 41). And an AND circuit for generating an AND of the switching control signal Hi Dr. In addition, the comparison circuit COMP 43 is a comparison circuit for comparing the reference node (VD node) with the threshold value "VrefL", and the AND circuit 44 is equal to the output from the comparison circuit COMP 43. An AND circuit generates an AND of the switching control signal Lo Dr. The OR circuit 45 is a logical sum circuit that generates a logical sum of the output from the AND circuit 42 and the output from the AND circuit 44, and the FF circuit 46 is an output from the OR circuit 45. Is a flip-flop (FLIP-FLOP) circuit that outputs a cutoff control signal that blocks the occurrence of a short circuit while maintaining

The FF circuit 46 maintains the Hi state when the output "Hi" of the OR circuit 45 is applied to the Set input. This Hi state continues until the FF circuit 46 is reset. (In addition, upon re-entry of the power supply, it is reset by applying Hi to the R input to return the FF circuit 46 to the initial state. ) When the inverter 47 receives the output "Q = Hi" from the FF circuit 46, the inverter 47 inverts the output to turn off the "Breaker FET" 20 and the "Breaker FET" 30. The cutoff control signal is output to the "Breaker FET" 20 and the "Breaker FET" 30. In addition, when the "Breaker FET" 20 and the "Breaker FET" 30 receive the cutoff control signal output from the inverter 47, the circuit is opened and separated from the power supply control device.

In addition, said threshold "VIN-VrefH" corresponds to "the first reference voltage" described in the claims, threshold "VrefL" corresponds to the "second reference voltage" described in the claims, "VIN-VrefH" can also be set higher than "VrefL".

Here, the setting method of the threshold values "VIN-VrefH" and "VrefL" is demonstrated using FIG. 3 and FIG. 3 is a figure which illustrates the thinking system of setting the threshold value VIN-VrefH, and FIG. 4 is a figure which illustrates the thinking system of setting the threshold value VrefL.

As shown in FIG. 3, when the voltage applied to the "Hi side FET" is "VQH", "VrefH" is smaller than "(VIN-VQH) x (R17 / (R14 + R17))" (VIN-VQH). Slightly smaller voltage). Here, when the VrefH adjustment resistor R17 is made smaller, the threshold margin increases. Thereby, the threshold value "VIN-VrefH" is set as "(VIN-VQH) x alpha". However, VQH = ldsQH × RdsQH, α is 1 or less (usually about 0.9) which is a threshold margin coefficient in consideration of the deviation.

In addition, as shown in FIG. 4, when the voltage applied to the "Lo side FET" is "VQL", "VrefL" is represented by "(VQL) x (R13 / (R10 + R13)) x ((R11 + R12). ) / (R11)) " (voltage slightly larger than VQL). Here, when the VrefL adjustment resistor R13 is made large, the threshold margin increases. As a result, the threshold value "VrefL" is set as "VQL x β". However, VQL = ldsQL × RdsQL and β are 1 or less (usually about 0.9) which is a threshold margin coefficient in consideration of the deviation.

The comparison circuit group 40 uses the threshold values "VIN-VrefH" and "VrefL" set by the above-described method and the voltage VD of the reference node to determine the short-circuit failure determination condition "switching control signal HiDr". = Hi is also referred to as reference voltage VD <threshold VIN-VrefH "and" switching control signal LoDr = Hi is also reference voltage VD> threshold VrefL ".

The power supply control circuit detects the intermediate voltage "VD" between the "Hi Side FET" 15 and the "Lo Side FET" 16 when the short circuit failure of the "Hi Side FET" 15 occurs. In (COMP 43), if larger than the voltage "(GND + Bias) = VrefL", AND logic is applied to the switching control signal Lo Dr. As a result, if it is positive logic, the "Breaker FET" 20 and the "Breaker FET" 30 are controlled off.

In addition, the power supply control circuit detects the intermediate voltage "VD" between the "Hi Side FET" 15 and the "Lo Side FET" 16 when the short circuit failure of the "Lo Side FET" 16 occurs. In (COMP 41), if it is small compared with the voltage "(Vi + bias) = (VIN-VrefH)", AND logic is applied to the switching control signal Lo Dr. As a result, if it is positive logic, the "Breaker FET" 20 and the "Breaker FET" 30 are controlled off.

In this way, the short circuit failure can be detected with good accuracy and at high speed, so that the short circuit failure can be accurately determined without false detection. In addition, compared with the conventional method, the number of parts is small and the configuration is simple, and the redundancy of the power source can be ensured.

[Operation Waveform of Power Supply Circuit]

Next, with reference to Figs. 5 to 26, the normal operation waveform and the failure waveform in the power supply control circuit according to the first embodiment will be described.

However, "ton" shown in FIGS. 5 to 26 is the conduction time of the "Hi Side FET" 15, "toff" is the conduction time of the "Lo Side FET" 16, and "tsw" is voltage feedback control. Is a load current, "IL" is a current flowing through the smoothing inductor 12, and "ILpp" is a ripple current flowing through the smoothing inductor 12. In addition, "VQH" is the voltage drop during conduction of the "Hi Side FET" 15 (VQH = ldsQH x RdsQH), and "VQL" is the voltage drop during conduction of the "Lo Side FET" 16 (VQL = ldsQL ×). RdsQL).

(1.Operation Waveform in Normal State)

First, the operation waveform in the normal state in the power supply control circuit according to the first embodiment will be described with reference to FIGS. 5 and 6. 5 is a diagram showing a normal operating waveform when the load current is large, and FIG. 6 is a diagram showing a normal operating waveform when the load current is small. In addition, when the load current is large, it is when (IOUT> = (1/2) × ILpp), and when the load current is small, it is when (IOUT <(1/2) × ILpp).

As shown in Fig. 5 and Fig. 6, the voltage feedback is controlled so that "ton = (VOUT + VQH) x tsw" and "toff = tsw-ton" are normal at normal times. At this time, the reference voltage VD becomes "(D at) VD = VIN-VQH" and "(toff) VD = -VQL". In addition, when the load current is small ((IOUT <(1/2) × ILpp)), since there is a period in which the smooth inductor 12 is reversed, it becomes “VD = + VQL”.

(2. Operation waveform in case of failure)

Next, operation waveforms at the time of failure in the power supply control circuit according to the first embodiment will be described. Here, "short circuit fault of Hi Side FET" when "load current is large" or "load current is small", and "Lo Side FET" when "load current is large" or "load current is small" Will be described.

(2-1.In case of short fault of Hi Side FET)

First, the outline | summary at the time of the short circuit failure of the "Hi Side FET" 15 is demonstrated using FIG. Fig. 7 is a diagram for explaining the short circuit failure time of the "Hi Side FET". As shown in FIG. 7, when the short circuit failure of the "Hi Side FET" is set to "ZQH", the impedance of the short circuit failure of the "Hi Side FET" is set to the on resistances "RdsQL" and "ZQH" of the "Lo Side FET". Division of VIN becomes the reference voltage "VD". That is, it becomes "VD = (RdsQL / (ZQH + RdsQL)) x VIN".

(2-1-1.In case of short circuit failure of Hi Side FET (load current is large))

Here, the "short fault", "Low impedance fault", "High impedance fault", and "open fault" which generate | occur | produce in the "Hi Side FET" when "load current is large" are demonstrated. In addition, "when load current is large" is a state of "load current IOUT> = (1/2) x ripple current ILpp".

(a.short fault)

First, the short failure of the "Hi Side FET" generated when the load current is large will be described with reference to FIG. Fig. 8 is a diagram showing an operation waveform at the time of a short failure of the "Hi Side FET" generated when the load current is large. The "short fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault "0ohm" failed. Therefore, the power supply control circuit according to the first embodiment can be approximated with reference voltage "VD" = "VIN", and with "switching control signal LoDr = Hi and reference voltage VD> threshold VrefL". As a result, it is determined that the "Hi Side FET" short circuit failure has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(b.Low Impedance Failure)

Next, the low impedance failure of the "Hi Side FET" generated when the load current is large will be described with reference to FIG. Fig. 9 is a diagram showing an operation waveform at the time of low impedance failure of the "Hi Side FET" generated when the load current is large. The "low impedance failure" shown here is a case where the impedance "ZQH" at the time of a short circuit failure fails at a value close to the on resistance of the "Hi Side FET" (for example, several mohms). Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "(1/2) x VIN to VIN", and "switching control signal LoDr = Hi and reference voltage VD. &Quot; threshold value (VrefL) &quot; to determine that the &quot; Hi Side FET &quot; short has failed.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(c.High impedance failure)

Next, the high impedance failure of the "Hi Side FET" generated when the load current is large will be described with reference to FIG. Fig. 10 is a diagram showing an operation waveform at the time of the high impedance failure of the "Hi Side FET" generated when the load current is large. The "High impedance fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault has broken down to the value (for example, tens of mohms) larger than the on resistance of a "Hi Side FET". Accordingly, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "0V-(VIN- (lds x ZQH))" by lowering the voltage by "lds x ZQH", and "switching" The control signal HiDr = Hi is also referred to as the reference voltage VD <threshold VIN-VrefH &quot;, thereby determining that the "Hi Side FET" short circuit fault has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(d. open fault)

Next, the open fault of the "Hi Side FET" which generate | occur | produced when load current is large is demonstrated using FIG. Fig. 11 is a diagram showing an operating waveform when an open failure of the "Hi Side FET" occurs when the load current is large. The "open fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault fails in several ohms or more. Therefore, the power supply control circuit according to the first embodiment can be approximated with "reference voltage" VD "= 0 V, and" switching control signal HiDr = Hi and reference voltage VD <threshold (VIN-VrefH) ", It determines with" Hi Side FET "short circuit failure.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(2-1-2.In case of short circuit failure of Hi Side FET (load current is small))

Here, the "short fault", "Low impedance fault", "High impedance fault", and "open fault" which generate | occur | produce in the "Hi Side FET" when "load current is small" are demonstrated. In addition, "when the load current is small" is a state of "load current IOUT <(1/2) x ripple current ILpp".

(a.short fault)

First, the short failure of the "Hi Side FET" generated when the load current is small will be described with reference to FIG. Fig. 12 is a diagram showing an operating waveform at the time of a short failure of the "Hi Side FET" generated when the load current is small. The "short fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault "0ohm" failed. Therefore, the power supply control circuit according to the first embodiment can be approximated with reference voltage "VD" = "VIN", and with "switching control signal LoDr = Hi and reference voltage VD> threshold VrefL". As a result, it is determined that the "Hi Side FET" short circuit failure has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(b.Low Impedance Failure)

Next, the low impedance failure of the "Hi Side FET" generated when the load current is small will be described with reference to FIG. Fig. 13 is a diagram showing an operation waveform at the time of low impedance failure of the "Hi Side FET" generated when the load current is small. The "low impedance fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault has failed at a value close to the on resistance of the "Hi Side FET" (for example, several mohms). Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "(1/2) x VIN to VIN", and "switching control signal LoDr = Hi and reference voltage VD. &Quot; threshold value (VrefL) &quot; to determine that the &quot; Hi Side FET &quot; short has failed.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(c.High impedance failure)

Next, with reference to FIG. 14, the high impedance failure of the "Hi Side FET" which generate | occur | produced when load current is small is demonstrated. Fig. 14 is a diagram showing an operating waveform at the time of high impedance failure of the "Hi Side FET" generated when the load current is small. The "High impedance fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault has broken down to the value (for example, tens of mohms) larger than the on resistance of a "Hi Side FET". Accordingly, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "0V-(VIN- (lds x ZQH))" by lowering the voltage by "lds x ZQH", and "switching" The control signal HiDr = Hi is also referred to as the reference voltage VD <threshold VIN-VrefH &quot;, thereby determining that the "Hi Side FET" short circuit fault has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(d. open fault)

Next, the open fault of the "Hi Side FET" which occurred when the load current was small is demonstrated using FIG. Fig. 15 is a diagram showing an operating waveform at the time of open failure of the "Hi Side FET" generated when the load current is small. The "open fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault fails in several ohms or more. Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "0V", and "switching control signal HiDr = Hi and reference voltage VD <threshold (VIN-VrefH) ", It determines with" Hi Side FET "short circuit failure.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(2-2.In case of short fault of Lo Side FET)

16, the outline at the time of the short circuit failure of the "Lo Side FET" 16 will be described. Fig. 16 is a diagram for explaining the short circuit failure time of the "Lo Side FET". As shown in FIG. 16, when the short circuit failure of the "Lo Side FET" is referred to as "ZQL", the impedance of the short circuit failure of the "Lo Side FET" corresponds to the on resistances "RdsQH" and "ZQL" of the "Hi Side FET". Division of VIN becomes the reference voltage "VD". That is, "VD = (ZQL) / (RdsQH + ZQL)) x VIN".

(2-2-1.In case of short-circuit failure of Lo Side FET (load current is large)

Here, the "short fault", "Low impedance fault", "High impedance fault", and "open fault" which generate | occur | produce in the "Lo Side FET" when "load current is large" are demonstrated. In addition, "when load current is large" is a state of "load current IOUT> = (1/2) x ripple current ILpp".

(a.short fault)

First, the short failure of the "Lo Side FET" generated when the load current is large will be described with reference to FIG. Fig. 17 is a diagram showing an operating waveform at the time of a short failure of the “Lo Side FET” generated when the load current is large. The "short fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault "0ohm" failed. Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" = "0V", and the "switching control signal HiDr = Hi and the reference voltage VD <threshold value (VIN-VrefH) ", It determines with" Lo Side FET "short circuit failure.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(b.Low Impedance Failure)

Next, the low impedance failure of the "Lo Side FET" generated when the load current is large will be described with reference to FIG. Fig. 18 is a diagram showing an operating waveform at the time of low impedance failure of the “Lo Side FET” generated when the load current is large. The "low impedance failure" shown here is a case where the impedance "ZQH" at the time of a short circuit failure fails at a value close to the on resistance of the "Lo Side FET" (for example, several mohms). Therefore, in the power supply control circuit according to the first embodiment, the reference voltage "VD" can be approximated to "0V-((1/2) x VIN)", and "switching control signal HiDr = Hi and the reference voltage ( VD) &lt; threshold value (VIN-VrefH) &quot; to determine that the &quot; Lo Side FET &quot; short has failed.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(c.High impedance failure)

Next, the high impedance failure of the "Lo Side FET" generated when the load current is large will be described with reference to FIG. 19. Fig. 19 is a diagram showing an operation waveform at the time of the high impedance failure of the "Lo Side FET" generated when the load current is large. The "High impedance fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault fails with a value (for example, tens of mohms) larger than the on resistance of the "Lo Side FET". Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "(lds x ZQH) ~ 0V", and "switching control signal LoDr = Hi and reference voltage VD> threshold Value (VrefL) "to determine that the" Lo Side FET "short circuit has failed.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(d. open fault)

Next, the open fault of the "Lo Side FET" which generate | occur | produced when load current is large is demonstrated using FIG. Fig. 20 is a diagram showing an operation waveform when an open failure of the "Lo Side FET" occurred when the load current is large. The "open fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault fails in several ohms or more. Accordingly, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "VIN", and the "switching control signal LoDr = Hi and the reference voltage VD> threshold value VrefL". As a result, it is determined that the "Lo Side FET" short circuit failure has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(2-2-2.In case of short circuit failure of Lo Side FET (load current is small))

Here, the "short fault", "Low impedance fault", "High impedance fault", and "open fault" which generate | occur | produce in the "Lo Side FET" 16 when "load current is small" are demonstrated. In addition, "when the load current is small" is a state of "load current IOUT <(1/2) x ripple current ILpp".

(a.short fault)

First, the short failure of the "Lo Side FET" generated when the load current is small will be described with reference to FIG. Fig. 21 is a diagram showing an operating waveform at the time of a short failure of the "Lo Side FET" generated when the load current is small. The "short fault" shown here is when the impedance "ZQH" at the time of a short circuit fault "0ohm" failed. Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" = "0V", and the "switching control signal HiDr = Hi" and the reference voltage VD <threshold value VIN-VrefH. ", It determines with" Lo Side FET "short circuit failure.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(b.Low Impedance Failure)

Next, the low impedance failure of the "Lo Side FET" generated when the load current is small will be described with reference to FIG. Fig. 22 is a diagram showing an operating waveform at the time of low impedance failure of the "Lo Side FET" generated when the load current is small. The "low impedance failure" shown here is a case where the impedance "ZQH" at the time of a short circuit failure fails at a value close to the on resistance of the "Lo Side FET" (for example, several mohms). Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "0V-(1/2) x VIN", and "switching control signal HiDr = Hi and reference voltage VD. By &quot; threshold value VIN-VrefH &quot;, it is determined that the "Lo Side FET" short circuit failure has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VIN-VrefH" by the comparator (COMP 41) is "VD <VIN-VrefH", Let the output of (41) be "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 41 and the switching control signal "HiDr = Hi" from the AND circuit 42, the AND circuit 42 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (42) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(c.High impedance failure)

Next, the high impedance failure of the "Lo Side FET" generated when the load current is small will be described with reference to FIG. Fig. 23 is a diagram showing an operating waveform at the time of high impedance failure of the "Lo Side FET" generated when the load current is small. The "High impedance fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault fails by a value (for example, tens of mohms) larger than the on resistance of the "Lo Side FET". Therefore, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "(lds x ZQH)-0V), and" switching control signal LoDr = Hi and reference voltage VD >> Threshold value (VrefL) ", and it determines with" Lo Side FET "short circuit failure.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

(d. open fault)

Next, with reference to FIG. 24, the open fault of "Lo Side FET" which generate | occur | produced when load current is small is demonstrated. Fig. 24 is a diagram showing an operating waveform at the time of an open failure of the "Lo Side FET" generated when the load current is small. The "open fault" shown here is a case where the impedance "ZQH" at the time of a short circuit fault fails in several ohms or more. Accordingly, the power supply control circuit according to the first embodiment can approximate the reference voltage "VD" to "VIN", and the "switching control signal LoDr = Hi and the reference voltage VD> threshold value VrefL". As a result, it is determined that the "Lo Side FET" short circuit failure has occurred.

Specifically, in the power supply control circuit according to the first embodiment, if the result of comparing the reference voltage "VD" and the threshold value "VrefL" with the comparator COMP43 is "VD> VrefL", Set the output to "Hi". Subsequently, when the power supply control circuit receives the output "Hi" of the COMP 43 and the switching control signal "LoDr = Hi" from the AND circuit 44, the AND circuit 44 outputs "Hi" and the AND circuit. The OR circuit 45 which received the output of (44) outputs "Hi". The output "Hi" of the OR circuit 45 is applied to the Set input of the FF circuit 46, and the output "Q" of the FF circuit 46 maintains the Hi state. This Hi state continues until the FF circuit 46 is reset. After that, the inverter 47 performs a logic inversion in the inverter 47 to turn off the "Breaker FET" 20 and the "Breaker FET" 30. Thus, the power supply control circuit which concerns on Example 1 isolate | disconnects a fault point and protects by turning off "Breaker FET" 20 and "Breaker FET" 30. FIG.

[Effect by Example 1]

Thus, according to the first embodiment, it is possible to accurately detect the short circuit failure. For example, it is a method of detecting the reference voltage (VD) applied between the "Hi Side FET" 15 and the "Lo Side FET" 16, and since no current is used for failure determination, Even when excessive current or reverse current occurs at the time of sudden load change, erroneous detection due to FET short circuit failure can be prevented. The obtained reference voltage VD is not a minute voltage and can be directly input to the comparator COMP41 or COMP43, and thus, not through the amplifier AMP or the delay circuit DELAY, Since the short circuit failure can be immediately determined and the "Breaker FET" 20 and the "Breaker FET" 30 can be opened, the response time can be made faster and the short circuit failure spread can be suppressed.

In addition, since the fault is determined by detecting the reference voltage VD, not by the method of detecting the fault by detecting the current, it can be detected by the AND logic with the switching control signal even at the time of the impedance fault. Specifically, the reference voltage VD applied between the "Hi Side FET" 15 and the "Lo Side FET" 16 is detected, and the AND logic is performed between the switching control signals. If it does not match the logic, it detects that a failure has occurred. Therefore, even when the impedance failure at which the VD is at an intermediate voltage different from the original can be logically identified as abnormal, the impedance failure can be detected and the heat generation can be prevented.

In addition, since the reference voltage VD applied between the "Hi Side FET" 15 and the "Lo Side FET" 16 is detected and a failure is judged, the current sense resistor Rsense may be unnecessary. By using the current sense resistor (Rsense) it is possible to prevent the power loss caused by the deterioration significantly. In addition, since there is no need to detect a current for failure determination, the current sense resistor (Rsense), amplifier (AMP), and DELAY (filter of peak) may also be unnecessary, thereby reducing the number of parts of the entire protection circuit (power supply control circuit). As a result, the installation area and cost can be improved.

Example 2

In addition, although Example 1 was demonstrated so far, this Example may be implemented in various other forms other than the above-mentioned Example. Therefore, as shown below, another embodiment will be described, each divided into (1) parallel configuration, (2) circuit configuration, and the like.

(1) parallel configuration

For example, in Example 1, although one DDC to which the power supply control circuit shown in this application was applied was demonstrated as an example, as shown in FIG. 25, n + 1 DDCs to which the power supply control circuit shown by this application was applied (DDC0- DDCn) can be connected in parallel. In general, when a general power supply control circuit is connected in parallel, when one unit fails, the input and output voltages enter and fail the failed DDC, resulting in power failure or load stoppage of the entire apparatus. Therefore, in a configuration in which n + 1 units (DDC0 to DDCn) in parallel with the DDC to which the power supply control circuit shown in the present application is connected, even when one DDC fails, the "Breaker FET" is opened as shown in FIG. The fault points can be separated, thereby preventing one fault from spreading to another DDC.

25 is a figure which shows the example which connected n + 1 parallel DDC which applied the power supply control circuit which this application discloses, and FIG. 26 shows n + 1 parallel to the DDC which applied the power supply control circuit which this application discloses. It is a figure which shows the example which a failure generate | occur | produced in the connected structure.

(2) circuit configuration

In addition, each component of each apparatus shown is a functional concept, and does not necessarily need to be comprised as shown physically. That is, the specific form of dispersion / integration of each device is not limited to what is shown in figure, All or one part can be functionally or physically distributed and integrated in arbitrary units according to various loads or usage conditions, etc., and can comprise it. . For example, in the configuration of FIG. 2, when a short circuit fault occurs in either of the "Hi Side FET" 15 and the "Lo Side FET" 16, the "Breaker FET" 20 and the "Breaker FET" Although an example of opening and separating both sides of (30) is shown, one of the "Breaker FET" 20 and the "Breaker FET" 30 may be opened to be separated.

10 input power 11 input capacitor
12: smoothing inductor 13: smoothing capacitor
14: Load 15: Hi Side FET
16: Lo Side FET 17: Hi Driver
18: Lo driver 20, 30: Breaker FET
40: comparative circuit group 41, 43: COMP
42, 44: AND circuit 45: OR circuit
46: FF circuit 47: inverter

Claims (12)

A first current interrupting circuit which is connected to a first electrode of an input power source and cuts off the current from the input power source based on a cutoff control signal input to a control terminal;
An input terminal is connected to an output terminal of the first current interrupting circuit, an output terminal is connected to a reference node, and the current or the reference flows out to the reference node based on a first switching control signal input to a control terminal. A first switching circuit for switching the current flowing from the node,
An input terminal is connected to the reference node, an output terminal is connected to a second electrode of the input power, and a current flowing from the reference node or the reference node is based on a second switching control signal input to a control terminal. A second switching circuit for switching the current flowing out to the
A second current interrupting circuit connected to a load, the output terminal being disconnected from the reference node based on the interruption control signal input to a control terminal;
As a result of comparing the voltage of the reference node with the first reference voltage, when the voltage of the reference node is lower than the first reference voltage, when the first switching control signal is on or the reference node A blocking control signal generation circuit outputting the blocking control signal when the second switching control signal is on when the voltage of the reference node is higher than the second reference voltage as a result of comparing the voltage of Power control circuit having a. The method of claim 1,
The cutoff control signal generation circuit,
A first comparison circuit for comparing the voltage of the reference node with the first reference voltage;
A first AND circuit for generating an AND of the output of the first comparison circuit and the first switching control signal;
A second comparison circuit for comparing the voltage of the reference node with the second reference voltage;
A second AND circuit for generating an AND of the output of the second comparison circuit and the second switching control signal;
And a logical sum generating circuit for generating a logical sum of the output of the first AND logic circuit and the output of the second AND logic circuit. The method of claim 2,
The cutoff control signal generation circuit,
And a holding circuit for holding the output of said logical sum generating circuit and outputting said cutoff control signal. The method according to any one of claims 1 to 3,
And the first reference voltage is higher than the second reference voltage. The method according to any one of claims 1 to 3,
And the first switching control signal and the second switching control signal are mutually exclusively turned on. The method according to any one of claims 1 to 3,
The power supply control circuit,
And a first smoothing circuit connected in parallel to an output of said first current interrupting circuit and a second electrode of said input power source. The method according to any one of claims 1 to 3,
The power supply control circuit,
A second power supply smoothing a current flowing from the reference node to the input terminal of the second current interrupting circuit or a current flowing from the input terminal of the second current blocking circuit to the reference node; Control circuit. Input power,
A first current interrupting circuit connected to an input terminal of the first power supply and blocking current from the input power based on a blocking control signal input to a control terminal;
An input terminal is connected to an output terminal of the first current interrupting circuit, an output terminal is connected to a reference node, and the current or the reference flows out to the reference node based on a first switching control signal input to a control terminal. A first switching circuit for switching the current flowing from the node,
An input terminal is connected to the reference node, an output terminal is connected to a second electrode of the input power, and a current flowing from the reference node or the reference node is based on a second switching control signal input to a control terminal. A second switching circuit for switching the current flowing out to the
A second current interrupting circuit connected to a load, the output terminal being disconnected from the reference node based on the interruption control signal input to a control terminal;
As a result of comparing the voltage of the reference node and the first reference voltage, when the voltage of the reference node is lower than the first reference voltage, when the first switching control signal is on, or when the first switching control signal is on, And a cutoff control signal generation circuit that outputs the cutoff control signal when the second switching control signal is on when the voltage of the reference node is higher than the second reference voltage as a result of comparing the two reference voltages. Power supply. A step in which a first current interrupting circuit, to which an input terminal is connected to a first electrode of an input power source, cuts off a current from the input power source based on a cutoff control signal input to a control terminal;
On the basis of the first switching control signal input to the control terminal, a first switching circuit connected to an output terminal of the first current interrupting circuit and simultaneously connected to an output terminal of the first current interrupting circuit flows out to the reference node. Switching a current to be supplied or current flowing from the reference node;
A second switching circuit having an input terminal connected to the reference node and an output terminal connected to a second electrode of the input power source is introduced from the reference node based on a second switching control signal input to a control terminal. Switching current or current flowing into the reference node;
A step in which the second current interrupting circuit whose output terminal is connected to the load cuts off the current flowing from the reference node based on the interruption control signal input to the control terminal;
As a result of comparing the voltage of the reference node and the first reference voltage, when the voltage of the reference node is lower than the first reference voltage, when the first switching control signal is on, or when the first switching control signal is on, And comparing the two reference voltages, when the voltage of the reference node is higher than the second reference voltage, when the second switching control signal is on, including a blocking control signal generating step of outputting the blocking control signal. The control method of the power supply control apparatus. The method of claim 9,
And the first reference voltage is higher than the second reference voltage. The method according to claim 9 or 10,
And the first switching control signal and the second switching control signal are mutually exclusively turned on. delete

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