CN103440010B - Active voltage limiting circuit - Google Patents
Active voltage limiting circuit Download PDFInfo
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- CN103440010B CN103440010B CN201310380044.7A CN201310380044A CN103440010B CN 103440010 B CN103440010 B CN 103440010B CN 201310380044 A CN201310380044 A CN 201310380044A CN 103440010 B CN103440010 B CN 103440010B
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Abstract
The invention relates to the technical field of analogue integrated circuits, and discloses an active voltage limiting circuit. The active voltage limiting circuit solves the problem that an existing voltage limiting circuit is insufficiently stable in output voltage and poor in accuracy. According to the technical scheme, the active voltage limiting circuit comprises an NMOS tube M1, an NMOS tube M2, an NMOS tube M14, an NMOS tube M18, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, a PMOS tube M12, a PMOS tube M13, a PMOS tube M15, a PMOS tube M16, a PMOS tube M17, a PNP type triode Q1, a PNP type triode Q2, an NPN type triode Q3, an inverter and an either-or selection circuit. When the input voltage is within the set threshold voltage scope, the output voltage follows changes of the input voltage, and the following accuracy is high. When the input voltage is out of the set threshold voltage scope, the output voltage is the upper limit of the threshold voltage or the lower limit of the threshold voltage, and the output voltage is high in stability.
Description
Technical field
The present invention relates to Analogous Integrated Electronic Circuits circuit engineering field, particularly a kind of active voltage limit circuit.
Background technology
Voltage limit circuit is as the design cell of partial circuit, comparatively be widely used in Analogous Integrated Electronic Circuits, its core is exactly in the voltage range of setting, output voltage can follow input voltage change, beyond the voltage range of setting, circuit exports can be fixed on a certain particular value, and not with input change, its degree of accuracy and stability determine the quality of voltage limit circuit performance to a great extent.
The shortcoming of traditional voltage limit circuit is, in the voltage range of setting, output voltage well can not follow input voltage change, produces error at output terminal; Or beyond the voltage range of setting, circuit exports can not be fixed on a certain particular value.Such circuit output voltage is stable not, poor accuracy, can produce labile factor, can not be applied in the more stable and accurate field of ask for something in subsequent conditioning circuit uses.
Summary of the invention
The object of the invention is to solve existing voltage limit circuit output voltage stable not, the problem of poor accuracy, provides a kind of active voltage limit circuit.
The present invention solve the technical problem, the technical scheme adopted is, a kind of active voltage limit circuit, it is characterized in that, comprise four NMOS tube: M1, M2, M14, M18,14 PMOS: M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17, two PNP type triode: Q1, Q2, NPN type triode a: Q3, phase inverter and alternative selection circuit;
Concrete annexation is as follows: NMOS tube M1, M2 form current mirror, M1, M2 pipe source ground, current source IB is connected with M1 grid leak, M1 grid connects M18 grid, M2 grid connects M1 grid and drain electrode, M2 drain electrode connects M3 drain and gate, M3 grid connects PMOS M4, M6, M7, M9, M11, M15 grid, M3, M4, M6, M7, M9, M11, M15 source electrode meets high level VDD, M4 drain electrode connects M5 source electrode and Q1 pipe base stage, M5 grounded drain, M5 grid is connected with M10 grid and is connected input voltage V
iN, M6 drain electrode connects PNP type triode Q1, the base stage of Q2 emitter and NPN type triode Q3, Q1, Q2 grounded collector, M7 drain electrode connects Q2 base stage and M8 source electrode, M8 grounded drain, M8 grid connects upper threshold voltage VTH+, M9 drain electrode connects M12 grid and M10 source electrode, M10 grounded drain, M11 drain electrode connects M12 and M13 source electrode, M12 grounded drain, M13 drain electrode connects M14 drain and gate and inverter input, M14 source ground, M15 drain electrode connects M13 grid and M16 source electrode, M16 grounded drain, M16 grid connects threshold voltages VTH-, NPN type triode Q3 collector meets high level VDD, Q3 emitter connects M17 source electrode, M17 grid is connected and output voltage VA with drain electrode, M17 drain electrode connects M18 drain electrode, M17 grid connects the B input end of alternative selection circuit, M18 source ground, the A input end of alternative selection circuit connects threshold voltages VTH-, inverter output connects the Enable Pin EN of alternative selection circuit, the output terminal output voltage V of alternative selection circuit
oUT,
Work as V
iNduring <VTH-, Enable Pin EN is high level, and alternative selection circuit exports VTH-; Work as VTH-<V
iNduring <VTH+, output voltage VA follows V
iNchange, Enable Pin EN is low level, and alternative selection circuit exports VA; Work as V
iNduring >VTH+, output voltage VA is fixed as VTH+, and Enable Pin EN is low level, alternative selection circuit output voltage VTH+.
The invention has the beneficial effects as follows, when input voltage is in the threshold voltage ranges set, output voltage follows input voltage change, and it is high to follow precision; Input voltage is when the threshold voltage ranges set is outer, and output voltage is upper threshold voltage or threshold voltages, and output voltage stability is high.
Accompanying drawing illustrates:
Fig. 1 is the circuit diagram of active voltage limit circuit of the present invention;
Fig. 2 is the emulation schematic diagram of active voltage limit circuit of the present invention.
Wherein: M1, M2, M14, M18 are NMOS tube; M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17 are PMOS; Q1, Q2 are PNP type triode; Q3 is NPN type triode; INV is phase inverter; MUX2 is alternative selection circuit.
Embodiment
Below in conjunction with accompanying drawing and concrete embodiment, the invention will be further elaborated.Obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making performing creative labour, all belongs to the scope of protection of the invention.
Active voltage limit circuit of the present invention, physical circuit as shown in Figure 1.Wherein, VTH+ and VTH-is the threshold voltage of setting, and VTH+ is upper threshold voltage, and VTH-is threshold voltages, V
iNfor input voltage.
Work as V
iNduring <VTH-, Enable Pin EN is high level, and alternative selection circuit MUX2 selects the input voltage VTH-of input end A as output, i.e. V
oUT=VTH-, as the minimum of output voltage.
Work as VTH-<V
iNduring <VTH+, Enable Pin EN is low level, and alternative selection circuit MUX2 selects the input voltage VA of input end B as output, i.e. V
oUT=VA.At this moment VA follows V
iNchange, V
oUTalso input voltage V is followed
iNchange and change.
Work as V
iNduring >VTH+, VA is fixed as VTH+, and Enable Pin EN is low level, and alternative selection circuit MUX2 selects the input voltage VA of input end B as output, i.e. V
oUT=VTH+, as the mxm. of output voltage.
Circuit of the present invention as shown in Figure 1, comprise four NMOS tube: M1, M2, M14, M18,14 PMOS: M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17, two PNP type triode: Q1, Q2, NPN type triode a: Q3, phase inverter INV and alternative selection circuit MUX2.
Concrete annexation is as follows: NMOS tube M1, M2 form current mirror, M1, M2 pipe source ground, current source IB is connected with M1 grid leak, M1 grid connects M18 grid, M2 grid connects M1 grid and drain electrode, M2 drain electrode connects M3 drain and gate, M3 grid connects PMOS M4, M6, M7, M9, M11, M15 grid, M3, M4, M6, M7, M9, M11, M15 source electrode meets high level VDD, M4 drain electrode connects M5 source electrode and Q1 pipe base stage, M5 grounded drain, M5 grid is connected with M10 grid and is connected input voltage V
iN, M6 drain electrode connects PNP type triode Q1, the base stage of Q2 emitter and NPN type triode Q3, Q1, Q2 grounded collector, M7 drain electrode connects Q2 base stage and M8 source electrode, M8 grounded drain, M8 grid connects upper threshold voltage VTH+, M9 drain electrode connects M12 grid and M10 source electrode, M10 grounded drain, M11 drain electrode connects M12 and M13 source electrode, M12 grounded drain, M13 drain electrode connects M14 drain and gate and inverter input, M14 source ground, M15 drain electrode connects M13 grid and M16 source electrode, M16 grounded drain, M16 grid connects threshold voltages VTH-, NPN type triode Q3 collector meets high level VDD, Q3 emitter connects M17 source electrode, M17 grid is connected and output voltage VA with drain electrode, M17 drain electrode connects M18 drain electrode, M17 grid connects the B input end of alternative selection circuit, M18 source ground, the A input end of alternative selection circuit connects threshold voltages VTH-, inverter output connects the Enable Pin EN of alternative selection circuit, the output terminal output voltage V of alternative selection circuit
oUT.
Below the principle of work of active voltage limit circuit of the present invention is described:
As shown in Figure 1,1) as input voltage V
iNwhen being less than threshold voltages VTH-, namely PMOS M16 grid voltage is greater than the grid voltage of M10, now PMOS M13 grid voltage is greater than PMOS M12 grid voltage, M13 pipe ends, NMOS tube M14 does not have electric current flow through, phase inverter INV is input as low level, and alternative selection circuit MUX2 Enable Pin EN is high level, selects the input voltage VTH-of input end A as output V
oUT, namely the bottoming voltage of circuit is VTH-;
2) when input voltage is greater than threshold voltages VTH-, namely PMOS M16 grid voltage is greater than M10 grid voltage, now PMOS M12 grid voltage is greater than PMOS M13 grid voltage, PMOS M12 ends, PMOS M13 conducting, PMOS M11 drain current all flows through NMOS tube M14, the input terminal voltage of phase inverter INV is raised, by reasonably designing the rollback point of phase inverter INV, realize the in good time reversion of phase inverter INV, now phase inverter INV is input as high level, and alternative selection circuit MUX2 Enable Pin EN is low level, selects the input voltage VA of input end B as output V
oUT;
2.1) when input voltage is greater than upper threshold voltage VTH+, from 2), circuit selects VA as output V
oUT, now have PMOS M5 grid voltage to be greater than M8 grid voltage, namely the base voltage of PNP type triode Q1 is greater than the base voltage of PNP type triode Q2, i.e. Q1 pipe cut-off, the conducting of Q2 pipe, all tail currents flow through on Q2, now by rational design circuit parameter, make VA=VTH+ as output V
oUT, then the output upper limit of circuit is VTH+, namely has:
VA＝V
TH++|V
GSM8|+|V
BEQ2|-V
BEQ3-|V
GSM17| (1)
Wherein, V
gSM8for PMOS M8 gate source voltage, V
gSM17for PMOS M17 gate source voltage, V
bEQ2for PNP type triode Q2 base-emitter voltage, V
bEQ3for NPN type triode Q3 base-emitter voltage.
Regulating circuit, makes:
|V
GSM8|＝|V
GSM17| (2)
|V
BEQ2|＝V
BEQ3 (3)
Then formula (1) can be reduced to:
VA＝V
TH+ (4)
2.2) when input voltage is greater than threshold voltages VTH-and be less than upper threshold voltage VTH+, from 2), circuit selects VA as output V
oUT, now have PMOS M5 grid voltage to be less than M8 grid voltage, namely the base voltage of PNP type triode Q1 is less than the base voltage of PNP type triode Q2, i.e. the conducting of Q1 pipe, and Q2 pipe ends, and all tail currents flow through on Q1, now have:
VA＝V
IN+|V
GSM8|+|V
BEQ2|-V
BEQ3-|V
GSM17| (5)
In like manner, by regulating circuit, abbreviation formula (5), can obtain:
VA＝V
IN (6)
Namely have: 1) work as V
iNduring <VTH-, Enable Pin EN is high level, and alternative selection circuit MUX2 selects VTH-, V
oUT=VTH-, as the minimum of output voltage;
2) V is worked as
iNduring >VTH-, Enable Pin EN is low level, V
oUTfollow VA to export, V
oUT=VA.
2.1) VTH-<V is worked as
iNduring <VTH+, voltage VA follows V
iNchange, i.e. V
oUTfollow input voltage V
iNchange and change;
2.2) V is worked as
iNduring >VTH+, voltage VA is fixed as VTH+, i.e. V
oUTexport fixed voltage VTH+, as the mxm. of output voltage.
Active voltage limit circuit of the present invention, lower threshold value VTH-is set as 0.5V, and upper threshold value VTH+ is set as 2V, input voltage V
iNwhen input range is in 0 ~ 3V, use H-spice simulation result as shown in Figure 2.
Those of ordinary skill in the art will appreciate that, embodiment described here is that protection scope of the present invention is not limited to so special statement and embodiment in order to help reader understanding's principle of the present invention.Those of ordinary skill in the art can make various other various distortion and combinations of not departing from essence of the present invention according to these technology enlightenment disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (1)
1. an active voltage limit circuit, it is characterized in that, comprise four NMOS tube: M1, M2, M14, M18,14 PMOS: M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M15, M16, M17, two PNP type triode: Q1, Q2, NPN type triode a: Q3, phase inverter and alternative selection circuit;
Concrete annexation is as follows: NMOS tube M1, M2 form current mirror, M1, M2 pipe source ground, current source IB is connected with M1 grid leak, M1 grid connects M18 grid, M2 grid connects M1 grid and drain electrode, M2 drain electrode connects M3 drain and gate, M3 grid connects PMOS M4, M6, M7, M9, M11, M15 grid, M3, M4, M6, M7, M9, M11, M15 source electrode meets high level VDD, M4 drain electrode connects M5 source electrode and Q1 pipe base stage, M5 grounded drain, M5 grid is connected with M10 grid and is connected input voltage V
iN, M6 drain electrode connects PNP type triode Q1, the base stage of Q2 emitter and NPN type triode Q3, Q1, Q2 grounded collector, M7 drain electrode connects Q2 base stage and M8 source electrode, M8 grounded drain, M8 grid connects upper threshold voltage VTH+, M9 drain electrode connects M12 grid and M10 source electrode, M10 grounded drain, M11 drain electrode connects M12 and M13 source electrode, M12 grounded drain, M13 drain electrode connects M14 drain and gate and inverter input, M14 source ground, M15 drain electrode connects M13 grid and M16 source electrode, M16 grounded drain, M16 grid connects threshold voltages VTH-, NPN type triode Q3 collector meets high level VDD, Q3 emitter connects M17 source electrode, M17 grid is connected and output voltage VA with drain electrode, M17 drain electrode connects M18 drain electrode, M17 grid connects the B input end of alternative selection circuit, M18 source ground, the A input end of alternative selection circuit connects threshold voltages VTH-, inverter output connects the Enable Pin EN of alternative selection circuit, the output terminal output voltage V of alternative selection circuit
oUT,
Work as V
iNduring <VTH-, Enable Pin EN is high level, and alternative selection circuit exports VTH-; Work as VTH-<V
iNduring <VTH+, output voltage VA follows V
iNchange, Enable Pin EN is low level, and alternative selection circuit exports VA; Work as V
iNduring >VTH+, output voltage VA is fixed as VTH+, and Enable Pin EN is low level, alternative selection circuit output voltage VTH+.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310380044.7A CN103440010B (en) | 2013-08-27 | 2013-08-27 | Active voltage limiting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310380044.7A CN103440010B (en) | 2013-08-27 | 2013-08-27 | Active voltage limiting circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103440010A CN103440010A (en) | 2013-12-11 |
| CN103440010B true CN103440010B (en) | 2015-01-07 |
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| CN201310380044.7A Expired - Fee Related CN103440010B (en) | 2013-08-27 | 2013-08-27 | Active voltage limiting circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1624486A (en) * | 2003-12-02 | 2005-06-08 | 精工电子有限公司 | Voltage detecting circuit |
| CN1909369A (en) * | 2005-08-02 | 2007-02-07 | 三星电机株式会社 | Voltage comparator having hysteresis characteristics |
| CN102160271A (en) * | 2008-09-22 | 2011-08-17 | 富士通株式会社 | Control method for power control circuit, power supply unit, power supply system, and power controller control method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02182017A (en) * | 1989-01-09 | 1990-07-16 | Sumitomo Electric Ind Ltd | Comparator circuit |
| JP2006261143A (en) * | 2005-03-15 | 2006-09-28 | Rohm Co Ltd | Thermal protection circuit and semiconductor integrated circuit device provided therewith |
| EP2296271B1 (en) * | 2008-06-09 | 2015-08-12 | Shimadzu Corporation | Limiter circuit |
-
2013
- 2013-08-27 CN CN201310380044.7A patent/CN103440010B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1624486A (en) * | 2003-12-02 | 2005-06-08 | 精工电子有限公司 | Voltage detecting circuit |
| CN1909369A (en) * | 2005-08-02 | 2007-02-07 | 三星电机株式会社 | Voltage comparator having hysteresis characteristics |
| CN102160271A (en) * | 2008-09-22 | 2011-08-17 | 富士通株式会社 | Control method for power control circuit, power supply unit, power supply system, and power controller control method |
Non-Patent Citations (3)
| Title |
|---|
| JP平2-182017A 1990.07.16 * |
| JP特开2006-261143A 2006.09.28 * |
| 赵树军.CMOS轨到轨电压跟随器的设计及优化.《黑龙江工程学院学报(自然科学版)》.2013,第27卷(第2期),第61-64. * |
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| CN103440010A (en) | 2013-12-11 |
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