JPH02182017A - Comparator circuit - Google Patents

Abstract

PURPOSE:To reduce the effect on a comparator circuit due to an offset by obtaining a level fluctuation such as a prescribed voltage drop from a level shift means. CONSTITUTION:An emitter of a transistor(TR) Q3 being a component of an emitter follower amplifier circuit being an impedance conversion means is connected to a base of a TR Q1 being a 1st input terminal of a differential amplifier circuit via a resistor r5 being a level shift means, and a constant current source 1 is connected to a connecting point between the resistor r5 and a base of the TR Q1. A part of the differential amplifier circuit comprising mainly the TRs Q1, Q2 outputs a signal in response to a potential difference given to bases of the TRs Q1, Q2. Since a difference of base voltages of the TRs Q1, Q2 is increased in advance because of the level shift of r5I1 and then compared, the operation with less effect by an offset is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a comparison circuit that can be used for detecting various signals.

[Conventional technology]

As shown in FIG. 5, a conventional comparison circuit (comparator) 500 is provided with offset adjustment terminals 501 and 502, and offset adjustment resistors r3' are connected between these terminals and the ground level. , this resistance r,
“The offset was adjusted by changing the value of 4 as appropriate.

A concrete example of the input stage of the circuit shown in FIG. 5 is shown in FIG. This comparison circuit consists of transistors Q,
Q and resistance r, r and constant current source 1 2
This is a circuit consisting of 1 2 600. In this circuit, the resistance r
, r are given a ground level, and a constant current source 600 is given a voltage of 1, to form a differential amplifier circuit using transistors eQ and Q2. Here, an input signal (IN) is applied to the base of the transistor Ql, a bias voltage is applied to the base of the transistor Q2, and an output signal is obtained from the collectors of the transistors Q1 and Q2.

However, strictly speaking, the base-emitter voltage v, ■ of transistors Q and Q2 is −BEI
[3B2 No. That is, about 58 for IV-V l.
A difference of about 10 mV from EI BIE2 mV occurs, and when the input signal and bias voltage are compared, an error occurs in the comparison result. Therefore, as mentioned above, the offset adjustment resistors r and r
The transistors Q and Q are 3 4
The output signals V and ■ in an unmanned state are made to closely match each other by connecting between the L2 vector and the ground and trimming either one of the resistors r and r.

[Problem to be solved by the invention]

However, the comparison circuit configured as described above has the problem that trimming is necessary and cumbersome, and it takes a long time for adjustment when configuring the circuit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a comparison circuit that does not require the troublesome work of trimming and can prevent offset from greatly affecting the sensitivity of the circuit.

[Means to solve the problem]

A comparator circuit according to the present invention is a differential amplifier circuit that outputs a signal corresponding to a potential difference between signals applied to a first input terminal and a second input terminal. Impedance conversion means for eliminating the influence of the differential amplifier circuit on the input signal is connected to the second input terminal, and this impedance conversion means and the first. It is characterized in that a level shift means is connected to at least one of the terminals between the input terminal and the second input terminal.

[Effect]

Since the comparator circuit according to the present invention is configured as described above, it is possible to obtain a level variation such as a predetermined voltage drop by the level shift means, and this level variation can be used to control the comparator circuit as follows. The effect of offset can be reduced.

A current II2 1 flows through the resistors r and r into the transistor Q1゜Q as shown in FIG.
2 cl' In the differential amplifier circuit into which c2 flows, the current II due to the potential difference (V - V )l between the signals applied to the bases of the transistors Q and Q2
Sui Sochi 1 2 cl'
Assume that the c2 ing characteristic is as shown in FIG. That is, it is shown that switching is completely performed at I VI V2 l = 100 mV. Here, assuming that the offset of the differential amplifier circuit is ±10 mV, the above switching is IVIV21-1-9O
It will be performed at ~110 mV. The above typical (t
The error during switching, taking into account the offset to the potential difference where ypical ) switching is performed, is (V - V )/(Vl - V2), , p - (90
/100) ~ (110/100) -〇, 9 ~ 1.1
...(1).

On the other hand, the voltage drop is caused by the level shift means of the present invention to obtain the above-mentioned potential difference I Vl-V.

A potential difference of 100 mV is generated from the beginning.

Here, if switching is performed with a potential difference IV-V21 of 100 mV according to the switching characteristics shown in FIG. 100
rn Vl −', I V V 2 + −200m Vl represents the actual switching. Here, if we calculate the error by considering the same offset as above, we get (V - V
)/(V -V,,)t,p- (190/200)
~(210/200)-0,95~1.05
...(2), and it can be seen that the error is compressed compared to equation (1), and the influence of the offset on the comparator circuit can be reduced.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2 of the accompanying drawings. In the description of the drawings, the same elements are given the same reference numerals and redundant description will be omitted.

FIG. 1 is a circuit diagram showing a comparison circuit according to an embodiment of the present invention. In the figure, constant current sources 1 and 3 flow current l, and constant current source 2 flows current ! . flow.

■ Current I of constant current source 2. A voltage of -Vee is applied to the downstream side where the current flows, and transistors Q and Q2 are applied to the upstream side.
The emitter of transistor Q2 is connected, and a resistor is connected between the collector of transistor Q2 and ground.
, r2 are connected. A resistor r serving as a level shift means is connected to the base of the transistor Q1, which is the first input terminal of the differential amplifier circuit configured in this way.
5 is connected to the emitter of a transistor Q3 constituting an emitter follower amplifier circuit, which is an impedance conversion means, and a constant current source 1 is connected to the connection point between the resistor r5 and the base of the transistor Q1. Further, the emitter of a transistor Q4 constituting an emitter follower amplification circuit, which is an impedance conversion means, is connected to the base of a transistor Q2, which is a second input terminal of the differential amplifier circuit, and a constant current source 3 is also connected. There is. Constant current source 1.
A voltage of -V is applied to the downstream side of 3. The collectors of transistors Q 1 and Q 2 are connected to ground. And transistor Q
A signal to be compared is applied to the base of transistor Q4, and a bias voltage is applied to the base of transistor Q4. Then, output signals are obtained from the collectors of transistors Q1 and Q2.

In the comparator circuit having such a configuration, the portion of the differential amplifier circuit mainly composed of transistors Q11Q2 is already connected to the sixth transistor.
As explained with reference to the figure, transistors Q and Q
outputs a signal according to the potential difference applied to the base of the However, due to the resistance 5, if the base current of transistor Q1 is ignored, a voltage drop of 511 will always occur on the emitter side of transistor Q.In other words, this level shift of r5I will cause the base voltage of transistors Q1 to Q2 to drop. Since the comparison operation is performed after the difference is increased in advance, it is possible to ensure an operation that is less affected by the offset as described above.

FIG. 2 shows the configuration of a type of detector to which the above comparison circuit is applied. In this circuit, a resistor R9 is connected between the base of the transistor Q and the ground to create a fundamental voltage for comparison. Further, a resistor RPD (RPD-RD) is connected between the base of the transistor Q4 and the ground, and the cathode of the photodiode 4 is connected to the base of the transistor Q4. In the circuit configured in this way, when the current I flowing through the photodiode 4 becomes less than a predetermined value, the comparison result between V and v2 is Based on the result of comparison with V t +V 2 transmitted without influence of the circuit), switching of the collector currents of the transistors Q and Q2 occurs, and detection is performed.

Here, considering the influence of offset, it is as follows. If the base-emitter voltage of transistors Q and Q is V and ■, then BF2 8E4 V --RD (11/h, o).

v --RPD(x+11/h,.)11'°V
”” V V BF2 r 51 t.

v2''=v2-VBB4. On the other hand, from the formula of the differential amplifier circuit, r - [h
/ (1+ hr8) 11 rs (IO/rl+ expt(v 1)/Vol]
) ... (3) t = t h / (1+ h r8) )2
re O-V' )/Vol]) (1/[l+cxpl-(v 1' 2... (
4) (v; constant -26 mV), and -■ vl 2 ``-Rpd'' 5 Il - ■BE3. Here, if we set V -V -V BF2 BH3d, 'BH3 V vl 2 -RI-rs 1l-Vd...(5
)d, so let equation (5) be ΔV.

Inserting this into equations (3) and (4), i-t h / (1+ h ro) )l
fe [1/ (1+exp (Δv/vo)l]...
(6) t” (h / (1”, h r8) )2
re [1/tl+exp(-Δv/vo)
l]... (7) is obtained. The comparator circuit operates when 1-V2. Therefore, rx 11-r2 12...
-(8) holds true. On the other hand, exp (Δv / v O) −Xrh I
/(1+hro)-10I'eO, then from equations (6), (7), and (8), r I
'11/(1+x)J O -r I'(1/(1+x-')1.x-ex
p(Δy/v)=r1/r2. By taking the logarithm of both sides, Δv−R1−r
s1-VdD ″vOIn”1 ”2) ,-, RPDl (r/r) + rs It 10Vd=vO
ln l 2 (9). Also, ■−ηP...(10)
It is. Here, P is the power in dB. P in the display layer is 10-d/10-3, and η is the conversion efficiency.

This power P is calculated from equations (9) and (10) as P − (v
lln(r/r)/RpI)771+(
r I +V )/RPD771 −(11)0
d. From this equation (11), v −o and vd−V′
When the ratio of the power P is calculated, it becomes '/P P (Vd -v) (Vd -0). In the above formula (12), X−V 11! +1 r/r)/
(RPDη).

The formula for the ratio of this power P is BH38 between V and V
E4 The difference between the power ■ and V when there is no difference (so to speak, no offset) is v', and E3 8
Since this is the power ratio when E4 is present (so to speak, when there is an offset), the larger the ratio value, the more the quality is affected by the offset. And the above inequality (12) becomes rs-
This proves that when rs is set to 0 and is brought closer to the conventional circuit, the value of the ratio becomes larger (easier to be affected by offset) than in this embodiment in which rs has a predetermined value.

The invention is not limited to the above embodiments.

For example, a diode or the like can be used instead of a resistor as the level shift means. Further, the emitter follower amplifier circuit may be of any other type as long as it performs impedance conversion on the applied signal so as not to affect the differential amplifier circuit. Furthermore, although it is sufficient to connect the level shift means to one of the first and second input terminals of the differential amplifier circuit, even if it is connected to both, by making the level shift amount different for each, it is possible to You can get the same effect as when connected.

〔Effect of the invention〕

As described in detail above, in the present invention, the level fluctuation caused by the level shift means is used to control the first and second differential amplifier circuits.
It is possible to increase the potential difference during switching between the input terminals of
This has the effect that the influence of the offset is relatively small, and the offset does not greatly affect the sensitivity of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a comparison circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a detector configured using the embodiment shown in FIG. 1, FIG. 3 is a block diagram of a differential amplifier circuit, and FIG.
Figure 5 is a diagram showing the switching characteristics of a differential amplifier circuit.
FIG. 6, a block diagram showing a conventional comparison circuit, is a detailed configuration diagram of the comparison circuit shown in FIG. 1 to 3...constant current source, 4...photodiode, Q
-Q ・) - transistor, r, r, rs. l 4 1 2 Ro・RPD"'Resistance O Example configuration Fig. 1 VrVdV] Fig. 4 Fig. 5

Claims (1)

[Claims] 1. An input terminal is connected to the first and second input terminals of a differential amplifier circuit that outputs a signal according to the potential difference between the signals applied to the first input terminal and the second input terminal. Impedance conversion means for eliminating the influence of the differential amplifier circuit on the signal is connected, and the impedance conversion means and the first,
A comparison circuit characterized in that a level shift means is connected to at least one of the terminals between the comparison circuit and the second input terminal. 2. The comparison circuit according to claim 1, wherein the impedance conversion means is an emitter follower amplifier circuit, and the level shift means is a resistor.