JP6601277B2 - Fault detection circuit for switching element - Google Patents

Description

  The present invention relates to a failure detection circuit that detects a failure of a switching element.

  2. Description of the Related Art Conventionally, switching circuits using switching elements are widely used in, for example, motor drive circuits and DC-DC converters. Such a switching circuit may be used for applications where a relatively high voltage is applied. In that case, if the switching element fails, a power fault or ground fault occurs, a large current flows, and the switching element and peripheral circuit components may be damaged. Therefore, for example, as disclosed in Patent Document 1, damage to the switching element is prevented by setting a threshold and detecting the occurrence of overcurrent or overvoltage.

Japanese Patent Laid-Open No. 2005-006464

  Since a large current flows as described above when a switching element fails, it is desired that the failure detection circuit can realize accurate failure detection regardless of the operating state of the switching element. In a switching circuit, the switching frequency may be increased in order to reduce the size of peripheral components such as capacitors and coils. Therefore, it is also desired that the failure detection circuit can quickly detect a failure. However, conventionally, there has been no failure detection circuit that can meet these demands with a simple configuration.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to realize a failure of a switching element that can detect a failure quickly and accurately regardless of the operating state of the switching element while simplifying the circuit configuration. It is to provide a detection circuit.

The failure detection circuit (1) according to claim 1 detects a failure of a switching element (Q2, Q20, Q22, Q24, Q26, Q28, Q30) used in the switching circuit, and comprises a level conversion circuit ( 11) and a failure determination circuit (12). The level conversion circuit converts the voltage amplitude of the output node whose voltage fluctuates when the switching element to be detected switches, into a signal having a voltage amplitude smaller than the voltage amplitude at the output node. The failure determination circuit determines a failure of the switching element based on the signal having a small voltage amplitude converted by the level conversion circuit.

  In this case, since the level conversion circuit only converts the magnitude of the voltage amplitude, it is possible to determine a failure based on a signal having a timing that matches the amplitude of the voltage at the output node. Therefore, the failure of the switching element can be detected quickly. The level conversion circuit includes a current source that outputs a predetermined current, and a level conversion diode that is connected between the output node and the current source with the current source side as an anode. Therefore, the circuit configuration can be simplified, and the failure of the switching element can be detected with a simple configuration. Furthermore, since the voltage amplitude can be reduced, a semiconductor circuit manufactured by, for example, a CMOS process can be used for the failure determination circuit, and a failure can be detected quickly.

  Depending on the application of the switching element to be detected, another circuit element may be connected to the output node. For example, when the switching element is used in a switching circuit such as a DC-DC converter, a diode having a large leak or a smoothing capacitor having a large capacity may be connected to the output node. In this case, in the period when the operation of the switching element is stopped, even if the switching element is not short-circuited, most of the current output from the current source flows to the other circuit element side, and the output The voltage of the node cannot be raised, which may cause false detection.

Therefore, the current source outputs a current having a first current value during a period when the switching circuit is operating, and has a second current value that is larger than the first current value during a period when the operation of the switching circuit is stopped. Output current. In this way, even when a diode with a large leak is connected to the output node, if the switching element is not short-circuited during the period when the operation of the switching element is stopped, the output node The voltage can be raised, and the occurrence of the erroneous detection described above can be prevented. Therefore, according to the configuration of this means, a failure of the switching element can be detected quickly and accurately regardless of the operating state of the switching element.

The figure which shows typically the structure of the failure detection circuit which concerns on 1st Embodiment. A diagram schematically showing one specific configuration example of a current source A diagram schematically showing the relationship of voltage amplitude at each detection point Flow chart showing overall flow of operation by failure detection circuit Flow chart showing start-up detection process Flow chart showing short detection process Flow chart showing open detection process Timing chart showing specific detection examples of short-circuit failure and open failure The flowchart which shows the short detection process which concerns on 2nd Embodiment. Flow chart showing open detection process Timing chart showing examples of detection of short-circuit failure and open failure Flowchart showing a short detection process according to the third embodiment. Flow chart showing open detection process Timing chart showing examples of detection of short-circuit failure and open failure FIG. 1 schematically shows another configuration of the failure detection circuit according to the fourth embodiment. FIG. 2 schematically showing another configuration of the failure detection circuit FIG. 3 schematically showing another configuration of the failure detection circuit FIG. 4 schematically showing another configuration of the failure detection circuit FIG. 5 schematically showing another configuration of the failure detection circuit FIG. 6 schematically showing another configuration of the failure detection circuit FIG. 7 schematically showing another configuration of the failure detection circuit The figure which shows other composition of constant current circuit typically FIG. 1 schematically showing another configuration of the current source FIG. 2 schematically showing another configuration of the current source FIG. 8 schematically showing another configuration of the failure detection circuit The figure which shows the example of the switching circuit which becomes the detection object typically The figure which shows the example of the structure which switches the electric current supplied to an output node typically The figure which shows the application example which uses the level conversion circuit independently

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, the failure detection circuit 1 detects a failure of a switching element used in the switching circuit 2. In the present embodiment, the failure detection circuit 1 is accommodated in the package of the semiconductor device 100.

  The switching circuit 2 includes field effect transistors (hereinafter simply referred to as transistors) Q1 and Q2, diodes D1 and D2, a coil L1, and a capacitor C1. The transistor Q1 has a drain connected to the drive power supply VS and a source connected to the cathode of the diode D1. The anode of the diode D1 is connected to the ground GND serving as the reference potential of the circuit. The transistor Q2 has a source connected to the ground GND and a drain connected to the anode of the diode D2.

  Coil L1 is connected between the interconnection point of transistor Q1 and diode D1 and the interconnection point of transistor Q2 and diode D2. The capacitor C1 is connected between the cathode of the diode D2 and the ground GND. A load 3 such as an LED is connected between both terminals of the capacitor C1. Such a switching circuit 2 is used in, for example, a step-up / step-down DC-DC converter.

  Transistors Q1 and Q2 corresponding to the switching elements are supplied with a drive signal output from the drive circuit 4 at their gates, and on / off is controlled by the drive signal. In the present embodiment, among these switching elements, the transistor Q2 is a failure detection target by the failure detection circuit 1. In the following description, outputting a drive signal for turning on the transistor Q1 or Q2 is also referred to as “outputting an on drive signal” and outputting a drive signal for driving off. It is also called “OFF drive signal is output”.

  When the boosting operation is performed, the transistor Q1 is always turned on and the transistor Q2 is repeatedly turned on and off, whereby electric power is supplied to the load 3 through the diode D2. As described above, when the transistor Q2 performs a switching operation that repeatedly turns on and off, the potential on the drain side of the transistor Q2 varies. That is, in the present embodiment, the interconnection node between the transistor Q2 and the diode D2 corresponds to an output node whose voltage fluctuates when the switching element is switched. The output node is connected to the failure detection circuit 1. In the following description, the output node is also referred to as “input” to the failure detection circuit 1.

  The failure detection circuit 1 includes a level conversion circuit 11 having a current source 10 and a failure determination circuit 12 that determines failure of the transistor Q2. The failure determination circuit 12 includes a comparator 13 and a determination unit 14. In this embodiment, the comparator 13 is manufactured by a CMOS semiconductor process and corresponds to a logic circuit. The level conversion circuit 11 converts the voltage amplitude at the output node of the transistor Q2 to be detected into a signal having a voltage amplitude smaller than the voltage amplitude at the output node.

  The current source 10 has a function of switching the output current value in two stages. Specifically, the current source 10 outputs a first current value state (hereinafter referred to as a small current output state) based on the switching signal Sa given from the failure determination circuit 12, and the first current value. It is possible to switch to either a state in which a current having a larger second current value is output (hereinafter referred to as a large current output state).

  As the current source 10, for example, a configuration as shown in FIG. 2 can be adopted. The current source 10 shown in FIG. 2 includes two constant current circuits 15 and 16. The constant current circuit 15 includes two bipolar transistors Tr1 and Tr2 and a constant current source 17. The transistors Tr1 and Tr2 have their emitters connected to the power supply VCC and their bases connected in common to form a current mirror circuit. A constant current source 17 is connected between the collector of the so-called diode-connected transistor Tr1 and the ground GND. With such a configuration, the constant current Ia corresponding to the output current of the constant current source 17 is output from the collector of the transistor Tr2. The current value of the constant current Ia corresponds to the first current value.

  The constant current circuit 16 includes two bipolar transistors Tr3 and Tr4 and a constant current source 18. The transistors Tr3 and Tr4 have their emitters connected to the power supply VCC and their bases connected in common, forming a current mirror circuit. A constant current source 18 is connected between the collector of a so-called diode-connected transistor Tr3 and the ground GND. With such a configuration, the constant current Ib corresponding to the output current of the constant current source 18 is output from the collector of the transistor Tr4. A current value obtained by adding the current value of the constant current Ia to the current value of the constant current Ib corresponds to the second current value. The operating state of the constant current source 18 is switched by a switching signal Sa.

  In such a configuration, the collectors of the transistors Tr 2 and Tr 4 are commonly connected, and the commonly connected collector corresponds to the output terminal of the current source 10. Therefore, when the constant current source 18 is deactivated by the switching signal Sa, the current source 10 outputs only the current output from the constant current circuit 15, that is, the small current output that outputs the current of the first current value. It becomes a state. When the constant current source 18 is activated by the switching signal Sa, the current source 10 outputs a current that is a sum of currents output from the two constant current circuits 15 and 16, that is, a current having a second current value. Is in a large current output state.

  As shown in FIG. 1, a diode D <b> 3 is provided between the current source 10 and the switching circuit 2. The diode D3 has a cathode connected to the output node of the transistor Q2, and an anode connected to the output terminal of the current source 10. The diode D3 corresponds to a level conversion diode.

  A diode D4 is provided between the current source 10 and the failure determination circuit 12. The diode D4 has an anode connected to the output terminal of the current source 10 and a cathode connected to the failure determination circuit 12 side. The diode D4 has a temperature characteristic common to the diode D3, and corresponds to a temperature compensating diode. In addition, a pull-down resistor R1 connected to the ground GND is provided between the diode D4 and the failure determination circuit 12 side. The resistor R1 corresponds to a resistance element.

  Here, the interconnection point of the diode D3 and the diode D4 is point A, the cathode side of the diode D4, that is, the input side to the failure determination circuit 12, is point B, and the cathode side of the diode D3, that is, the output node side of the transistor Q2. Is point C. As described above, the diode D4 has a temperature characteristic common to the diode D3. The diode D3 is arranged so that the direction from the point A to the point C is the forward direction, and the diode D4 is arranged so that the direction from the point A to the point B is the forward direction. That is, the diodes D3 and D4 are arranged so that the forward directions are opposite to each other in the path from the point C to the point B with the point A as the center.

  Therefore, the temperature characteristic of the diode D3 is canceled by the temperature characteristic of the diode D4. As a result, the temperature characteristic of the voltage converted by the level conversion circuit 11 is eliminated. That is, in this embodiment, the level of the voltage amplitude can be converted in a constant state without depending on the temperature.

  Further, a Zener diode D5 is provided between the current source 10 and the failure determination circuit 12, more strictly between the diode D4 and the comparator 13 in the present embodiment. The Zener diode D5 is connected between the point B and the ground GND with the ground GND side as an anode. The Zener diode D5 corresponds to a voltage limiting element that limits the voltage at the output terminal of the current source 10, and prevents saturation of the transistors Tr2 and Tr4 of the current source 10.

  The comparator 13 converts the voltage amplitude converted by the level conversion circuit 11 into a voltage amplitude in a range that can be handled by the CMOS semiconductor circuit (hereinafter referred to as a CMOS level for convenience) in this embodiment. The comparator 13 has a non-inverting input terminal connected to the output of the level conversion circuit 11, that is, the point B, and an inverting input terminal connected to the reference voltage source 19.

  Therefore, assuming that the voltage generated by the reference voltage source 19 is the threshold voltage Vth, when the potential at the point B is higher than the threshold voltage Vth, an H level signal is output from the comparator 13 at the CMOS level, and the potential at the point B is When the voltage is lower than the threshold voltage Vth, the comparator 13 outputs an L level signal at the CMOS level. The voltage amplitude at the CMOS level is smaller than the voltage amplitude at the output node of the transistor Q2.

  The determination unit 14 determines the failure of the transistor Q2 based on the small voltage amplitude signal converted by the level conversion circuit 11. More specifically, in the case of the present embodiment, the determination unit 14 is configured by a small-scale logic circuit made of a CMOS semiconductor circuit, and the transistor Q2 based on the CMOS level signal converted by the comparator 13 Determine failure. Usually, since the CMOS semiconductor circuit can operate at high speed, the determination unit 14 can quickly determine the failure of the transistor Q2, as will be described later. The output of the determination unit 14 is output to, for example, a microcomputer outside the semiconductor device 100 or used for control within the semiconductor device 100.

  The determination unit 14 is provided with an operation request signal Sb for requesting an operation start from the outside. When determining that the operation start is requested based on the operation request signal Sb, the determination unit 14 starts the operation. Further, the determination unit 14 is given an output of the comparator 13 and a drive signal for driving the transistor Q2. The determination unit 14 determines a failure of the transistor Q2 based on the output of the comparator 13 and the drive signal.

  Specifically, the determination unit 14 executes a short detection process and an open detection process, which will be described later, and determines a failure of the transistor Q2 by these detection processes. The short detection process is a process for detecting a short circuit failure of the transistor Q2, that is, a state in which the transistor Q2 remains turned on. The open detection process is a process for detecting an open failure of the transistor Q2, that is, a state in which the transistor Q2 remains off.

  In addition to the failure of the transistor Q2, for example, when other peripheral components such as the diode D1 and the load 3 fail, a so-called ground fault may occur that short-circuits with the ground GND. There may be a so-called skyline that shorts between the two. In the present embodiment, the former can be detected by a short detection process and the latter can be detected by an open detection process.

Next, the operation of the above configuration will be described.
<Voltage amplitude conversion mode>
First, a voltage amplitude conversion mode in the level conversion circuit 11 and the comparator 13 will be described. Here, assuming that the forward voltage of the diode D3 and the diode D4 is Vf, the Zener voltage of the Zener diode D5 is Vz, and the collector-emitter saturation voltage of the transistors Tr2 and Tr4 is Vsat, “Vz <VCC−Vsat−Vf”, It is assumed that the relationship “Vz> Vth” is satisfied.

  When the on-drive signal is output and the transistor Q2 is turned on, or when a short fault described later occurs, the voltages at the points B and C become substantially the same, and the output of the comparator 13 becomes L level. On the other hand, when an off drive signal is output and the transistor Q2 is turned off, or when an open failure occurs as will be described later, the voltages at the points C and B rise, but the voltage at the point B is the zener diode D5. And is fixed at the Zener voltage Vz. Since the voltage at the point B becomes Vz, it becomes higher than the threshold voltage Vth, and the output of the comparator 13 becomes H level.

  Therefore, when the switching circuit 2 is driven, as shown in FIG. 3, at point C corresponding to the input, the voltage can oscillate in the range up to VS or more, but at point A, the voltage oscillates in the range up to Vf + Vz. At point B, the voltage swings in the range up to Vz. Further, the voltage amplitude at the point B is compared with the threshold voltage Vth by the comparator 13, and if it is higher than Vth, an H level signal is output, and if it is lower than Vth, an L level signal is output.

  In other words, in the present embodiment, the voltage amplitude of the output node of the transistor Q2 is first converted into a signal having a voltage amplitude smaller than the voltage amplitude of the output node by the level conversion circuit 11, and further, the comparator 13 outputs the signal of the output node. It is converted into a CMOS level signal (hereinafter also referred to as the output of the comparator 13 for convenience) having a voltage amplitude smaller than the voltage amplitude.

<Overall Flow of Operation by Fault Detection Circuit 1>
The determination unit 14 performs a series of operations as shown in FIG. That is, in step S101, it is determined whether or not there is an activation request. Here, if it is determined that there is a startup request, that is, if “YES” in the step S101, the process proceeds to a step S102, and a startup detection process is performed. The startup detection process is a process performed during a period in which the operation of the transistor Q2 that is a failure detection target is stopped, and is a process as illustrated in FIG.

  When the startup detection process is started, first, in step S201, the output state of the current source 10 is switched to the “large current output state”. In subsequent step S202, the short detection process shown in FIG. 6 is executed. As a result of executing the short detection process, if a predetermined time elapses without detecting a short failure, that is, if “YES” in the step S203, the process proceeds to a step S204.

  In step S204, the output state of the current source 10 is switched to the “small current output state”, and the startup detection process ends. Although not shown, if a short circuit failure is detected as a result of the short detection process, the process immediately proceeds to step S204, and the output state of the current source 10 is switched to the “small current output state”. It is done. Note that the determination unit 14 switches the output state of the current source 10 by changing the level of the switching signal Sa. Further, in the present embodiment, the predetermined time described above is, for example, 10 ms.

  When the startup detection process ends, the process proceeds to step S103, and the normal detection process is performed. The normal-time detection process is a process performed during a period in which the transistor Q2 that is a failure detection target is operating. Therefore, the operation of the switching circuit 2 is also started at the timing when the normal detection process is started. In the normal detection process, the short detection process and the open detection process shown in FIG. 7 are repeatedly executed in parallel.

<Details of short detection processing and open detection processing>
Here, first, the flow of the short detection process and the open detection process will be described with reference to the flowcharts of FIGS. 6 and 7, and then a specific detection example will be described with reference to the timing chart of FIG. In FIG. 8, the state of the drive signal when turning on the transistor Q2 is ON, the state of the drive signal when turning off the transistor Q2 is OFF, and the H level signal output from the comparator 13 or the like is simply “H”. The L level signal output from the comparator 13 or the like is simply indicated as “L”.

Flow of “1” short detection process When the short detection process shown in FIG. 6 is started, first, in step S301, the determination unit 14 changes the state of the drive signal, that is, within one cycle of the drive pattern of the switching element. Monitor the comparator output. In the present embodiment, the period from when the drive signal is turned on to when it is turned off, and again from when it is turned on, that is, the period from the rise of the drive signal to the next rise is defined as one cycle of the drive pattern. Even when the period from the falling edge of the driving signal to the next falling edge is one cycle of the driving pattern, the failure can be detected by a substantially common process.

  In step S302, the determination unit 14 determines whether or not the H level is detected within one cycle of the drive pattern. When the determination unit 14 detects an H level signal, that is, when “YES” is determined in the step S302, the determination unit 14 determines that a short circuit failure has not occurred, and returns to the step S301 to repeat the processing. If the determination unit 14 does not detect an H level signal, that is, if “NO” in step S302, the determination unit 14 determines that a short circuit failure has occurred, and proceeds to step S303. In step S303, the determination unit 14 outputs a signal indicating that a short circuit has been detected, that is, a short circuit failure has been detected.

[2] Flow of Open Detection Process When the open detection process shown in FIG. 7 is started, first, in step S401, the determination unit 14 monitors the comparator output within one cycle of the switching element drive pattern. In subsequent step S402, the determination unit 14 determines whether or not the L level is detected within one cycle of the drive pattern. If the determination unit 14 detects an L-level signal, that is, if “YES” in step S402, it determines that an open failure has not occurred, and returns to step S401 to repeat the processing.

  If the determination unit 14 does not detect the L level signal, that is, if “NO” in step S402, the determination unit 14 determines that an open failure has occurred, and proceeds to step S403. In step S403, the determination unit 14 outputs a signal indicating that an open detection, that is, a short failure has been detected.

“3” Specific Detection Example First, a case is assumed in which the comparator output changes following the drive pattern, for example, “normal” shown in FIG. In this case, since the H level is detected within one cycle in the short detection process and the L level is detected within one period in the open detection process, the determination unit 14 performs the short detection and the open detection. Neither is output. In this case, it can be determined that no failure has occurred in the transistor Q2.

  Next, let us assume a case where a short circuit failure occurs after the drive pattern is turned on, as in “at the time of a short circuit failure” shown in FIG. In this case, the transistor Q2 remains on, that is, remains conductive even when the drive pattern is turned off. Therefore, when a short circuit failure occurs, the output of the comparator 13 is fixed at the L level. That is, unlike the period of “one cycle L level continues” shown in FIG. 8, the comparator output does not become H level within one cycle of the drive pattern. Therefore, the determination unit 14 outputs short detection in the short detection process. In this case, it can be determined that a short circuit failure has occurred in the transistor Q2.

  Next, a case is assumed where an open failure occurs when the drive pattern is turned on, as in “open failure” shown in FIG. In this case, even if the drive pattern is turned on, the transistor Q2 remains off, that is, does not conduct. Therefore, when an open failure occurs, the output of the comparator 13 is fixed at the H level. That is, unlike the period of “one cycle H level continues” shown in FIG. 8, the comparator output does not become L level within one cycle of the drive pattern. Therefore, the determination unit 14 outputs open detection in the open detection process. In this case, it can be determined that an open failure has occurred in the transistor Q2.

  As described above, the failure detection circuit 1 determines whether or not the state of the signal having a voltage amplitude smaller than the output node of the transistor Q2 changes following the change of the state of the drive signal. A failure is detected.

According to this embodiment described above, the following effects can be obtained.
The failure detection circuit 1 converts the voltage amplitude at the output node of the transistor Q2 to be detected in the level conversion circuit 11 into a signal having a voltage amplitude smaller than the voltage amplitude at the output node, and the converted signal having a small voltage amplitude. Based on the above, the failure determination circuit 12 determines the failure of the transistor Q2. In this case, since the level conversion circuit 11 only converts the magnitude of the voltage amplitude, it is possible to determine a failure based on a signal having a timing that matches the amplitude of the voltage at the output node. Therefore, the failure of the switching element can be detected quickly.

  At this time, the level conversion circuit 11 includes a current source 10 and a diode D3 which is a conversion diode having a cathode connected to the output node of the transistor Q2 and an anode connected to the current source 10. . Therefore, the circuit configuration can be simplified, and the failure of the switching element can be detected with a simple configuration. Further, since the voltage amplitude can be reduced, a semiconductor circuit manufactured by, for example, a CMOS process can be used for the failure determination circuit 12, and a failure can be detected quickly.

  Further, since the level conversion circuit 11 does not require a capacitor, charging and discharging of the capacitor is not required at the time of level conversion, and level conversion can be performed quickly. Since the level can be quickly changed, even when the transistor Q2 is in operation or when the switching speed is high, a signal that follows it can be generated, and high-speed detection can be performed. Is possible.

  Since a Zener diode D5, which is a voltage limiting element that limits the voltage at the output terminal of the current source 10, is provided between the current source 10 and the failure determination circuit 12, saturation of the transistors Tr2, Tr4, etc. of the current source 10 is prevented. Is done. As a result, the output voltage of the level conversion circuit 11, that is, the voltage of the output terminal of the current source 10, is clamped, and the transistors Tr2 and Tr4 can always be operated in the non-saturation region, and the responsiveness of the current value can be improved. Therefore, level conversion can be performed at high speed.

  When the diode D4, which is a temperature compensating diode having temperature characteristics common to the diode D3, is between the current source 10 and the failure determination circuit 12, the forward direction is opposite to that of the diode D3 when the point A is a reference. Are arranged as follows. Thereby, the temperature characteristic of the diode D3 is canceled by the temperature characteristic of the diode D4. Therefore, the temperature characteristic is excluded or suppressed from the voltage amplitude converted by the level conversion circuit 11. That is, the voltage amplitude level can be converted in a constant state regardless of the temperature. Since the pull-down resistor R1 is provided between the diode D4 and the failure determination circuit 12, the voltage amplitude can be input to the failure determination circuit 12 even when the diode D4 is provided.

  The voltage output from the level conversion circuit 11 and the threshold voltage Vth are compared before the failure determination circuit 12, and the comparison result is converted into a signal having a voltage amplitude of CMOS level smaller than the voltage amplitude of the output node of the transistor Q2. A comparator 13 is provided. The fault detection circuit 1 has a voltage amplitude smaller than that of the output node by providing the level conversion circuit 11. For this reason, it is possible to use a semiconductor logic element manufactured by a fine semiconductor process such as CMOS or BiCMOS and operating at high speed. Thereby, the delay between the voltage amplitude of the output node and the output of the comparator 13 can be reduced, and the change of the output of the comparator 13 and the change of the voltage amplitude of the output node can be handled as the same timing. Therefore, the failure can be detected even during the operation of the transistor Q2 and when the switching speed is high.

  In the short detection process and the open detection process, a failure is determined based on whether the output of the comparator 13 changes following the change in the state of the drive signal, using the comparator output and the drive signal. This makes it possible to reliably determine whether or not the transistor Q2 has failed during the operation of the transistor Q2. At this time, if the comparator output is fixed for one period or more of the drive signal, it is determined that the transistor Q2 has failed. Thereby, a failure can be detected in one cycle at the shortest. That is, a failure can be detected quickly. In addition, since the semiconductor device 100 of this embodiment includes the failure detection circuit 1 described above, it is possible to quickly detect a failure of the transistor Q2 with a simple configuration.

  In the switching circuit 2, a diode D1 is connected to the output node of the transistor Q2 to be detected through the coil L1, and a smoothing capacitor C1 is connected through the diode D2. In this case, a diode having a large leakage current may be used as the diode D1 for the purpose of cost reduction. Further, since the capacitor C1 is intended for smoothing, a capacitor having a relatively large capacity is often used. Therefore, during the period when the transistor Q2 is not operating, the current output from the current source 10 also flows through a path leaking from the coil L1 to the ground GND through the diode D1 in the reverse direction, and the capacitor C1 is connected through the diode D2. It also flows through the charging path.

  At this time, if the current output from the current source 10 is small, even if the transistor Q2 is not short-circuited and is in a normal state, most of the current flows to the diode D1 or capacitor C1 side, and the output node That is, the voltage at point C does not rise. Then, the determination unit 14 may erroneously determine that a short circuit has occurred despite the fact that the transistor Q2 is normal.

  Therefore, in the present embodiment, the current source 10 is in a large current output state during the period when the operation of the transistor Q2 is stopped. In this way, even when a diode having a large leak is used as the diode D1 or when a capacitor having a large capacity is used as the capacitor C1, the transistor Q2 is short-circuited while the operation of the transistor Q2 is stopped. If there is no failure, the voltage of the output node can be raised appropriately, and the erroneous determination described above, that is, the occurrence of erroneous detection can be prevented. Therefore, according to the present embodiment, the failure of the transistor Q2 can be detected quickly and accurately regardless of the operating state of the transistor Q2.

  During the period in which the transistor Q2 is operating, that is, the period in which the switching circuit 2 is performing the boosting operation, the transistor Q1 is always turned on and output from the drive power supply VS via the transistor Q1 and the coil L1. Current is supplied to the node side. Therefore, during the period in which the transistor Q2 is operating, even if the current output from the current source 10 is small, the voltage at the output node can be appropriately raised during the period in which the transistor Q2 is turned off. Therefore, the current source 10 is set to a small current output state during the period in which the transistor Q2 is operating. In this way, current consumption during normal operation can be kept low.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
In the second embodiment, the processing contents in the short detection process and the open detection process are different from those in the first embodiment. The configuration of the failure detection circuit 1 is the same as that of the first embodiment, and will be described with reference to FIG.

  In the case of the present embodiment, the output of the comparator 13 at the time when the drive signal changes, that is, the state of the signal having a voltage amplitude smaller than the output node of the transistor Q2, is different from the corresponding state before the state of the drive signal changes. In this case, it is determined that the transistor Q2 has failed.

  In the switching circuit 2, for example, when the control method of PWM (Pulse Width Modulation) or PFM (Pulse Frequency Modulation) is adopted, the ON time and OFF time of the control signal are longer than the response time of the comparator 13. To do. Note that the ON time is the time that is ON in FIG. 11, and the OFF time is the time that is OFF in FIG. In other words, the pulse width of the control signal from when the control signal is turned on to when it is turned off is longer than the response time of the comparator 13. In the present embodiment, in consideration of such points, the failure of the transistor Q2 is detected as follows.

Flow of “1” short detection processing When the short detection processing shown in FIG. 9 is started, first, in step S311, the determination unit 14 compares the timing at which the drive signal changes to ON, that is, the rise timing of the drive pattern. Monitor the output. In subsequent step S312, the determination unit 14 determines whether the comparator output is at the H level at the rising timing of the drive pattern.

  In an actual circuit component, there is a time required for the transistor Q2 to be turned on, a response time of the comparator 13, and the like, so that the timing at which the state of the drive pattern changes as in the case of “short circuit failure” shown in FIG. That is, there is a slight delay between the timing when the signal is turned ON or OFF and the change in the state is reflected in the output of the comparator 13. Therefore, when switching is performed normally, at the timing when the drive pattern rises, the comparator 13 is in a state corresponding to the state in which the drive pattern is OFF, that is, in this embodiment, a state in which the H level is output. It should be.

  Here, a case is assumed in which a short circuit failure occurs when the drive pattern is turned off, such as “at the time of a short circuit failure” shown in FIG. In this case, the output of the comparator 13 is fixed at the L level. Therefore, at the time of the next drive pattern rising, the output of the comparator 13 remains at the L level. That is, when a short circuit failure occurs, the output of the comparator 13 is not in a state corresponding to the driving pattern being OFF.

  Therefore, when the comparator output at the rising timing of the drive pattern is at the H level, that is, when “YES” in step S312, the determination unit 14 determines that no short failure has occurred, and returns to step S311 for processing. repeat. Further, when the comparator output at the rising timing of the drive pattern is not at the H level, that is, when “NO” is determined in Step S312, the determination unit 14 determines that a short circuit failure has occurred, and proceeds to Step S303 to output a short detection. To do.

“2” Flow of Open Detection Processing When the open detection processing shown in FIG. 10 is started, first, in step S411, the determination unit 14 determines the timing at which the drive signal changes to OFF, that is, the timing at which the drive pattern falls. Monitor the comparator output. In subsequent step S412, the determination unit 14 determines whether or not the comparator output is at the L level at the rising timing of the drive pattern.

  Here, a case is assumed in which an open failure occurs when the drive pattern is turned on, such as “at the time of an open failure” shown in FIG. In this case, the output of the comparator 13 is fixed at the H level. Therefore, at the fall of the next drive pattern, the output of the comparator 13 remains at the H level. That is, when an open failure occurs, the output of the comparator 13 is not in a state corresponding to the drive pattern being ON.

  Therefore, the determination unit 14 determines that an open failure has not occurred when the comparator output at the falling timing of the drive pattern is at the L level, that is, “YES” in step S412, and returns to step S411. repeat. The determination unit 14 determines that an open failure has occurred when the comparator output at the falling timing of the drive pattern is not at the L level, that is, “NO” in step S412, and proceeds to step S403 to detect open detection. Output.

  In the present embodiment described above, the failure detection circuit 1 causes the transistor Q2 to fail when the output of the comparator 13 at the time when the drive signal changes is different from the corresponding state before the state of the drive signal changes. It is determined that Even with such a configuration, the failure of the transistor Q2 can be detected quickly and accurately regardless of the operating state of the transistor Q2 while simplifying the circuit configuration as in the first embodiment.

  In the case of the present embodiment, since the failure is determined at the rising or falling timing of the drive signal, the time required from the occurrence of the failure to the detection can be shortened. In addition, in the unlikely event that the transistor Q2 fails, the time during which a large current flows can be shortened, and the risk of damage to circuit components can be reduced.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
In the third embodiment, the processing contents in the short detection process and the open detection process are different from those in the first embodiment. The configuration of the failure detection circuit 1 is almost the same as that of the first embodiment, and will be described with reference to FIG.

  In the present embodiment, the failure is detected in consideration of the operation delay time of the transistor Q2 with respect to the drive signal and the maximum delay time in the comparator 13. More specifically, in the case of this embodiment, the output of the comparator 13 after a predetermined time from the time when the state of the drive signal changes, that is, the state of the signal having a voltage amplitude smaller than the output node of the transistor Q2, The failure is determined based on whether or not the change follows the change.

Flow of “1” short detection process When the short detection process shown in FIG. 12 is started, the determination unit 14 first monitors the output of the comparator 13 after the drive pattern is turned off in step S321. . In the subsequent step S322, the determination unit 14 determines whether or not the comparator output is at the H level after a predetermined time from when the drive pattern is turned off, that is, after a predetermined time from the rising timing of the drive pattern. That is, the determination unit 14 determines whether or not the comparator output is at the H level after the drive pattern has changed and when the change has been reflected. The predetermined time is set in consideration of the operation delay time of the transistor Q2 and the maximum delay time in the comparator 13.

  Here, a case is assumed where a short circuit failure occurs when the drive pattern is turned off, such as “at the time of a short circuit failure” shown in FIG. In the configuration of the present embodiment, when no failure has occurred, the output of the comparator 13 after a predetermined time after the drive pattern is turned off should be at the H level.

  Therefore, the determination unit 14 determines that no short-circuit failure has occurred when the comparator output at the predetermined time after the drive pattern is turned off is at the H level, that is, when “YES” is determined in the step S322, the step Returning to S321, the processing is repeated. Further, when the comparator output after the predetermined time is not at the H level, that is, when “NO” is determined in Step S322, the determination unit 14 determines that a short failure has occurred, and proceeds to Step S303 to output short detection.

“2” Flow of Open Detection Process When the open detection process shown in FIG. 13 is started, the determination unit 14 first monitors the comparator output after the drive signal is turned on in step S421. In subsequent step S422, the determination unit 14 determines whether or not the comparator output at the predetermined time after the drive signal is turned on is at the L level.

  Here, a case is assumed in which an open failure occurs when the drive pattern is turned on, such as “at the time of an open failure” shown in FIG. In this case, if no failure has occurred, the output of the comparator 13 after a predetermined time after the drive pattern is turned on should be at the L level.

  Therefore, the determination unit 14 determines that an open failure has not occurred when the comparator output at a predetermined time after the drive pattern is turned on is L level, that is, when “YES” is determined in the step S422, the step The process returns to S421 and is repeated. If the comparator output after the predetermined time is not at the L level, that is, if “NO” in step S422, the determination unit 14 determines that an open failure has occurred, and proceeds to step S403 to output an open detection.

  In the present embodiment described above, the failure detection circuit 1 performs switching when the output of the comparator 13 after a predetermined time from the time when the state of the drive signal changes does not change following the change of the drive signal. It is determined that the element has failed. Even with such a configuration, the failure can be detected quickly and accurately regardless of the operating state of the transistor Q2 while simplifying the circuit configuration, as in the first embodiment.

  In the case of the present embodiment, since the failure determination is performed after a predetermined time from the time when the state of the drive signal changes, the time required from the occurrence of the failure to the detection can be shortened. In addition, in the unlikely event that the transistor Q2 fails, the time during which a large current flows can be shortened, and the risk of damage to circuit components can be reduced.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIGS. 15 to 26.
In the fourth embodiment, an example of another electrical configuration of the failure detection circuit 1 is shown. In the failure detection circuit 1 of this embodiment, each detection process shown in the above embodiments can be performed, and a failure of the transistor Q2 can be detected as in the above embodiments.

  FIG. 15 shows the failure detection circuit 1 with a simplified configuration. In this case, the diode D4 and the resistor R1 are omitted. Therefore, the voltage amplitudes at points A and B are substantially the same. Even in such a configuration, the input to the failure determination circuit 12 is input by the level conversion circuit 11 as a signal having a voltage amplitude smaller than the voltage amplitude of the output node of the transistor Q2. Even with such a circuit configuration, the same effect as in the first embodiment can be obtained.

  However, in the case of the configuration shown in FIG. 15, since the temperature compensation diode D4 is omitted, the temperature characteristics of the diode D3 may affect the detection of the failure. For example, when the voltage at the point B changes with temperature, if the threshold voltage Vth is fixed, the threshold voltage Vth may fall out of an appropriate range.

Therefore, it is considered that the possibility of false detection can be reduced by making the threshold voltage Vth changeable according to the temperature characteristics of the diode D3.
FIG. 16A shows the failure detection circuit 1 provided with the threshold value changing circuit 20. In this case, the threshold voltage Vth input to the inverting input terminal of the comparator 13 is changed by the threshold change circuit 20. Specifically, in the threshold value changing circuit 20, a diode D6 and a resistor R2 are connected in series between the output of the transistor Tr5 that operates in synchronization with the current source 10 and the ground GND. The output of the transistor Tr5, that is, in the case of FIG. 16, the anode side of the diode D6 is connected to the inverting input terminal of the comparator 13.

  The diode D6 has a temperature characteristic common to the level conversion diode D3, and the forward voltage changes in a manner common to the diode D3 in accordance with a change in temperature. That is, the threshold voltage Vth automatically changes according to a change in temperature, and the change corresponds to the temperature characteristic of the diode D3. By providing such a threshold change circuit 20, the threshold voltage Vth can be automatically changed when the temperature changes, so that the failure can be detected with high accuracy.

  In the case of the circuit configuration shown in FIG. 16A, the threshold voltage Vth can be changed so as to compensate for the temperature characteristics of the diode D3, so that the detection accuracy can be further improved. FIG. 16B is a modification of the threshold value changing circuit 20 shown in FIG. 16A, and shows a configuration in which a dedicated current source 21 is provided instead of the transistor Tr5.

  Further, by providing the threshold value changing circuit 20, for example, immediately after starting the DC-DC converter, when the voltage amplitude of the transistor Q2 is smaller than the steady state, the threshold voltage Vth is lowered to prevent erroneous detection of a failure. Can do. In addition, by switching the threshold voltage Vth in a time-sharing manner, it becomes possible to separately set the threshold voltage Vth when detecting a ground fault and the threshold voltage Vth when detecting a power fault or detecting open, etc. Detection with high accuracy can be performed. These effects can also be obtained in the case of a failure detection circuit 1 shown in FIGS. 17 and 18 described later.

  FIG. 17 shows a failure detection circuit 1 in which the threshold change circuit 20 is configured by a D / A converter 22. In this case, the voltage output from the D / A converter 22 is input to the comparator 13 as the threshold voltage Vth. At this time, the D / A converter 22 may be configured to read a set value from a memory (not shown) and output the threshold voltage Vth at the time of startup, or may be configured to set the set value from an external microcomputer (not shown). There may be. Thus, the threshold voltage Vth can be changed by configuring the threshold changing circuit 20 with the D / A converter 22.

  FIG. 18 shows the failure detection circuit 1 in which the threshold value changing circuit 20 is configured by a D / A converter 22 and the threshold voltage Vth has temperature characteristics. In this case, the set value is set by the arithmetic circuit 23 in the D / A converter 22. The arithmetic circuit 23 calculates a set value to be set in the D / A converter 22 based on the temperature detected by the temperature detection unit 24. The arithmetic circuit 23 is configured to set the set value read from the memory 25 in the D / A converter 22 at the time of startup or the like, and to change the set value according to the calculation result when normal operation is started. Also good. The threshold voltage Vth can also be changed by such a threshold change circuit 20. As the temperature detection unit 24, a known temperature sensor or the like may be used.

  FIG. 19 shows a failure detection circuit 1 provided with a diode D7 connected to a constant voltage power supply VCC2 as a voltage limiting element instead of the clamping Zener diode D5 shown in FIG. Here, assuming that the forward voltage of the diodes D3, D4, and D7 is Vf and the collector-emitter saturation voltage of the transistors Tr2 and Tr4 is Vsat, “VCC2 + Vf <VCC−Vsat−Vf”, “VCC2 + Vf> Vth” Assume that the relationship is satisfied.

  Even with such a configuration, the voltage at the output terminal of the current source 10, that is, the voltage at the point B can be limited. Therefore, saturation of the transistors Tr2 and Tr4 of the current source 10 can be prevented, and a failure can be detected quickly. In this case, the voltage limiting element may be configured to use one or a forward voltage of a plurality of diodes D8, D9, and D10 as shown in FIG. Here, assuming that the forward voltage of the diodes D3, D4, D8, D9 and D10 is Vf and the collector-emitter saturation voltage of the transistors Tr2 and Tr4 is Vsat, “3 × Vf <VCC−Vsat−Vf”, “3 It is assumed that the relationship of “× Vf> Vth” is satisfied. The number of diodes to be used is not limited to the three shown in FIG. 20, but can be changed as appropriate based on the respective forward voltages.

  FIG. 21 shows a failure detection circuit 1 using a Schmitt trigger buffer 26 manufactured by a CMOS process as a logic circuit, instead of the comparator 13 shown in FIG. For example, when the accuracy is not required with respect to the threshold voltage Vth, the output voltage of the level conversion circuit 11 is set to the CMOS level while simplifying the circuit by using the Schmitt trigger buffer 26 whose threshold is fixed in advance. Can be converted. Therefore, the same effect as that of the first embodiment can be obtained by such a configuration. Further, since the Schmitt trigger buffer 26 has hysteresis, the failure detection circuit 1 can be kept resistant to noise.

  Although illustration is omitted, the same effect can be obtained by using a Schmitt trigger inverter instead of the Schmitt trigger buffer 26 or using a normal buffer or inverter having no hysteresis. When a Schmitt trigger inverter or an inverter is used, the logic level at the time of determination in the short detection process and open may be set as appropriate.

  FIG. 22 shows another configuration example of the constant current circuit 15. The constant current circuit 16 can also have the same configuration as those of other configuration examples. For example, as shown in FIG. 22A, the constant current circuit 15 can be configured by a current mirror circuit using field effect transistors Q10 and Q11 instead of the bipolar transistors Tr1 and Tr2 shown in FIG. Alternatively, as shown in FIG. 22B, the constant current source 17 can be omitted, and the constant current circuit 15 can be configured using a depletion type field effect transistor Q13. Further, as shown in FIG. 22C, the constant current circuit 15 can be configured using the constant current diode 27. These are examples of the constant current circuit 15, and other circuit configurations may be adopted as long as the constant current can be supplied to the level conversion diode D3.

  FIG. 23 shows another configuration example of the current source 10. FIG. 23A shows a configuration in which the constant current circuit 16 is omitted and a variable current source 28 is used instead of the constant current source 17 in the configuration shown in FIG. In this case, based on the switching signal Sa, the variable current source 28 can be switched between a state of outputting a current having a first current value and a state of outputting a current having a second current value. Even with the current source 10 having such a configuration, a “small current output state” in which a current having a first current value is output and a “large current output state” in which a current having a second current value larger than the first current value is output. Can be switched.

  The variable current source 28 may have any configuration as long as the output current can be switched in at least two stages based on the switching signal Sa. For example, as the variable current source 28, a configuration including six resistors R11 to R16, four transistors Tr11 to Tr14, and a switch 29 as shown in FIG.

  In this case, the interconnection point of the base of the transistor Tr14 and the resistor R16 is connected to the collector of the transistor Tr1 constituting the constant current circuit 15. The switch 29 is composed of a MOS transistor or the like, and on / off of the switch 29 is controlled based on the switching signal Sa. According to such a configuration, the output current of the variable current source 28 is determined by the resistance value between the emitter of the transistor Tr13 and the ground GND, and the resistance value is switched by turning on / off the switch 29. Therefore, according to the configuration shown in FIG. 23B, the output current can be switched in two stages based on the switching signal Sa.

  FIG. 24 is a configuration in which the constant current circuit 16 is omitted and four transistors Tr21 to Tr24 and a switch 30 are added to the configuration shown in FIG. The transistors Tr21 to Tr24 are connected to form a current mirror circuit together with the transistors Tr1 and Tr2 when the switch 30 is on. The switch 30 is composed of a MOS transistor or the like, and on / off of the switch 30 is controlled based on the switching signal Sa.

  In this case, the value of the output current of the constant current circuit 15 is the first current value when the switch 30 is off, and the second current value is larger than the first current value when the switch 30 is on. The current value of the constant current source 17, the sizes of the transistors Tr1, Tr2, and Tr21 to Tr24 are set. Even with such a configuration, the output current can be switched in two stages based on the switching signal Sa. In this case, four transistors Tr21 to Tr24 are added as transistors for configuring the current mirror circuit, but the number of transistors to be added may be changed as appropriate.

  FIG. 25 shows a configuration in which a latch circuit 31 is added. The latch circuit 31 holds the output of the comparator 13 and outputs the held signal as a switching signal Sa for switching the output state of the current source 10. According to such a configuration, the output state of the current source 10 can be switched without going through the determination unit 14 including a logic circuit or the like. Therefore, for example, when a short-circuit failure of the transistor Q2 is detected in the startup detection process, the current source 10 can be quickly switched to the “small current output state”. That is, according to such a configuration, the current source 10 can be immediately switched to the “small current output state” during a period when it is not necessary to output a large current, so that the current consumption by the current source 10 can be further reduced. it can.

  FIG. 26 shows an example of the switching circuit 2 including a switching element to be detected by the failure detection circuit 1. In FIG. 26, the switching element to be detected is surrounded by a broken line. In addition to the step-up / step-down DC-DC converter as shown in FIG. 1, the failure detection circuit 1 includes a transistor Q20 of the switching circuit 2 used in, for example, an ON / OFF driver shown in FIG. Or, for example, the lower-arm transistors Q22 and Q24 of the switching circuit 2 used in the full-bridge driver shown in FIG. 26B, or the switching circuit 2 used in the driver circuit of the three-phase motor shown in FIG. The present invention can be applied to detecting a failure of the lower arm transistors Q26, Q28, and Q30.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above and described in drawing, In the range which does not deviate from the summary, it can change, combine or expand arbitrarily.
In each embodiment, the configuration in which the magnitude of the current supplied to the output node is switched by using the current source 10 that can switch the output state is shown. However, the switching of the magnitude of the current supplied to the output node is as follows. It is also possible to do so. That is, as shown in FIG. 27, instead of the current source 10, a current source 32 that always outputs a current having a first current value is used. Then, control is performed such that the drive circuit 4 turns on the transistor Q1 in at least a part of the period in which the short detection process in the startup detection process is executed.

  Even in such a configuration, in the short detection process when the operation of the transistor Q2 is stopped, a current value larger than the first current value, that is, a current of the second current value can be supplied to the output node. Since the current source 32 only needs to be configured to output a constant current, the current source 32 can be configured with a smaller circuit area than the current source 10 configured to switch the current value. Therefore, by adopting such a configuration, it is possible to obtain the same effects as those of the above-described embodiments while suppressing the circuit area of the failure detection circuit 1 and thus the semiconductor device 100 to be small.

  In each embodiment, the configuration in which the failure determination circuit 12 is provided in the semiconductor device 100 is shown. However, an external microcomputer is used as the failure determination circuit 12, and the output of the level conversion circuit 11 or the comparator 13 is output to the external microcomputer. It is good also as composition to do. In this case, the level conversion circuit 11 may be handled as a signal conversion device as shown in FIG. 28, for example, alone or in combination with a logic circuit such as the comparator 13. In this case, the signal conversion device is provided with a level conversion circuit 11 that receives an input whose voltage fluctuates and converts the signal into a signal having a voltage amplitude smaller than the input voltage amplitude. For example, when a CMOS level output is desired, a logic circuit that outputs a signal with a small voltage amplitude converted by the level conversion circuit 11 may be provided. Further, this signal conversion device may be incorporated in a semiconductor device.

  DESCRIPTION OF SYMBOLS 1 ... Failure detection circuit, 10 ... Current source, 11 ... Level conversion circuit, 12 ... Failure determination circuit, D3 ... Diode, Q2, Q20, Q22, Q24, Q26, Q28, Q30 ... Transistor.

Claims (12)

A failure detection circuit (1) for detecting a failure of a switching element (Q2, Q20, Q22, Q24, Q26, Q28, Q30) used in the switching circuit,
A level conversion circuit (11) for converting the voltage amplitude of the output node whose voltage fluctuates when the switching element to be detected is switched into a signal having a voltage amplitude smaller than the voltage amplitude at the output node;
A failure determination circuit (12) for determining a failure of the switching element based on a signal having a small voltage amplitude converted by the level conversion circuit;
With
The level conversion circuit includes a current source (10) that outputs a predetermined current, and a level conversion diode (D3) that is connected between the output node and the current source with the current source side as an anode. Prepared,
The current source outputs a current having a first current value during a period in which the switching circuit is operating, and a second current greater than the first current value in a period during which the operation of the switching circuit is stopped. Fault detection circuit for switching element that outputs current of value.   The level conversion circuit includes a voltage limiting element (D5, D7, D8, D9, D10) that is provided between the current source and the failure determination circuit and limits a voltage of an output terminal of the current source. The failure detection circuit of the switching element according to 1. The level conversion circuit includes:
A temperature compensation diode (D4) connected between the current source and the failure determination circuit with the current source side as an anode and having a temperature characteristic common to the level conversion diode;
A resistance element (R1) for pulling down the cathode of the temperature compensating diode;
The failure detection circuit of the switching element of Claim 1 or 2 provided with these.   The failure determination circuit compares an output voltage of the output terminal of the current source with a threshold voltage, and converts the comparison result into a signal having a voltage amplitude smaller than the voltage amplitude of the output node (13, 26). The failure detection circuit for a switching element according to any one of claims 1 to 3, further comprising:   5. The switching element failure detection circuit according to claim 4, further comprising a threshold value changing circuit (20) for changing the threshold voltage.   The threshold value changing circuit includes a threshold value changing diode (D6) having a temperature characteristic common to the level converting diode, and automatically changes the threshold voltage according to temperature. 5. A switching element failure detection circuit according to 5. A temperature detector (24) for detecting the temperature;
6. The switching element failure detection circuit according to claim 5, wherein the threshold value changing circuit (20) changes a threshold voltage based on a temperature detected by the temperature detecting unit.   The failure determination circuit receives a signal having a voltage amplitude smaller than the voltage amplitude at the output node and a drive signal for driving the switching element, and the state of the signal having a voltage amplitude smaller than the voltage amplitude at the output node is the drive signal. The failure of the switching element according to claim 1, wherein the failure of the switching element is determined based on whether or not the state of the switching element changes following the change of the state of the switching element. Detection circuit.   The failure determination circuit determines that the switching element has failed when a state of a signal having a voltage amplitude smaller than a voltage amplitude at the output node is fixed for one period or more of the drive signal. Item 9. A switching element failure detection circuit according to Item 8.   The failure determination circuit performs switching when the state of a signal having a voltage amplitude smaller than the voltage amplitude at the output node at the time when the drive signal changes is different from a corresponding state before the state of the drive signal changes. 9. The switching element failure detection circuit according to claim 8, wherein it is determined that the element has failed.   When the state of the signal having a voltage amplitude smaller than the voltage amplitude at the output node after a predetermined time from the time when the state of the drive signal changes does not change following the change of the drive signal, the failure determination circuit 9. The switching element failure detection circuit according to claim 8, wherein it is determined that the switching element has failed.   A semiconductor device comprising the switching element failure detection circuit according to claim 1.

Images