JP2016163451A - Synchronous rectifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten dead time while eliminating necessity of an external diode.SOLUTION: When a reflux current is allowed to flow through a parasitic diode Dam of a main transistor Mam in a MOS transistor Ma when a command signal InH is an L level, drain potential of the MOS transistor Ma is reduced lower than source potential. In the case, a current is allowed to flow from a control power supply Pca through a current limiting resistor Rsa and a parasitic diode Das of a sense transistor Mas and a reflux detection voltage VNa is changed from a state higher than a reference voltage Vpa to a lower state. When the reflux detection voltage VNa is lower than the reference voltage Vpa in a period that the command signal InH becomes an H level, a drive control circuit Fa controls a gate voltage Vga of the MOS transistor Ma to an ON driving level and performs synchronous rectification.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a synchronous rectifier circuit using a MOS transistor.

  The step-up converter includes a reactor connected in series between the positive and negative terminals of the input power supply and a first transistor for switching, a capacitor connected between the output terminals, and a second transistor for synchronous rectification that guides the current flowing through the reactor to the capacitor. Etc. The control circuit applies a first drive signal having a duty ratio corresponding to the deviation between the target voltage and the output voltage to the first transistor, and secures a dead time and then has a second relationship complementary to the first drive signal. A drive signal is applied to the second transistor.

  Since the capacitor is short-circuited when the first transistor and the second transistor are simultaneously turned on, the dead time is generally set with a margin. For this reason, in the dead time period after the first transistor is driven off, the return current flows through the parasitic diode while the second transistor is driven off, and thus the conduction loss of the second transistor cannot be sufficiently reduced. .

  On the other hand, the synchronous rectification MO transistor control circuit described in Patent Document 1 includes a constant current circuit, a diode connected between the output terminal of the constant current circuit and the drain of the transistor, and an anode of the diode. And a circuit for generating a gate voltage of the transistor using a resistor connected between the transistor and the source of the transistor and a voltage across the resistor. This control circuit monitors the voltage between the drain and source of the transistor and detects whether or not the paired counterpart transistor is off to generate a gate voltage. Thereby, dead time can be shortened.

JP 2004-208407 A

  Since the above-described conventional configuration requires an external diode, there are problems such as an increase in the number of parts, an increase in cost, and an increase in circuit scale. In addition, the noise increases due to the parasitic capacitance of the external diode, which causes malfunction.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a synchronous rectifier circuit that eliminates the need for an external diode and can reduce dead time while reducing noise.

  The synchronous rectifier circuit described in claim 1 uses a parasitic diode of a sense transistor formed in a MOS transistor in place of the external diode described above. The MOS transistor has a main transistor and a sense transistor whose drains and gates are commonly connected, and is connected so that a reflux current flows between the drain and source of the main transistor.

  The synchronous rectifier circuit includes a control power supply, a current limiting resistor, a reference voltage generation circuit, and a drive control circuit in addition to the MOS transistor. The control power supply supplies a control voltage having the same polarity as the polarity of the drain voltage when the main transistor is turned off and no current flows with reference to the source potential of the main transistor. If the MOS transistor is an N channel type, it is positive, and if it is a P channel type, it is negative. The current limiting resistor is provided between the control power supply and the source of the sense transistor.

  The reference voltage generation circuit has a return detection voltage in the return state in which the parasitic diode of the main transistor is energized, which is lower than the control voltage (as an absolute value) when the voltage at the sense transistor side of the current limiting resistor is the return detection voltage. Produces a higher reference voltage (as an absolute value).

  The drive control circuit recirculates when the on-drive command is given and during the period when the off-drive command is given and before the on-drive command is given after the return detection voltage becomes higher than the reference voltage. When the detection voltage is lower than the reference voltage, an ON drive voltage is output to the MOS transistor.

  According to this configuration, when the reflux current flows through the parasitic diode of the main transistor when the off drive command is given, the drain potential of the MOS transistor is lowered and becomes lower than the source potential. At this time, current flows from the control power source through the current limiting resistor and the parasitic diode of the sense transistor, and the return detection voltage changes from a state higher than the reference voltage to a lower state. The drive control circuit outputs an ON drive voltage to the MOS transistor when the return detection voltage is lower than the reference voltage within a period until the ON drive command is given.

  As a result, even during the dead time period, when the return current starts to flow due to the switching element of another synchronous rectifier circuit used in a pair with the synchronous rectifier circuit, the main transistor is turned on and synchronous rectification is started. To do. Thereby, the reflux period through the parasitic diode can be shortened.

  Further, since the parasitic diode of the sense transistor is used instead of an external diode as means for generating the return detection voltage, the number of parts, cost, circuit scale, etc. can be reduced as compared with the conventional configuration. Since the sense transistor has a smaller cell size even when the withstand voltage is higher than that of an external diode, parasitic capacitance is reduced, and noise current flowing through the parasitic capacitance is reduced with respect to noise. As a result, noise superimposed on the reflux detection voltage can be reduced, and malfunction due to noise can be prevented.

  In addition, a delay circuit is provided that delays the timing at which the drive control circuit starts outputting the on-drive voltage to the MOS transistor during the period when the off-drive command is given. As a result, it is possible to prevent the drive control circuit from operating and outputting the on-drive voltage when noise is added to the return detection voltage while the MOS transistor is off.

  According to the second aspect, the sense transistor according to the first aspect is replaced with a reflux detection diode. That is, in the configuration of the first aspect, the parasitic diode of the sense transistor is used as means for obtaining the return detection voltage, and the sense transistor body is not used. Therefore, if only a diode in place of the parasitic diode is formed in the MOS transistor, the same effect as in the first aspect can be obtained without using an external diode.

  According to a third aspect of the present invention, the drive control circuit includes a return detection voltage between the time when the return detection voltage becomes higher than the reference voltage during the period in which the off drive command is given and the time when the on drive command is given. When the voltage becomes lower than the reference voltage, the on-drive voltage is continuously output to the MOS transistor until the on-drive command is given thereafter.

  When the switching elements used as a pair are turned off, ringing is likely to occur in the drain-source voltage of the main transistor which starts to flow a reflux current. When ringing occurs, the reflux detection voltage also becomes oscillatory. According to this means, once the return detection voltage becomes lower than the reference voltage, the on drive voltage is continuously output until the on drive command is given regardless of the subsequent return detection voltage. Therefore, the main transistor can be continuously turned on, and the reflux period through the parasitic diode can be further shortened.

  According to the means described in claim 4, since the means according to claim 2 also includes the delay circuit similar to that of claim 1, when noise is added to the return detection voltage during the period in which the MOS transistor is off, Thus, it is possible to prevent the drive control circuit from operating and outputting the ON drive voltage.

  According to the means described in claim 5, the power supply side switch is provided between the control power supply and the source of the sense transistor. The switch control circuit controls the power supply side switch to an on state during a period in which the drive control circuit outputs an off drive voltage to the MOS transistor in response to an off drive command. Further, the switch control circuit is a period in which a current flows through the MOS transistor by the ON drive command, on condition that the drive control circuit does not output the ON drive voltage to the MOS transistor before the ON drive command is given, Control the power switch to the off state.

  When the above-described synchronous rectification circuit performs synchronous rectification, when the ON drive voltage is applied to the MOS transistor, the direction of the current flowing through the main transistor matches the direction of the current flowing through the sense transistor (if it is an N-channel type) Source to drain). On the other hand, when the synchronous rectification circuit does not perform synchronous rectification, the direction of the current flowing through the main transistor when the ON drive voltage is applied to the MOS transistor (drain to source in the case of the N channel type) and the sense transistor This is opposite to the direction of the flowing current (source to drain if N-channel type). If the current direction differs between the main transistor and the sense transistor formed in one MOS transistor, current concentration may occur in the sense cell.

  According to this means, when synchronous rectification is not performed (when the drive control circuit does not output the on-drive voltage before the on-drive command is given), the current flows through the main transistor of the MOS transistor, The reverse current flowing from the control power supply to the source of the sense transistor is cut off. Therefore, current concentration on the sense cell can be prevented.

  According to the sixth aspect of the present invention, the source-side switch whose ON state is exclusively controlled by the switch control circuit by the switch control circuit is provided between the source of the sense transistor and the source of the main transistor. With this configuration, when the power supply side switch is turned off and the current flowing from the control power supply to the source of the sense transistor is cut off, the source is connected to the source of the main transistor via the source side switch. Therefore, the source potentials of the main and sense transistors are equal, and leakage current can be prevented from flowing between them.

  According to the seventh aspect of the present invention, overcurrent detection is performed based on a current detection resistor connected to any one terminal side of the source side switch and a current flowing through the current detection resistor when the source side switch is turned on. And an overcurrent detection circuit. That is, by using the source side switch, in addition to the action of shortening the return period by the drive control circuit, the overcurrent detection action by the overcurrent detection circuit, which is the original purpose of providing the sense transistor, can be executed. .

  According to the eighth aspect, the same effect as that of the fifth aspect can be obtained with the configuration in which the sense transistor according to the first aspect is replaced with a reflux detection diode.

  According to a ninth aspect of the present invention, the switch control circuit includes a delay circuit that delays the timing for controlling the power supply side switch to the ON state. That is, when the MOS transistor is turned off, the drain-source voltage of the main transistor rises, but at this time, the drain-source voltage is likely to ring. When ringing occurs, the reflux detection voltage also becomes oscillating, so that the voltage signal output from the drive control circuit also becomes oscillating. According to this means, the power supply side switch can be turned on while avoiding the period in which the ringing occurs due to the delay time provided by the delay circuit.

According to the tenth aspect, the parasitic capacitance Csense of the sense transistor is set as follows. The input capacity of the drive control circuit is Cin, the voltage of the control power supply is Vcc, the reference voltage is Vp, and the drain voltage of the MOS transistor is Vout. When the drain voltage Vout varies, the input voltage variation ΔVN of the drive control circuit is given by the following equation.
ΔVN = Csense / Cin · Vout
In order to suppress malfunction of the drive control circuit during this voltage fluctuation, the following conditions are required.
ΔVN <Vcc−Vp
Therefore, the parasitic capacitance Csense of the sense transistor is
Csense <(Vcc-Vp) / Vout · Cin
As a result, it is possible to set a capacitance value sufficient to suppress the malfunction of the drive control circuit. As a result, a noise filter and a mask circuit are not required, and a highly responsive drive control circuit can be designed while suppressing noise.

  According to the eleventh aspect of the present invention, in the configuration including the return detection diode as in the second aspect, the parasitic capacitance Cdiode of the return detection diode is equal to the parasitic capacitance Csense in the means according to the tenth aspect. Is set, the same effect as in the tenth aspect can be obtained.

1 is a configuration diagram of a synchronous rectifier circuit showing a first embodiment. Booster configuration diagram Waveform diagram The structure of the synchronous rectifier circuit which shows 2nd Embodiment and was provided with respect to MOS transistor Ma Configuration diagram of one-shot circuit Waveform diagram The structure of the synchronous rectifier circuit which shows 3rd Embodiment and was provided with respect to MOS transistor Mb Configuration diagram of switch and switch control circuit Waveform diagram The block diagram of the synchronous rectifier circuit which shows 4th Embodiment The block diagram of the synchronous rectifier circuit (high side) which shows 5th Embodiment Waveform diagram Configuration diagram of switching control circuit (low side) showing sixth embodiment Waveform diagram The block diagram of the synchronous rectifier circuit (low side) which shows 7th Embodiment The block diagram of the synchronous rectifier circuit which shows 8th Embodiment

In each embodiment, the same parts are denoted by the same reference numerals, and description thereof is omitted.
(First embodiment)
A first embodiment will be described with reference to FIGS. 1 to 3. A booster circuit 1 shown in FIG. 2 is a chopper circuit that boosts a voltage Vin of an input power source 2 such as a battery connected between input terminals and outputs a boosted voltage Vout to a load 3 connected between output terminals. . A capacitor C1 is connected between the input terminals, and a capacitor C2 is connected between the output terminals. Although not shown, a voltage detection circuit that divides and detects the boosted voltage Vout is provided.

  A reactor L and an N-channel MOS transistor Ma are connected in series between the input node N1 and the output node N2 with the intermediate node N3 interposed therebetween. An N channel type MOS transistor Mb is connected between the intermediate node N3 and the ground. The MOS transistor Ma includes a main transistor Mam and a sense transistor Mas whose drains and gates are commonly connected. Similarly, the MOS transistor Mb includes a main transistor Mbm and a sense transistor Mbs. Parasitic diodes Dam and Dbm and parasitic diodes Das and Dbs are formed in parallel in the main transistors Mam and Mbm and the sense transistors Mas and Mbs, respectively.

  The gate voltage generation circuit 4 generates gate voltages Vga and Vgb based on the command signals InH and InL input from the control IC 5 and the source potentials of the sense transistors Mas and Mbs (circulation detection voltages VNa and VNb described later). FIG. 1 specifically shows the circuit configuration of the gate voltage generation circuit 4. Since the circuits that generate the gate voltages Vga and Vgb have the same configuration, the circuit configuration that mainly generates the gate voltage Vga will be described.

  The control power supply Pca generates a positive control voltage Vcca having the same polarity as the drain voltage in a state where the main transistor Mam is driven off and no current flows with reference to the source potential of the main transistor Mam. A current limiting resistor Rsa for limiting the current flowing through the parasitic diode Das is connected between the positive terminal of the control power source Pca and the source of the sense transistor Mas. The voltage VNa at the connection node Na between the current limiting resistor Rsa and the source of the sense transistor Mas corresponds to the reflux detection voltage referred to in the present invention.

  The reference voltage generation circuit Ppa is based on the source potential of the main transistor Mam and is lower than the control voltage Vcca and higher than the return detection voltage VNa (approximately 0 V) in the return state in which the parasitic diode Dam of the main transistor Mam is energized. Vpa is generated.

  The drive control circuit Fa includes a comparator CPa, an OR circuit ORa, a driver circuit DRa, and a gate resistor Rga. The comparator CPa outputs an L level signal S1a when the return detection voltage VNa is higher than the reference voltage Vpa, and outputs an H level signal S1a when the return detection voltage VNa is lower than the reference voltage Vpa.

  However, the comparison operation is invalidated while the command signal InH is at the H level, and the L level signal S1a is output regardless of the magnitude relationship between the reflux detection voltage VNa and the reference voltage Vpa. This invalidation state is canceled when the return detection voltage VNa becomes higher than the reference voltage Vpa while the command signal InH is at the L level. The command signal InH and the signal S1a are input to the OR circuit ORa, and the output signal becomes the gate voltage Vga through the driver circuit DRa and the gate resistor Rga.

  Similarly, the circuit that generates the gate voltage Vgb includes a control power supply Pcb that generates the control voltage Vccb, a current limiting resistor Rsb, a reference voltage generation circuit Ppb that generates the reference voltage Vpb, and a drive control circuit Fb. The voltage VNb at the connection node Nb between the current limiting resistor Rsb and the source of the sense transistor Mbs corresponds to the reflux detection voltage referred to in the present invention. The drive control circuit Fb includes a comparator CPb, an OR circuit ORb, a driver circuit DRb, and a gate resistor Rgb. The drive control circuit Fb receives the command signal InH, the reflux detection voltage VNb, and the reference voltage Vpb, and outputs the gate voltage Vgb.

  Next, the operation of this embodiment will be described with reference to FIG. The control IC 5 controls the duty ratio of the command signal InL by performing proportional / integral control on the deviation between the target voltage and the boosted voltage Vout detected by the voltage detection circuit. Since the control IC 5 performs synchronous rectification during the boosting operation, the control IC 5 generates a command signal InH having a dead time Td with respect to the command signal InL and having a complementary relationship. In the command signals InL and InH, the H level corresponds to an on drive command, and the L level corresponds to an off drive command. As described above, since the capacitor C2 is short-circuited when the main transistors Mam and Mbm are turned on simultaneously, the dead time Td is set with a margin.

  In the timing chart shown in FIG. 3, the command signal InL, the command signal InH, the gate voltages Vgb and Vga, the drain-source voltage VDS (Mbm) of the main transistor Mbm, and the drain-source voltage VDS ( Mam), the return detection voltage VNb, the return detection voltage VNa, the output signal S1b of the comparator CPb, the output signal S1a of the comparator CPa, the output signal of the OR circuit ORb, the output signal of the OR circuit ORa, and the current IL flowing through the reactor L Yes.

  Since the command signals InH and InL are at the L level immediately before time t1, the gate voltages Vga and Vgb are at the off drive level, and the main transistors Mam and Mbm are off. The current IL flows to the capacitor C2 through the parasitic diode Dam. At this time, the parasitic diode Das is energized, and the return detection voltage VNa is almost 0V. However, since the comparison operation of the comparator CPa is invalidated, the output signal S1a of the comparator CPa remains at the L level. On the other hand, since the reverse voltage is applied to the parasitic diode Dbs, the return detection voltage VNb is equal to Vccb, and the comparator CPb outputs the L level output signal S1b.

  When the command signal InL becomes H level at time t1, the output signal of the OR circuit ORb becomes H level, and the gate voltage Vgb becomes the ON drive level through the mirror period. Accordingly, the drain-source voltage VDS (Mbm) of the main transistor Mbm decreases, and the drain-source voltage VDS (Mam) of the main transistor Mam increases. As a result, a current flows from the input power source 2 through the reactor L and the main transistor Mbm, and the current IL gradually increases. In the following description, the MOS transistor Mb through which such an active current flows may be referred to as a switching-side element.

  At this time, the parasitic diode Das is de-energized, and the return detection voltage VNa becomes equal to Vcca. When the reflux detection voltage VNa becomes higher than the reference voltage Vpa, the invalidated state of the comparator CPa is released. On the other hand, the parasitic diode Dbs is energized, and the return detection voltage VNb becomes almost 0V. However, since the command signal InL is at the H level, the comparison operation of the comparator CPb is invalidated, and the output signal S1b remains at the L level.

  When the command signal InL becomes L level at time t2, the output signal of the OR circuit ORb becomes L level, and the gate voltage Vgb becomes the OFF drive level through the mirror period. Along with this, the drain-source voltage VDS (Mbm) of the main transistor Mbm increases and the drain-source voltage VDS (Mam) of the main transistor Mam decreases. As a result, the current IL flowing through the reactor L flows through the parasitic diode Dam to the capacitor C2, and the current IL gradually decreases.

  At this time, the parasitic diode Dbs is de-energized, and the return detection voltage VNb is equal to Vccb. The output signal of the OR circuit ORb remains at the L level. On the other hand, the parasitic diode Das is energized, and the return detection voltage VNa becomes approximately 0 V in the vicinity of time t3. Since the recirculation detection voltage VNa becomes lower than the reference voltage Vpa, the output signal S1a of the comparator CPa that has already been canceled is changed to the H level.

  That is, even when the command signal InH is at L level (off drive command), the output signal of the OR circuit ORa becomes H level based on the fact that the parasitic diode Dam starts to energize. As a result, the gate voltage Vga becomes the on drive level, the main transistor Mam is turned on, and synchronous rectification is started without waiting for the end of the dead time Td (time t4). The MOS transistor Ma that performs such synchronous rectification may be referred to as an element on the synchronous rectification side in the following description.

  When the command signal InH becomes H level at time t4, the comparison operation of the comparator CPa is invalidated, and the output signal S1a of the comparator CPa returns to L level. At this time, the output signal of the OR circuit ORa remains at the H level and the synchronous rectification continues.

  Thereafter, when the command signal InH becomes L level at time t5, the output signal of the OR circuit ORa becomes L level, and the gate voltage Vga decreases to the off drive level. As a result, the synchronous rectification is completed, and the current IL flows to the capacitor C2 through the parasitic diode Dam instead of the main transistor Mam. At this time, the drain-source voltages VDS (Mam) and VDS (Mbm) of the main transistors Mam and Mbm change by the forward voltage Vf of the parasitic diode Dam. The operation after time t6 is the same as the operation after time t1 described above.

  As described above, the booster circuit 1 of the present embodiment includes the MOS transistor Mb (switching side element) for storing energy in the reactor L and the MOS transistor Ma (synchronous rectification side side) for transferring the stored energy to the capacitor C2. Element). When the return current starts to flow through the parasitic diode Dam due to the MOS transistor Mb being turned off, the main transistor Ma is turned on to start synchronous rectification even during the dead time period. As a result, the reflux period through the parasitic diode Dam can be shortened, and loss can be reduced.

  In addition, as the means for generating the reflux detection voltages VNa and VNb, the parasitic diodes Das and Dbs of the sense transistors Mas and Mbs are used instead of external diodes, so the number of parts, cost, circuit scale, etc. are reduced compared to the conventional configuration. it can. A general external diode tends to increase the current capacity and parasitic capacity as the withstand voltage increases. On the other hand, the sense transistor has a small cell size even if the withstand voltage is high, so that the parasitic capacitance is small, and the noise current flowing through the parasitic capacitance is small against noise. As a result, noise superimposed on the reflux detection voltages VNa and VNb is reduced, and malfunctions of the comparators CPa and Cpb can be reduced.

  Normally, the current of the reactor L is positive (in the direction of the arrow shown in FIG. 1). However, when the load is light, a negative regenerative current flows from the output side to the input power source 2 through the main transistor Mam and the reactor L. At this time, when the main transistor Mam is turned off, a reflux current flows through the parasitic diode Dbm. At this time, the main transistor Mbm is turned on during the dead time period to perform synchronous rectification. Therefore, in the present embodiment, the same rectifier circuit as that on the MOS transistor Ma side is provided on the MOS transistor Mb side.

(Second Embodiment)
A second embodiment will be described with reference to FIGS. This embodiment is also a booster circuit having the main circuit configuration shown in FIG. FIG. 4 shows a synchronous rectification circuit of the MOS transistor Ma. The sense transistor Mas and its parasitic diode Das are not shown.

  A one-shot circuit Ya is provided between the comparator CPa and the OR circuit ORa. When the output signal S1a of the comparator CPa changes from L level to H level, the one shot circuit Ya outputs a one shot signal S2a having an H level width of a predetermined time Ty. As shown in FIG. 5, the D flip-flop (DFF) 6 sets the signal S2a to the H level at the rising edge of the signal S1a.

  When the signal S2a becomes H level, the adder 7, the selector 8 and the register 9 perform a count operation in synchronization with the clock. If the determiner 10 determines that the count value held in the register 9 is equal to or greater than the value corresponding to the predetermined time Ty, the determiner 10 outputs an H level reset signal and returns the signal S2a to the L level. The synchronous rectifier circuit of the MOS transistor Mb also includes a similar one-shot circuit Yb and outputs a one-shot signal S2b.

  As shown in FIG. 6, when the command signal InL becomes L level (time t2), the drain-source voltage VDS (Mbm) of the main transistor Mbm rises, and the drain-source voltage VDS (Mam) of the main transistor Mam. Decreases. At this time, ringing is likely to occur in the voltages VDS (Mbm) and VDS (Mam) (time t2 to t3). When ringing occurs, the return detection voltage VNa also becomes oscillating, so that the output signal S1a of the comparator CPa and thus the gate voltage Vga also oscillates.

  The one-shot circuit Ya detects that the return detection voltage VNa is the reference voltage Vpa when the return detection voltage VNa is higher than the reference voltage Vpa and the invalidation state of the comparator CPa is released while the command signal InH is at the L level. If it becomes lower than that, the H level signal S2a is output for a predetermined time Ty regardless of the level of the subsequent signal S1a. The predetermined time Ty may be set equal to a time longer than the time until the command signal InH becomes H level, for example, the dead time Td.

  According to the present embodiment, even if the command signal InL becomes L level and ringing occurs in the voltages VDS (Mbm) and VDS (Mam), the main transistor Mam is on until the command signal InH becomes H level. Synchronous rectification continues. Therefore, regardless of the occurrence of ringing, the return period through the parasitic diode Dam can be shortened, and loss can be reduced.

(Third embodiment)
A third embodiment will be described with reference to FIGS. This embodiment is also a booster circuit having the main circuit configuration shown in FIG. FIG. 7 shows a synchronous rectifier circuit of the MOS transistor Mb. This synchronous rectifier circuit is a switch composed of transistors 11a (power supply side switches) and 11b (source side switches) between a current limiting resistor Rsb and a sense source (the source of the sense transistor Mbs, the anode of the parasitic diode Dbs). 11 is provided.

  The switch 11 is turned on when an L level control signal S3 is input from the switch control circuit 12, and connects the current limiting resistor Rsb and the sense source. The switch 11 is turned off when an H level control signal S3 is input from the switch control circuit 12, disconnects the current limiting resistor Rsb and the sense source, and connects the sense source to the ground. The synchronous rectifier circuit of the MOS transistor Ma is similarly configured.

  The reason for providing the switch 11 is as follows. In the first and second embodiments described above, when the command signal InL becomes H level, a current flows from the drain to the source in the main transistor Mbm, and a current flows from the source to the drain in the sense transistor Mbs. That is, in the MOS transistor Mb on the switching side, there are periods in which the directions of current flow differ between the main transistor Mbm and the sense transistor Mbs.

  Specifically, this is a period from when the gate voltage Vgb exceeds the threshold voltage Vth of the element to below the threshold voltage Vth. During this period, current may concentrate on the sense transistor Mbs. Such a period does not exist in the MOS transistor Ma on the synchronous rectification side.

  Therefore, in the present embodiment, the switch 11 is added to the synchronous rectifier circuit of the MOS transistor Mb, and the control signal S3 of H level is output from the switch control circuit 12 while the current is flowing through the MOS transistor Mb, so that the transistor 11a is turned on. Turns off and disconnects between the current limiting resistor Rsb and the sense source. However, as described above, when the load is light, the main transistor Mbm may perform synchronous rectification. Therefore, the switch control circuit 12 generates the control signal S3 at the H level on the condition that VNb> Vpb (that is, synchronous rectification is not performed) during the dead time period immediately before the command signal InL rises to the H level. Output.

  The switch control circuit 12 for the MOS transistor Mb has the configuration shown in FIG. The delay command signal InLd is a signal obtained by delaying the command signal InL by a predetermined delay time. The reason why the delay command signal InLd is used is to detect the state of the signal S1b during the dead time period immediately before the command signal InL rises to the H level as described above. Therefore, the delay time needs to be less than the dead time Td.

  The reflux detection voltage VNb and the command signal InL are input to the set terminal S1 of RSFF1 via the AND circuit 13. The delayed command signal InLd and the inverted signal of the command signal InL are input via the AND circuit 14 to the reset terminal R1 of RSFF1. The delay command signal InLd and the signal from the output terminal Q1 of RSFF1 are input to the set terminal S2 of RSFF2 via the AND circuit 15.

  In order to determine whether or not the gate voltage Vgb is higher than the threshold voltage Vth, a comparator 19 that compares the voltage obtained by dividing the gate voltage Vgb with the resistors 17 and 18 with the reference voltage Vr is provided. The reference voltage Vr is set substantially equal to a voltage obtained by dividing the threshold voltage Vth of the element by the resistors 17 and 18. The comparator 19 outputs an H level signal during a period when the divided voltage of the gate voltage Vgb is higher than the reference voltage Vr. The output signal of the comparator 19 and the command signal InL are input to the reset terminal R2 of the RSFF 2 via the NOR circuit 16. The control signal S3 is output from the output signal Q2 of RSFF2.

  The operation waveforms shown in FIG. 9 are waveforms when the MOS transistor Ma shown in FIG. 2 is an element on the synchronous rectification side and the MOS transistor Mb is an element on the switching side. The delay command signal InHd is a signal obtained by delaying the command signal InH by a predetermined delay time. The RSFF 1 detects the state of the return detection voltage VNb (Vccb: switching-side element / 0: synchronous rectification-side element) immediately before the delay command signal InLd becomes H level. The RSFF 1 holds an H level signal when it is determined as an element on the switching side, and holds an L level signal when determined as an element on the synchronous rectification side. When the command signal InL becomes L level, RSFF1 is reset.

  The RSFF 2 determines whether or not the divided voltage of the gate voltage Vgb exceeds the reference voltage Vr. RSFF2 holds an H level signal if the divided voltage of the gate voltage Vgb is equal to or higher than the reference voltage Vr and RSFF1 holds the H level. RSFF2 is reset when the divided voltage of the gate voltage Vgb falls below the reference voltage Vr. According to the above operation, the current limiting resistor Rsb and the sense are sensed during a period in which the drain current flows through the main transistor Mbm, that is, a period from when the gate voltage Vgb exceeds the threshold voltage Vth until it falls below the threshold voltage Vth. Release between the source.

  According to the present embodiment, when the MOS transistor Mb is an element on the switching side, the current limiting resistor Rsb is turned off by turning off the transistor 11a during a period in which the command signal InL is at the H level and a current flows through the MOS transistor Mb. Current flowing into the sense source from is interrupted. Thereby, it is possible to prevent current from being concentrated on the parasitic diode Dbs of the sense transistor Mbs.

Since the transistor 11b is turned on at the same time as the transistor 11a is turned off,
The source of the sense transistor Mbs is connected to the source of the main transistor Mbm. Therefore, the source potentials of both are equal, and leakage current can be prevented from flowing between them.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. The MOS transistors Ma1 and Mb1 of the present embodiment have a configuration in which the sense transistors Mas and Mbs are deleted from the MOS transistors Ma and Mb, and diodes Da and Db (reflux detection diodes) are provided instead. For example, in the first embodiment, the parasitic diodes Das and Dbs are used as means for obtaining the return detection voltage, and the sense transistors Mas and Mbs are not used. Therefore, if only the diodes Da and Db instead of the parasitic diodes Das and Dbs are formed inside the MOS transistors Ma1 and Mb1, the same operational effects as those of the first embodiment can be obtained without using external diodes. It will be.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIGS. 11 and 12. FIG. 11 shows only the configuration of the high side, but the drive control circuit Fa1 of this embodiment is a delay circuit (integration circuit) including a resistor Ra1 and a capacitor Ca1 between the output terminal of the comparator CPa and the input terminal of the OR gate ORa. ) 21a. The output signal of this delay circuit 21a is S1ad.

  Next, the operation of this embodiment will be described. FIG. 12 is a diagram corresponding to FIG. 6. In the second embodiment, the one-shot circuit Ya is provided in response to the return detection voltage VNa becoming oscillating as ringing occurs. In the present embodiment, since the delay circuit 21a is arranged in place of the one-shot circuit Ya, the change of the output signal of the comparator CPa is delayed, and the signal is generated after a period in which ringing occurs at the falling edge of the command signal InL. S1ad is set up. Thereby, the effect similar to 2nd Embodiment is acquired.

(Sixth embodiment)
A sixth embodiment will be described with reference to FIGS. 13 and 14. Although FIG. 13 shows only the low-side configuration, the switching control circuit 22 of this embodiment is a delay circuit (integration circuit) including a resistor Rb2 and a capacitor Cb2 between the output terminal of the comparator 19 and the input terminal of the NOR gate 16. 23b.

  Next, the operation of this embodiment will be described. Similar to the fifth embodiment, when the MOS transistor Mb is turned off, if the drain-source voltage VDS (Mbm) of the main transistor Mbm rises and ringing occurs, the return detection voltage VNb also becomes oscillating. On the other hand, in this embodiment, as shown in FIG. 14, the delay circuit 23b delays the output signal change of the comparator 19 to delay the timing for resetting the RSFF2. As a result, the signal S3 rises after the ringing occurrence period elapses to turn on the transistor 11a and turn off the transistor 11b. Therefore, the source of the sense transistor Mbs can be connected to the current limiting resistor Rsb while avoiding the ringing generation period.

(Seventh embodiment)
A seventh embodiment will be described with reference to FIG. FIG. 15 shows only the low-side configuration, but in this embodiment, overcurrent detection using the sense transistor Mbs is performed using the switch 11 of the third embodiment. A series circuit of a resistor Rsb and a current detection resistor Rs2b is connected between the transistors 11a and 11b. The resistor Rsb that has been connected to the source side of the transistor 11a in the third embodiment is moved to the drain side. The common connection point of the resistor Rsb and the current detection resistor Rs2b is connected to the input terminal of the overcurrent detection circuit 24.

  With this configuration, the overcurrent detection circuit 24 can perform overcurrent detection based on the current flowing through the current detection resistor Rs2b from the source of the sense transistor Mbs when the source-side switch 11b is turned on. .

(Eighth embodiment)
The eighth embodiment will be described with reference to FIG. In the present embodiment, it will be examined how the parasitic capacitance Csense of the sense transistor Mas should be set. Assuming that the input capacitance of the comparator CPa is Cin, when the drain voltage Vout of the MOS transistor Ma varies, the input voltage variation ΔVN of the comparator CPa is given by the following equation.
ΔVN = Csense / Cin · Vout (1)
In order to suppress the malfunction of the comparator CPa during this voltage fluctuation, the following conditions are required.
ΔVN <Vcc−Vp (2)
Therefore, the parasitic capacitance Csense is
Csense <(Vcc−Vp) / Vout · Cin (3)
Then, it is possible to set a capacitance value sufficient to suppress the malfunction of the comparator CPa. As a result, a noise filter and a mask circuit are not required, and a highly responsive drive control circuit Fa can be designed while suppressing noise.
Further, as in the fourth embodiment, for a configuration including only the diodes Da and Db, the value of the parasitic capacitance Cdiode of the diodes Da and Db may be set under the condition of the expression (3).

(Other embodiments)
As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.
The same configuration as that of the third embodiment can be applied to the second embodiment.
The resistor Rsb of the third embodiment may be connected to the drain side of the transistor 11a as in the seventh embodiment.
By making the size of the sense cell comprising the sense transistor and its parasitic diode small, the parasitic capacitance is reduced, and malfunction due to noise can be prevented more reliably.

  In the drawing, 11 is a switch, 12 is a switch control circuit, Fa and Fb are drive control circuits, Ma and Mb are MOS transistors, Mam and Mbm are main transistors, Mas and Mbs are sense transistors, and Dam and Dbm are parasitics of the main transistor. Diodes, Pca and Pcb are control power supplies, Ppa and Ppb are reference voltage generation circuits, and Rsa and Rsb are current limiting resistors.

Claims (11)

A MOS transistor having a main transistor (Mam, Mbm) and a sense transistor (Mas, Mbs) in which drains and gates are commonly connected, and connected so that a reflux current flows between the drain and source of the main transistor (Ma, Mb),
Control power supplies (Pca, Pcb) for supplying a control voltage having the same polarity as the drain voltage in a state where the main transistor is driven off and no current flows with reference to the source potential of the main transistor,
Current limiting resistors (Rsa, Rsb) provided between the control power supply and the source of the sense transistor;
When the voltage of the terminal on the sense transistor side of the current limiting resistor is a reflux detection voltage, the return detection voltage is lower than the control voltage and is in the reflux state in which the parasitic diodes (Dam, Dbm) of the main transistor are energized. A reference voltage generation circuit (Ppa, Ppb) for generating a higher reference voltage,
The recirculation detection voltage when the on-drive command is given and during the period when the off-drive command is given and before the on-drive command is given after the recirculation detection voltage becomes higher than the reference voltage A drive control circuit (Fa, Fb) for outputting an ON drive voltage to the MOS transistor when is lower than the reference voltage;
Synchronous rectification characterized by comprising a delay circuit (21a) for delaying the timing at which the drive control circuit starts to output an ON drive voltage to the MOS transistor during a period when an OFF drive command is given circuit. Main transistor (Mam, Mbm) and a cathode having a reflux detection diode (Da, Db) whose cathode is connected to the drain of the main transistor, connected so that the reflux current flows between the drain and source of the main transistor MOS transistors (Ma, Mb),
Control power supplies (Pca, Pcb) for supplying a control voltage having the same polarity as the drain voltage in a state where the main transistor is driven off and no current flows with reference to the source potential of the main transistor,
Current limiting resistors (Rsa, Rsb) provided between the control power supply and the anode of the reflux detection diode;
Reference voltage lower than the control voltage and higher than the return detection voltage in the return state in which the parasitic diodes (Dam, Dbm) of the main transistor are energized when the anode voltage of the return detection diode is a return detection voltage. A reference voltage generation circuit (Ppa, Ppb) for generating
The recirculation detection voltage when the on-drive command is given and during the period when the off-drive command is given and before the on-drive command is given after the recirculation detection voltage becomes higher than the reference voltage And a drive control circuit (Fa, Fb) for outputting an ON drive voltage to the MOS transistor when is lower than the reference voltage.   The drive control circuit is configured such that the return detection voltage is higher than the reference voltage after the return detection voltage is higher than the reference voltage until the on drive command is supplied in a period in which the off drive command is supplied. 3. The synchronous rectifier circuit according to claim 1, wherein when the voltage becomes low, an on-drive voltage is continuously output to the MOS transistor until an on-drive command is given thereafter.   3. A delay circuit (21a) for delaying a timing at which said drive control circuit starts outputting an on-drive voltage to said MOS transistor during a period in which an off-drive command is given. The synchronous rectifier circuit according to claim 3, which refers to claim 2. A power supply side switch (11a) provided between the control power supply and the source of the sense transistor;
While the drive control circuit outputs an off drive voltage to the MOS transistor in response to an off drive command, the switch is controlled to be in an on state, and the drive control circuit is turned on to the MOS transistor before the on drive command is given. And a switch control circuit (12) for controlling the power supply side switch to an OFF state during a period in which a current flows through the MOS transistor in response to an ON drive command on condition that no ON drive voltage is output. 4. The synchronous rectifier circuit according to claim 1, wherein the synchronous rectifier circuit is cited.   A source-side switch (11b) provided between the source of the sense transistor and the source of the main transistor and whose ON state is exclusively controlled by the switch control circuit (12) with the power-side switch. 6. The synchronous rectifier circuit according to claim 5, wherein: A current detection resistor (Rs2b) connected to any terminal side of the source side switch;
The synchronous rectification according to claim 6, further comprising an overcurrent detection circuit (24) for detecting an overcurrent based on a current flowing through the current detection resistor when the source side switch is turned on. circuit. A power supply side switch (11) provided between the current limiting resistor and the anode of the reflux detection diode;
While the drive control circuit outputs an off drive voltage to the MOS transistor in response to an off drive command, the switch is controlled to be in an on state, and the drive control circuit is turned on to the MOS transistor before the on drive command is given. And a switch control circuit (12) for controlling the power supply side switch to an OFF state during a period in which a current flows through the MOS transistor in response to an ON drive command on condition that no ON drive voltage is output. The synchronous rectifier circuit according to claim 3 or 4, wherein the synchronous rectifier circuit according to claim 2 or 2 is cited.   The said switch control circuit (12) is provided with the delay circuit (23b) which delays the timing which controls the said power supply side switch to an ON state, The Claim 1 characterized by the above-mentioned. Synchronous rectifier circuit. When the input capacitance of the drive control circuit is Cin, the voltage of the control power supply is Vcc, the reference voltage is Vp, and the drain voltage of the MOS transistor is Vout, the parasitic capacitance Csense of the sense transistor is
Csense <(Vcc-Vp) / Vout · Cin
The synchronous rectifier circuit according to claim 3, wherein the synchronous rectifier circuit is cited by claim 1 or claim 1. When the input capacitance of the drive control circuit is Cin, the voltage of the control power supply is Vcc, the reference voltage is Vp, and the drain voltage of the MOS transistor is Vout, the parasitic capacitance Cdiode of the reflux detection diode is
Cdiode <(Vcc-Vp) / Vout · Cin
The synchronous rectifier circuit according to claim 8, wherein the synchronous rectifier circuit is cited as claim 2 or claim 2.

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