JP3331601B2 - Load state detection circuit - Google Patents
Load state detection circuitInfo
- Publication number
- JP3331601B2 JP3331601B2 JP30740091A JP30740091A JP3331601B2 JP 3331601 B2 JP3331601 B2 JP 3331601B2 JP 30740091 A JP30740091 A JP 30740091A JP 30740091 A JP30740091 A JP 30740091A JP 3331601 B2 JP3331601 B2 JP 3331601B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- signal
- voltage
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】この発明は負荷状態検出回路に関
し、特に過電流検出、負荷ショート検出回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load state detecting circuit, and more particularly to an overcurrent detecting circuit and a load short detecting circuit.
【０００２】[0002]
【従来の技術】出力部にパワースイッチング素子を用い
た出力回路において負荷に過電流が流れた時、出力電流
を制限するための信号を検出する負荷状態検出回路があ
る。従来、この種の負荷状態検出回路は図３に示すよう
に電流検出抵抗ｒ１と、出力端子間の電流検出スイッチ
ング素子１５のコントロール信号を出力素子１のドライ
ブ信号と同一にしている。出力オン状態では、電流検出
スッチング素子１５はオン状態なので節点Ｐは、出力電
圧を反映する。従って、出力に過電流が流れた時、出力
電圧の降下はそのまま節点Ｐに出力され、この信号を基
準電圧Ｖｒｅｆ５と比較することで過電流を検出してい
た。2. Description of the Related Art There is a load state detecting circuit for detecting a signal for limiting an output current when an overcurrent flows in a load in an output circuit using a power switching element in an output section. Conventionally, in this type of load state detection circuit, the control signal of the current detection switching element 15 between the output terminal and the current detection resistor r1 is the same as the drive signal of the output element 1, as shown in FIG. In the output ON state, the node P reflects the output voltage because the current detection switching element 15 is in the ON state. Therefore, when an overcurrent flows to the output, the drop of the output voltage is output as it is to the node P, and the overcurrent is detected by comparing this signal with the reference voltage Vref5.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記の従来
の負荷状態検出回路は、電流検出スイッチング素子のコ
ントロール信号が直接、出力素子のドライブ信号につな
がっていたため、通常の出力ターンオン時に、ゲートド
ライブ回路の立上りに対する出力端子電圧の立上り遅れ
から電流検出スイッチング素子１５のゲート・ソース間
に電位差が生じ、また素子サイズの違いから、電流検出
スイッチング素子１５のスイッチング時間が出力素子の
それより早いため、出力立上り遅延の中間的な出力電圧
をモニターし、比較器で過電流と誤検出する欠点があっ
た。In the above-mentioned conventional load state detection circuit, the control signal of the current detection switching element is directly connected to the drive signal of the output element. The potential difference between the gate and source of the current detection switching element 15 occurs due to the delay of the rise of the output terminal voltage with respect to the rise of the current, and the current detection occurs due to the difference in element size.
Since the switching time of the switching element 15 is shorter than that of the output element, there is a disadvantage that the intermediate output voltage of the output rise delay is monitored and the comparator incorrectly detects an overcurrent.
【０００４】[0004]
【課題を解決するための手段】出力端子に接続された負
荷の電流を入力信号によって制御する出力パワーＭＯＳ
ＦＥＴを有する出力回路において、前記出力パワーＭＯ
ＳＦＥＴに並列に接続され前記出力端子電圧をモニター
する出力電圧モニター回路と、電源とＧＮＤ間に接続さ
れ出力電圧モニタ回路を制御するドライブ回路と、前記
出力端子電圧を基準電圧と比較して過電流信号を送出す
る過電流検出用比較器と、前記入力信号を遅滞させた信
号と前記ドライブ回路の出力信号とにもとづき負荷ショ
ート信号を送出する負荷ショート検出回路とを有し、前
記出力電圧モニター回路は前記入力信号がＯＦＦ信号時
モニター電圧の送出を禁止する手段を有し、前記ドライ
ブ回路は前記出力端子電圧を入力信号とするヒステリシ
スをもった反転回路であり、 前記基準電圧は前記ドライ
ブ回路のヒステリシス幅内に設定されたことを特徴とす
る負荷状態検出回路である。An output power MOS for controlling a load current connected to an output terminal by an input signal.
In an output circuit having an FET, the output power MO
Monitor the output terminal voltage connected in parallel with the SFET
An output voltage monitor circuit, is connected between the power supply and GND
Is a drive circuit for controlling the output voltage monitor circuit, said
Sends an overcurrent signal by comparing the output terminal voltage with the reference voltage
That the overcurrent detection comparator, and a load short-circuit detecting circuit for transmitting a load short-circuit signal based on the output signal of the signal obtained by delay said input signal and said drive circuit, said output voltage monitor circuit fill before The drive circuit includes means for inhibiting transmission of the monitor voltage when the output signal is an OFF signal, and the drive circuit includes a hysteresis circuit that uses the output terminal voltage as an input signal.
Ri inverting circuit der having a scan, the reference voltage is said dry
A load state detection circuit set within the hysteresis width of the circuit.
【０００５】[0005]
【作用】上記の構成によると、通常の出力オン時には、
出力ＰｏＭＯＳＦＥＴのドレイン・ソース間電圧はＶｃ
ｃに対して充分小さく、出力電圧モニター回路は、出力
電圧をモニターする。この時、出力に過電流が流れれば
出力ＰｏＭＯＳＦＥＴのドレイン・ソース間電圧は増大
しそれによる出力電圧の変動が出力電圧モニター回路に
モニターされ、過電流検出用比較器で過電流検出信号を
出す。According to the above configuration, at the time of normal output on,
The drain-source voltage of the output PoMOSFET is Vc
sufficient rather small for c, the output voltage monitor circuit monitors the output voltage. At this time, if an overcurrent flows to the output, the voltage between the drain and the source of the output PoMOSFET increases, and the fluctuation of the output voltage due to the increase is monitored by an output voltage monitor circuit , and an overcurrent detection comparator outputs an overcurrent detection signal. .
【０００６】しかし、負荷短絡時には、出力電圧が降下
するので一瞬、過電流検出はするがすぐにドライブ回路
によって出力電圧モニター回路のモニター信号はマスク
されるのでドライブ回路の出力信号とゲートドライブ回
路の制御信号との論理積を負荷ショート信号とする。そ
して過電流検出用比較器の基準電圧Ｖｒｅｆは、ドライ
ブ回路のヒステリシス幅内に設定し、出力ターンオン時
には、出力ＰｏＭＯＳＦＥＴのドレイン・ソース間電圧
が充分小さくなってはじめてドライブ回路は出力電圧モ
ニター回路を動作させるため、過電流の誤検出はなくな
る。また本出力回路にＯＮ信号が入ってから、出力電圧
モニター回路が出力をモニターするまでの間、負荷ショ
ート誤検出は遅延回路により解消できる。However, when the load is short-circuited, the output voltage drops and the overcurrent is detected for a moment. However, the monitor signal of the output voltage monitor circuit is immediately masked by the drive circuit, so that the output signal of the drive circuit and the gate drive circuit are output. The logical product with the control signal is defined as a load short signal. The reference voltage Vref of the overcurrent detection comparator is set within the hysteresis width of the drive circuit. When the output is turned on, the drive circuit operates the output voltage monitor circuit only when the drain-source voltage of the output PoMOSFET becomes sufficiently small. Therefore, erroneous detection of overcurrent is eliminated. After the ON signal is input to this output circuit, the output voltage
Until the monitor circuit monitors the output, false detection of a load short can be eliminated by the delay circuit.
【０００７】一方出力ターンオフ時には、出力電位がド
ライブ回路を反転させる前に、本出力回路のＯＦＦ信号
を検知して、モニター電圧の出力を禁止するので過電流
誤検出をなくせる。On the other hand, when the output is turned off , the output potential becomes low.
Prior to inverting the live circuit detects the OFF signal of the output circuit, it is prohibited to output the monitor voltage overcurrent
Eliminate erroneous detection .
【０００８】[0008]
【実施例】以下、この発明について図面を参照して説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【０００９】図１は、この発明の第１の実施例の回路図
である。図において、１はＮチャンネル出力パワーＭＯ
ＳＦＥＴ，２はゲートドライブ回路，３は過電流検出用
比較器，４は出力電圧モニター回路，５は出力電圧モニ
ター回路４を制御するドライブ回路，６は負荷ショート
検出用ＡＮＤ回路，７は出力負荷，８は遅延回路，９は
電流検出値マスク用Ｐチャンネルトランジスタ，１０は
電流検出用Ｐチャンネルトランジスタ，１１は比較器，
１２は遅延回路用コンデンサ，r1は電流検出用抵抗，r
2，r3，r4はヒステリシス比較器用抵抗，r5は遅延回路
用抵抗である。FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the figure, 1 is an N-channel output power MO
SFET, 2 is a gate drive circuit, 3 is an overcurrent detection comparator, 4 is an output voltage monitor circuit , and 5 is an output voltage monitor.
A drive circuit for controlling the inverter circuit 4, a AND circuit 6 for detecting a load short, an output load 7, a delay circuit 8, and a delay circuit 9.
P-channel transistor for current detection value mask , 10 is a P-channel transistor for current detection, 11 is a comparator,
12 is a delay circuit capacitor, r1 is a current detection resistor, r
2, r3 and r4 are resistors for a hysteresis comparator, and r5 is a resistor for a delay circuit.
【００１０】次に上記の回路図について動作を説明す
る。Next, the operation of the above circuit diagram will be described.
【００１１】まず、比較器１１のヒステリシス幅内に比
較器３の基準電圧Vref1が収まるようなr2，r3，r4の比
にする。すなわち比較器１１のハイレベルのしきい値を
ＶTH，ロウレベルのしきい値をＶTLとするとＶTL＜Vref
1 ＜ＶTHという関係に設定する。出力ターンオン時に
は、出力電位が上昇しVref1 を越え比較器１１のハイレ
ベルしきい値ＶTHを越えてはじめて、トランジスタ１０
がオンする。したがって、節点Ｑの電位をモニターする
ことで、出力パワーＭＯＳＦＥＴ１が充分ＯＮした状態
以後の電流をモニターすることとなる。負荷が過大とな
って、出力電流が過大な時、出力パワーＭＯＳＦＥＴ１
のオン抵抗ＲONが有限なので出力端子電位は降下する。
今、検出したい過電流値をＩoc以上とすると、基準電圧
をVerf1＝Ｖｃｃ?ＲON×Ｉocと設定すれば節点Ｑの電位
はほぼ出力端子電位に等しいので節点Ｑでモニターした
出力電位を比較器３で基準電圧Vref1 と比較することで
過電流を検出できる。First, the ratio of r2, r3, and r4 is set so that the reference voltage Vref1 of the comparator 3 falls within the hysteresis width of the comparator 11. That is, if the high-level threshold of the comparator 11 is VTH and the low-level threshold is VTL, VTL <Vref
1 Set the relationship VTH. At the time of output turn-on, the output voltage of the transistor 10 is not increased until the output potential exceeds Vref1 and exceeds the high-level threshold value VTH of the comparator 11.
Turns on. Therefore, by monitoring the potential of the node Q, the current after the output power MOSFET 1 is sufficiently turned on is monitored. When the load is excessive and the output current is excessive, the output power MOSFET 1
Has a finite on-resistance RON, the output terminal potential drops.
Assuming that the overcurrent value to be detected is equal to or greater than Ioc, if the reference voltage is set to Verf1 = Vcc? RON × Ioc, the potential of the node Q is almost equal to the output terminal potential. The overcurrent can be detected by comparing with the reference voltage Vref1.
【００１２】出力端子がＧＮＤと短絡した時、出力電位
が極端に降下し、比較器１１から“Ｈ”が出力され、ト
ランジスタ１０がオフして、過電流検出をしなくなると
共に、負荷ショート検出用ＡＮＤ回路６が負荷ショート
信号を出力する。出力ターンオフの時、トランジスタ９
のゲートに本出力回路の入力信号を接続しているのでこ
の入力信号がＯＮ→ＯＦＦになり、パワーＭＯＳＦＥＴ
１のオフで出力電位が降下しても、過電流と誤検出する
前にトランジスタ９のオンにより電流検出用抵抗r1をシ
ョートするので誤検出がなくなる。When the output terminal is short-circuited to GND, the output potential drops extremely, the comparator 11 outputs "H", the transistor 10 is turned off, and no overcurrent is detected. The AND circuit 6 outputs a load short signal. When the output is turned off, transistor 9
Since the input signal of this output circuit is connected to the gate of
Even if the output potential drops when 1 is off, the current detection resistor r1 is short-circuited by turning on the transistor 9 before erroneous detection as an overcurrent, so that erroneous detection is eliminated.
【００１３】上記、動作より、過電流，負荷ショートの
誤検出が生じないという利点がある。The above operation has the advantage that erroneous detection of overcurrent and load short does not occur.
【００１４】[0014]
【実施例２】図２は、この発明の第２実施例の回路図で
ある。Embodiment 2 FIG. 2 is a circuit diagram of a second embodiment of the present invention.
【００１５】前記第１の実施例の出力回路がオープンソ
ースのハイサイドスイッチであったのに対し、この第２
実施例はオープンドレインのローサイドスイッチであ
り、それに伴い第１実施例のＰチャンネルトランジスタ
９とＰチャンネルトランジスタ１０は、それぞれＮチャ
ンネルトランジスタ９ａ，１０ａに代えた。また、実施
例１では、出力電流が増えれば出力電位は降下したが、
この第２の実施例では、出力電位は上昇することを考慮
すれば、動作原理は第１の実施例と同様であるため同一
部分には、同一参照符号を付して、その説明を省略す
る。While the output circuit of the first embodiment is an open source high side switch,
The embodiment is an open-drain low-side switch, and accordingly, the P-channel transistor 9 and the P-channel transistor 10 of the first embodiment are replaced with N-channel transistors 9a and 10a, respectively. In the first embodiment, the output potential decreases as the output current increases.
In the second embodiment, the operation principle is the same as that of the first embodiment, considering that the output potential rises. Therefore, the same portions are denoted by the same reference numerals, and description thereof will be omitted. .
【００１６】[0016]
【発明の効果】以上説明したように、本発明は、過電流
検出のための出力電圧モニター回路が、その出力電圧を
入力として、ヒステリシスを持たせたドライブ回路によ
りドライブさせたことにより、出力ターンオン時の電流
誤検出を防止する効果がある。As described above, according to the present invention, the output voltage monitor circuit for detecting overcurrent is driven by the drive circuit having hysteresis with the output voltage as an input, so that the output is turned on. This has the effect of preventing erroneous detection of current at the time.
【図１】 この発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図２】 この発明の第２の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the present invention.
【図３】 従来・技術の回路図である。FIG. 3 is a circuit diagram of the related art.
１ 出力パワーＭＯＳＦＥＴ ２ ゲートドライブ回路 ３ 過電流検出用比較器 ４ 出力電圧モニター回路 ５ ドライブ回路 ６ 負荷ショート検出用ＡＮＤ回路 ７ 出力負荷 ８ 遅延回路 ９ 電流検出値マスク用トランジスタ（Ｐチャンネル） １０ 電流検出用トランジスタ（Ｐチャンネル） １１ ドライブ回路用比較器 １２ 遅延回路用コンデンサ r1 電流検出用抵抗 r2，r3，r4 ヒステリシス用抵抗 r5 遅延回路用抵抗 Ｑ 節点 １３，１４ 信号反転用インバータ ９ａ 電流検出値マスク用トランジスタ（Ｎチャンネ
ル） １０ａ 電流検出用トランジスタ（Ｎチャンネル） Ｂ 節点Reference Signs List 1 output power MOSFET 2 gate drive circuit 3 comparator for overcurrent detection 4 output voltage monitor circuit 5 drive circuit 6 AND circuit for load short detection 7 output load 8 delay circuit 9 transistor for current detection value mask (P channel) 10 current detection Transistor (P channel) 11 comparator for drive circuit 12 capacitor for delay circuit r1 resistor for current detection r2, r3, r4 resistor for hysteresis r5 resistor for delay circuit Q node 13, 14 inverter for signal inversion 9a for current detection value mask Transistor (N-channel) 10a Transistor for current detection (N-channel) B Node
フロントページの続き (56)参考文献 特開 平３−105262（ＪＰ，Ａ) 特開 平２−181664（ＪＰ，Ａ) 特開 平２−87930（ＪＰ，Ａ) 特開 平２−136066（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H02H 3/08 - 3/253 Continuation of the front page (56) References JP-A-3-105262 (JP, A) JP-A-2-181664 (JP, A) JP-A-2-87930 (JP, A) JP-A-2-136066 (JP) , A) (58) Field surveyed (Int. Cl. 7 , DB name) H02H 3/08-3/253
Claims (3)
号によって制御する出力パワーＭＯＳＦＥＴを有する出
力回路において、 前記出力パワーＭＯＳＦＥＴに並列に接続され前記出力
端子電圧をモニターする出力電圧モニター回路と、 電源とＧＮＤ間に接続され出力電圧モニタ回路を制御す
るドライブ回路と、前記出力端子電圧を基準電圧と比較して過電流信号を送
出する過電流検出用比較器と、 前記入力信号を遅滞させた信号と前記ドライブ回路の出
力信号とにもとづき負荷ショート信号を送出する負荷シ
ョート検出回路とを有し、 前記出力電圧モニター回路は前記入力信号がＯＦＦ信号
時モニター電圧の送出を禁止する手段を有し、 前記ドライブ回路は前記出力端子電圧を入力信号とする
ヒステリシスをもった反転回路であり、 前記基準電圧は前記ドライブ回路のヒステリシス幅内に
設定された ことを特徴とする負荷状態検出回路。(1)Connected to the output terminalInput current of load
Output having an output power MOSFET controlled by a signal
In the power circuit, connected in parallel with the output power MOSFETAnd said output
Monitor terminal voltageOutput voltage monitor circuit, connected between power supply and GNDControl the output voltage monitor circuit.
ToDrive circuit,The output terminal voltage is compared with a reference voltage to send an overcurrent signal.
An overcurrent detection comparator A signal that delays the input signal and the output of the drive circuit
A load system that sends a load short signal based on the force signal
And an output voltage monitor circuit.Is beforeInput signal is OFF signal
Means for prohibiting the transmission of a time monitor voltage, wherein the drive circuit uses the output terminal voltage as an input signal.
HysteresisInverting circuit withAnd The reference voltage is within the hysteresis width of the drive circuit.
Set A load state detection circuit, characterized in that:
のソースであって、前記負荷ショート検出回路が、前記
ドライブ回路の出力と前記入力信号を遅延させた信号と
の論理積回路であることを特徴とする請求項１に記載の
負荷状態検出回路。2. An output terminal is a source of an N-type power MOS transistor, and said load short detection circuit is an AND circuit of an output of said drive circuit and a signal obtained by delaying said input signal. The load state detection circuit according to claim 1, wherein
のドレインであって、前記負荷ショート検出回路が、前
記ドライブ回路の出力を反転した信号と、前記入力信号
を遅延させた信号との論理積回路であることを特徴とす
る請求項１に記載の負荷状態検出回路。3. An AND circuit according to claim 1, wherein said output terminal is a drain of an N-type power MOS transistor, and said load short-circuit detecting circuit outputs a signal obtained by inverting an output of said drive circuit and a signal obtained by delaying said input signal. The load state detection circuit according to claim 1, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30740091A JP3331601B2 (en) | 1991-11-22 | 1991-11-22 | Load state detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30740091A JP3331601B2 (en) | 1991-11-22 | 1991-11-22 | Load state detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05146049A JPH05146049A (en) | 1993-06-11 |
| JP3331601B2 true JP3331601B2 (en) | 2002-10-07 |
Family
ID=17968597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30740091A Expired - Fee Related JP3331601B2 (en) | 1991-11-22 | 1991-11-22 | Load state detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3331601B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102160271B (en) | 2008-09-22 | 2013-11-20 | 富士通株式会社 | Control method for power control circuit, power supply unit, power supply system, and power controller control method |
| JP2010218003A (en) * | 2009-03-13 | 2010-09-30 | Ricoh Co Ltd | Medium controller |
| JP5609821B2 (en) * | 2011-08-25 | 2014-10-22 | 株式会社デンソー | Load drive device |
| JP7325314B2 (en) * | 2019-12-12 | 2023-08-14 | 三菱電機株式会社 | semiconductor equipment |
-
1991
- 1991-11-22 JP JP30740091A patent/JP3331601B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05146049A (en) | 1993-06-11 |
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