KR101086560B1 - 부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장 - Google Patents

부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장 Download PDF

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KR101086560B1
KR101086560B1 KR1020087021913A KR20087021913A KR101086560B1 KR 101086560 B1 KR101086560 B1 KR 101086560B1 KR 1020087021913 A KR1020087021913 A KR 1020087021913A KR 20087021913 A KR20087021913 A KR 20087021913A KR 101086560 B1 KR101086560 B1 KR 101086560B1
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booth
sign
tree
multiplication
bit
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KR20080094813A (ko
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라지브 크리쉬나무디
크리스토퍼 에드워드 쿠브
윌리엄 씨. 앤더슨
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콸콤 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49994—Sign extension
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Mobile Radio Communication Systems (AREA)
KR1020087021913A 2006-02-15 2007-02-15 부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장 Expired - Fee Related KR101086560B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/356,359 2006-02-15
US11/356,359 US7797366B2 (en) 2006-02-15 2006-02-15 Power-efficient sign extension for booth multiplication methods and systems
PCT/US2007/062256 WO2007095626A1 (en) 2006-02-15 2007-02-15 Power-efficient sign extension for booth multiplication methods and systems

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020117020529A Division KR101173405B1 (ko) 2006-02-15 2007-02-15 부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장

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KR20080094813A KR20080094813A (ko) 2008-10-24
KR101086560B1 true KR101086560B1 (ko) 2011-11-23

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KR1020087021913A Expired - Fee Related KR101086560B1 (ko) 2006-02-15 2007-02-15 부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장
KR1020117020529A Expired - Fee Related KR101173405B1 (ko) 2006-02-15 2007-02-15 부스 곱셈 방법들 및 시스템들을 위한 전력-효율적인 부호 확장

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Country Link
US (1) US7797366B2 (https=)
EP (1) EP1984809A1 (https=)
JP (4) JP2009527064A (https=)
KR (2) KR101086560B1 (https=)
CN (2) CN102279724B (https=)
TW (1) TWI332625B (https=)
WO (1) WO2007095626A1 (https=)

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US7809783B2 (en) * 2006-02-15 2010-10-05 Qualcomm Incorporated Booth multiplier with enhanced reduction tree circuitry
US20160188327A1 (en) * 2014-12-24 2016-06-30 Elmoustapha Ould-Ahmed-Vall Apparatus and method for fused multiply-multiply instructions
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US10802826B2 (en) 2017-09-29 2020-10-13 Intel Corporation Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
US10664277B2 (en) 2017-09-29 2020-05-26 Intel Corporation Systems, apparatuses and methods for dual complex by complex conjugate multiply of signed words
US10534838B2 (en) 2017-09-29 2020-01-14 Intel Corporation Bit matrix multiplication
US10795676B2 (en) 2017-09-29 2020-10-06 Intel Corporation Apparatus and method for multiplication and accumulation of complex and real packed data elements
US10795677B2 (en) 2017-09-29 2020-10-06 Intel Corporation Systems, apparatuses, and methods for multiplication, negation, and accumulation of vector packed signed values
US10514924B2 (en) 2017-09-29 2019-12-24 Intel Corporation Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
US11074073B2 (en) 2017-09-29 2021-07-27 Intel Corporation Apparatus and method for multiply, add/subtract, and accumulate of packed data elements
US11243765B2 (en) 2017-09-29 2022-02-08 Intel Corporation Apparatus and method for scaling pre-scaled results of complex multiply-accumulate operations on packed real and imaginary data elements
US11256504B2 (en) * 2017-09-29 2022-02-22 Intel Corporation Apparatus and method for complex by complex conjugate multiplication
CN110688087B (zh) * 2019-09-24 2024-03-19 上海寒武纪信息科技有限公司 数据处理器、方法、芯片及电子设备
CN110554854B (zh) * 2019-09-24 2024-05-03 上海寒武纪信息科技有限公司 数据处理器、方法、芯片及电子设备
TWI696947B (zh) 2019-09-26 2020-06-21 中原大學 乘積累加裝置及其方法
JP7317151B2 (ja) * 2020-02-06 2023-07-28 三菱電機株式会社 複素乗算回路
JP7381426B2 (ja) * 2020-03-19 2023-11-15 株式会社東芝 演算回路
US11327718B2 (en) 2020-03-19 2022-05-10 Kabushiki Kaisha Toshiba Arithmetic circuitry for power-efficient multiply-add operations
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US11868741B2 (en) * 2021-06-17 2024-01-09 Rebellions Inc. Processing element, neural processing device including same, and multiplication operation method using same
CN119512501B (zh) * 2024-11-01 2026-03-17 杭州电子科技大学 一种基于基-4Booth编码和改进Wallace压缩树的乘法器

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Publication number Publication date
CN101384990B (zh) 2012-09-19
JP2012089144A (ja) 2012-05-10
US20070192399A1 (en) 2007-08-16
KR20110114698A (ko) 2011-10-19
JP5215433B2 (ja) 2013-06-19
CN102279724A (zh) 2011-12-14
JP2014209347A (ja) 2014-11-06
TW200802078A (en) 2008-01-01
CN101384990A (zh) 2009-03-11
TWI332625B (en) 2010-11-01
CN102279724B (zh) 2015-09-16
JP2009527064A (ja) 2009-07-23
KR101173405B1 (ko) 2012-08-10
JP5611923B2 (ja) 2014-10-22
KR20080094813A (ko) 2008-10-24
EP1984809A1 (en) 2008-10-29
JP2011222024A (ja) 2011-11-04
US7797366B2 (en) 2010-09-14
WO2007095626A1 (en) 2007-08-23

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