KR101065049B1 - 변형된 핀펫 채널 제조 방법 - Google Patents

변형된 핀펫 채널 제조 방법 Download PDF

Info

Publication number
KR101065049B1
KR101065049B1 KR1020067013878A KR20067013878A KR101065049B1 KR 101065049 B1 KR101065049 B1 KR 101065049B1 KR 1020067013878 A KR1020067013878 A KR 1020067013878A KR 20067013878 A KR20067013878 A KR 20067013878A KR 101065049 B1 KR101065049 B1 KR 101065049B1
Authority
KR
South Korea
Prior art keywords
semiconductor layer
layer
trench
channel region
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020067013878A
Other languages
English (en)
Korean (ko)
Other versions
KR20060130098A (ko
Inventor
쿠이 시앙
제임스 엔. 팬
정-석 구
Original Assignee
글로벌파운드리즈 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 글로벌파운드리즈 인크. filed Critical 글로벌파운드리즈 인크.
Publication of KR20060130098A publication Critical patent/KR20060130098A/ko
Application granted granted Critical
Publication of KR101065049B1 publication Critical patent/KR101065049B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020067013878A 2004-01-12 2004-12-21 변형된 핀펫 채널 제조 방법 Expired - Fee Related KR101065049B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/755,763 US7138302B2 (en) 2004-01-12 2004-01-12 Method of fabricating an integrated circuit channel region
US10/755,763 2004-01-12

Publications (2)

Publication Number Publication Date
KR20060130098A KR20060130098A (ko) 2006-12-18
KR101065049B1 true KR101065049B1 (ko) 2011-09-19

Family

ID=34739641

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067013878A Expired - Fee Related KR101065049B1 (ko) 2004-01-12 2004-12-21 변형된 핀펫 채널 제조 방법

Country Status (8)

Country Link
US (1) US7138302B2 (enExample)
EP (1) EP1723668B1 (enExample)
JP (1) JP2007518272A (enExample)
KR (1) KR101065049B1 (enExample)
CN (1) CN100477126C (enExample)
DE (2) DE112004002641B4 (enExample)
TW (1) TWI360197B (enExample)
WO (1) WO2005071728A1 (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
KR100618852B1 (ko) * 2004-07-27 2006-09-01 삼성전자주식회사 높은 동작 전류를 갖는 반도체 소자
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7271448B2 (en) * 2005-02-14 2007-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple gate field effect transistor structure
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US7365401B2 (en) * 2006-03-28 2008-04-29 International Business Machines Corporation Dual-plane complementary metal oxide semiconductor
WO2008030574A1 (en) 2006-09-07 2008-03-13 Amberwave Systems Corporation Defect reduction using aspect ratio trapping
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US8502263B2 (en) 2006-10-19 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitter-based devices with lattice-mismatched semiconductor structures
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
WO2009035746A2 (en) 2007-09-07 2009-03-19 Amberwave Systems Corporation Multi-junction solar cells
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US7872303B2 (en) * 2008-08-14 2011-01-18 International Business Machines Corporation FinFET with longitudinal stress in a channel
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
CN102379046B (zh) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法
JP5666961B2 (ja) * 2011-03-31 2015-02-12 猛英 白土 半導体記憶装置
JP5667017B2 (ja) * 2011-09-03 2015-02-12 猛英 白土 半導体装置及びその製造方法
FR3029011B1 (fr) * 2014-11-25 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede ameliore de mise en contrainte d'une zone de canal de transistor
US9362400B1 (en) 2015-03-06 2016-06-07 International Business Machines Corporation Semiconductor device including dielectrically isolated finFETs and buried stressor
US10411128B1 (en) 2018-05-22 2019-09-10 International Business Machines Corporation Strained fin channel devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors
US20030201458A1 (en) 2002-03-19 2003-10-30 Clark William F. Strained fin fets structure and method
US6855583B1 (en) * 2003-08-05 2005-02-15 Advanced Micro Devices, Inc. Method for forming tri-gate FinFET with mesa isolation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076334A (ja) * 2000-08-30 2002-03-15 Hitachi Ltd 半導体装置及びその製造方法
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
CN1225799C (zh) * 2002-04-24 2005-11-02 华邦电子股份有限公司 金属氧化物半导体场效应晶体管及其制造方法
WO2003105189A2 (en) 2002-06-07 2003-12-18 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6806534B2 (en) * 2003-01-14 2004-10-19 International Business Machines Corporation Damascene method for improved MOS transistor
US6815738B2 (en) 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
EP1602125B1 (en) * 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation process
US6835618B1 (en) * 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6955969B2 (en) * 2003-09-03 2005-10-18 Advanced Micro Devices, Inc. Method of growing as a channel region to reduce source/drain junction capacitance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors
US20030201458A1 (en) 2002-03-19 2003-10-30 Clark William F. Strained fin fets structure and method
US6855583B1 (en) * 2003-08-05 2005-02-15 Advanced Micro Devices, Inc. Method for forming tri-gate FinFET with mesa isolation

Also Published As

Publication number Publication date
TWI360197B (en) 2012-03-11
DE602004006782T2 (de) 2008-01-24
CN100477126C (zh) 2009-04-08
EP1723668A1 (en) 2006-11-22
TW200529367A (en) 2005-09-01
WO2005071728A1 (en) 2005-08-04
DE112004002641T5 (de) 2006-12-14
US7138302B2 (en) 2006-11-21
US20050153486A1 (en) 2005-07-14
EP1723668B1 (en) 2007-05-30
JP2007518272A (ja) 2007-07-05
CN1902744A (zh) 2007-01-24
DE112004002641B4 (de) 2009-01-02
DE602004006782D1 (de) 2007-07-12
KR20060130098A (ko) 2006-12-18

Similar Documents

Publication Publication Date Title
KR101065049B1 (ko) 변형된 핀펫 채널 제조 방법
US10998425B2 (en) FinFET structure and method for fabricating the same
US8900973B2 (en) Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion
US12027607B2 (en) Methods for GAA I/O formation by selective epi regrowth
US9230989B2 (en) Hybrid CMOS nanowire mesh device and FINFET device
US6709982B1 (en) Double spacer FinFET formation
EP1547156B1 (en) Finfet having improved carrier mobility and method of its formation
US10879242B2 (en) Method of manufacturing semiconductor device on hybrid substrate
KR100585171B1 (ko) 다면 채널을 가지는 반도체 소자 및 그 제조 방법
US9053981B2 (en) Hybrid CMOS nanowire mesh device and PDSOI device
US6936516B1 (en) Replacement gate strained silicon finFET process
US9117907B2 (en) Semiconductor device
CN101023530A (zh) 高迁移率块体硅p沟道场效应晶体管
US20150357332A1 (en) Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
CN103681342B (zh) 一种导电沟道制作方法
CN117673149A (zh) 半导体装置及其形成方法
KR20020058256A (ko) Ｂｃ ｐｍｏｓｆｅｔ 및 그 제조방법

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20140825

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20150819

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20160818

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20170818

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180908

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180908

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000