KR101027179B1 - 회로 기판 상에의 반도체 부품의 탑재 방법 - Google Patents

회로 기판 상에의 반도체 부품의 탑재 방법 Download PDF

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KR101027179B1
KR101027179B1 KR1020097010427A KR20097010427A KR101027179B1 KR 101027179 B1 KR101027179 B1 KR 101027179B1 KR 1020097010427 A KR1020097010427 A KR 1020097010427A KR 20097010427 A KR20097010427 A KR 20097010427A KR 101027179 B1 KR101027179 B1 KR 101027179B1
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South Korea
Prior art keywords
solder
semiconductor component
substrate
stud bumps
circuit board
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KR1020097010427A
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English (en)
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KR20090101441A (ko
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유키후미 오야마
가즈시게 도리야마
히데토시 니시와키
야스미츠 오리이
도시히코 니시오
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인터내셔널 비지네스 머신즈 코포레이션
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
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  • Engineering & Computer Science (AREA)
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  • Mechanical Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 부품의 스터드 범프에 균일한 양의 땜납을 공급하고, 회로 기판 상의 접합 패드와 땜납 접합시키는 것을 목적으로 한다.
복수의 스터드 범프(12)가 형성된 반도체 부품(10)을 준비하는 단계, 스터드 범프의 각각에 대응하는 고형 땜납(14)이 배열된 땜납 기판(13)을 준비하는 단계, 스터드 범프의 각각에 대응하는 접합 패드(21)를 갖는 회로 기판(20)을 준비하는 단계, 스터드 범프의 각각의 선단부에 땜납 기판 상의 대응하는 고형 땜납을 부착시키는 단계, 스터드 범프의 선단부에 부착된 고형 땜납을 땜납 기판으로부터 분리하는 단계, 스터드 범프의 각각의 선단부에 부착된 고형 땜납과 대응하는 접합 패드를 접촉시키는 단계, 대응하는 접합 패드에 접촉시킨 고형 땜납을 용융시켜 스터드 범프의 각각과 대응하는 접합 패드를 땜납 접합시키는 단계를 포함하는 방법이 제공된다.

Description

회로 기판 상에의 반도체 부품의 탑재 방법{METHOD FOR MOUNTING SEMICONDUCTOR COMPONENT ON CIRCUIT BOARD}
본 발명은 회로 기판 상에 반도체 부품을 탑재하는 방법에 관한 것이다. 본 발명은 특히 스터드 범프를 갖는 반도체 부품과 접합 패드를 갖는 회로 기판을 땜납을 이용하여 접합시키기 위한 방법에 관한 것이다.
반도체 부품을 회로 기판에 전기 접합시키는 방법으로서, 양자의 접합(전극) 패드를 땜납을 이용하여 접합시키는 플립 칩 본딩(FCB)법이 있다. 이 FCB법의 하나로, 반도체 부품의 접합 패드에 범프를 형성하고, 회로 기판의 접합 패드에 미리 땜납층을 형성하는 방법(프리코팅법)이 있다. 도 1은 프리코팅법을 설명하기 위한 도면이다. 범프(2)가 형성된 반도체 부품(1)과, 기판(3) 상의 접합 패드(4) 상에 땜납층(5)이 형성된 기판(3)을 준비한다(a). 범프(2)와 접합 패드(4)를 정렬시킨 후에 접촉시킨다(b). 가열하여 접합 패드(4) 상의 땜납층(5)을 용융시켜 범프(2)와 접합 패드(4)를 땜납 접합한다(c).
도 1의 종래의 방법에는, 예컨대 이하와 같은 문제가 있다. 접합 패드(4)가 Cu로 이루어지고, 또한 땜납 재료로서 Sn-Ag를 사용한 경우, 접합 패드(4) 상에 땜납층(5)을 형성할 때의 가열(프리코팅 가열)에 의해 땜납 속의 Sn과 접합 패드(4) 를 구성하는 Cu 간에 금속간 화합물(Sn-Cu)이 형성되어 버린다. 그 결과, 땜납 속의 Sn 원자가 감소하고 Ag의 비율이 커져 땜납의 융점이 상승한다. 또한, Sn-Pb 공정(共晶) 땜납에서도, 공정점인 63% Sn-37% Pb의 비율이 변함으로써 마찬가지로 융점은 상승한다. Pb가 함유되지 않은 Sn-Ag계의 경우는, 특별히 이러한 융점 상승이 현저해진다.
땜납의 융점이 상승하면, 도 1c의 땜납을 용융시키기 위한 가열 온도를 높여야 한다. 그 결과, 기판과 반도체 부품의 열팽창계수의 차에 의해 발생하는 신장(열팽창)의 차도 커진다. 그리고, 스터드 범프(2)와 접합 패드(4)의 위치 어긋남이나 기판(3)의 휨에 기인한 결함이 발생한다. 또한, 프리코팅시와 땜납 접합시의 2회의 땜납 용융에 있어서 형성되는 Ag3Sn 결정의 경도가 높기 때문에, 용융후의 고화한 땜납에 크랙이 발생하기 쉽다.
프리코팅시의 땜납의 용융을 회피하는 종래 방법으로서, 페이스트 전사법 있다. 도 2는 페이스트 전사법을 설명하기 위한 도면이다. 반도체 부품(1)의 범프(2)를 땜납 페이스트(7) 내에 침지한다(a). 땜납 페이스트(7)는 땜납 입자에 점성을 갖는 플럭스를 혼합한 것이다. 플럭스의 점성에 의해 반도체 부품(1)의 범프(2)의 표면에 땜납 페이스트(8)가 부착된다. 땜납 페이스트(8)가 부착된 범프(2)를 기판(3) 상의 접합 패드(4) 상에 위치 설정한다(b). 그 후, 범프(2)를 가열하여 땜납 페이스트(8)를 용융시켜 범프(2)와 접합 패드(4)를 고화한 땜납(9)에 의해 접합시킨다(c).
도 2의 페이스트 전사법에서는, 1회밖에 땜납을 용융시키지 않기 때문에, 도 1의 방법에 있어서의 Sn-Cu 금속간 화합물 혹은 Ag3Sn의 생성에 기인한 문제를 줄일 수 있다. 그러나, 페이스트 전사법에는 이하의 문제가 있다. 땜납 페이스트 내의 플럭스의 점도가 높은 경우, 범프로의 페이스트 부착시에 인접한 범프 사이에서 땜납 페이스트가 이어져 브릿지를 형성하게 된다. 반대로, 그 점성이 낮은 경우, 범프로의 페이스트의 부착량이 적어지게 된다. 땜납 용융 후에, 전자의 경우는 범프간의 쇼트를 발생시키고, 후자의 경우는, 땜납 접합 강도의 저하(단선)를 발생시킨다. 양자의 경우 모두 땜납 접합 불량이 된다.
반도체 부품과 회로 기판과의 전기 접속을 그 접속시에 땜납을 용융하지 않고 행하는 방법이 일본의 공개 특허 공보, 평성 제6-188289호와 제2000-232129호에 개시되어 있다. 이들의 종래 기술에서는, 기판 상의 콘택트 핀을 반도체 부품 상의 볼형의 땜납 범프에 푹 찌름으로써 양자의 전기 접속을 취한다. 그러나, 단순히 핀을 땜납볼에 푹 찌르고 있을 뿐이기 때문에, 그 접합부의 강도가 낮고 또한 접촉 저항도 용융시키는 경우에 비하여 커진다. 또한, 이 2개의 종래 기술은, 땜납 범프가 반도체 소자의 전극 패드에 미리 형성되어 있고, 회로 기판측에 미리 땜납 층을 형성하는 도 1 및 도 2의 종래 방법과 다르다.
특허 문헌 1: 일본 공개 특허 공보 평성 제6-188289호
특허 문헌 2 : 일본 공개 특허 공보 제2000-232129호
본 발명의 목적은 반도체 부품의 스터드 범프와 회로 기판의 접합 패드를 1회의 땜납 용융으로 접합시킬 수 있는 방법을 제공하는 것이다.
본 발명의 목적은 반도체 부품의 모든 스터드 범프에 미리 균일한 양의 땜납을 공급한 후에, 회로 기판 상의 접합 패드와 스터드 범프를 땜납 접합시키는 방법을 제공하는 것이다.
본 발명의 목적은 반도체 부품의 스터드 범프와 회로 기판의 Cu제 접합 패드를 땜납 접합시킬 때, Sn-Cu 금속간 화합물의 형성을 경감할 수 있는 접합 방법을 제공하는 것이다.
본 발명의 목적은 Pb가 함유되지 않은 땜납을 이용한 반도체 부품의 스터드 범프와 회로 기판의 접합에 있어서, 땜납의 리플로우 온도의 상승을 억제할 수 있는 접합 방법을 제공하는 것이다.
본 발명에 따르면, 회로 기판 상에 반도체 부품을 탑재하는 방법으로서, 표면에 복수의 스터드 범프(12)가 형성된 반도체 부품(10)을 준비하는 단계와, 표면에 복수의 스터드 범프 각각에 대응하는 고형 땜납(14)이 배열된 땜납 기판(13)을 준비하는 단계와, 표면에 복수의 스터드 범프 각각에 대응하는 접합 패드(21)를 갖는 회로 기판(20)을 준비하는 단계와, 복수의 스터드 범프 각각의 선단부에, 땜납 기판 상의 대응하는 고형 땜납을 부착시키는 단계와, 스터드 범프의 선단부에 부착된 고형 땜납을 땜납 기판으로부터 분리하는 단계와, 스터드 범프의 각각의 선단부에 부착된 고형 땜납과 대응하는 접합 패드를 접촉시키는 단계, 그리고 대응하는 접합 패드에 접촉시킨 고형 땜납을 용융시켜 스터드 범프 각각과 대응하는 접합 패드를 땜납 접합시키는 단계를 포함하는 방법이 제공된다.
본 발명에 따르면, 반도체 부품의 스터드 범프와 회로 기판의 접합 패드를 1회의 땜납 용융으로 땜납 접합시킬 수 있다.
본 발명에 따르면, 반도체 부품의 모든 스터드 범프에 미리 균일한 양의 땜납을 공급한 후에, 회로 기판 상의 접합 패드와 스터드 범프를 땜납 접합시킬 수 있다.
본 발명에 따르면, 반도체 부품의 스터드 범프와 회로 기판의 Cu제 접합 패드를 Sn을 함유한 땜납을 이용하여 접합시킬 때, Sn-Cu 금속간 화합물의 형성을 경감하고, 또한 Ag3Sn 등의 결정 석출을 억제할 수 있다.
본 발명에 따르면, Sn이 주인 땜납을 이용한 경우, 반도체 부품의 스터드 범프와 회로 기판의 접합에 있어서, 땜납의 리플로우 온도의 상승을 억제할 수 있다.
도 1은 종래의 프리코팅법을 설명하기 위한 도면이다.
도 2는 종래의 페이스트 전사법을 설명하기 위한 도면이다.
도 3은 본 발명의 방법(플로우)을 설명하기 위한 도면이다.
도 4는 본 발명의 반도체 부품과 땜납 기판의 관계를 나타내기 위한 도면이다.
도 5는 본 발명의 땜납 기판의 다른 예를 나타낸 도면이다.
〈도면의 주요 부분에 대한 부호의 설명〉
1, 10 : 반도체 부품
2, 12 : 스터드 범프
3, 20 : 기판
4, 21 : 접합 패드
5 : 땜납 층
7, 8 : 땜납 페이스트
9 : 땜납(접합)
11 : 접합 패드
13 : 땜납 기판
14 : 땜납볼
15 : 개구
17 : 스터드 범프의 선단
18 : 충전 땜납
본 발명에 대해서 도면을 참조하여 이하에 상세히 설명한다. 도 3은 본 발명의 방법(플로우)을 설명하기 위한 도면이다. 공정 (a)에서 표면 상의 접합 패드(11)에 복수의 스터드 범프(12)가 형성된 반도체 부품(10)을 준비한다. 또한, 공정 (a)에서 스터드 범프(12) 각각에 대응하는 고형 땜납(14)이 배열된 땜납 기판(13)을 준비한다. 도 3a의 고형 땜납(14)은 구형이다. 구형의 땜납볼(14)은 종래의 인쇄법 또는 스프레이법 등의 임의의 방법으로 제작할 수 있다. 땜납볼(14) 의 재료로서는 Pb가 함유된 Sn-Pb계, Pb가 함유되지 않은 Sn-Ag계 등의 1원계 또는 2원계 이상의 임의의 땜납 재료를 선택할 수 있다. 땜납볼(14)의 사이즈(직경)는 스터드 범프(12)의 사이즈, 그 간격(피치) 등에 따라 작성 가능한 범위에서 임의로 결정할 수 있다. 그 사이즈는 ㎚ 정도에서 ㎜ 정도까지 임의로 선택 가능하다.
반도체 부품(10)에는 마이크로 프로세서 유닛(MPU)이나 시스템 온 칩(SOC) 등의 대형 IC 칩이나 다른 비교적 작은 반도체 칩 등의 각종 전자부품이 포함된다. 스터드 범프(12)의 수는 반도체 부품의 사이즈, 전극(접합 패드)의 수에 따라 변화된다. 스터드 범프(12)는 돌기형 선단부(17)를 갖는다. 스터드 범프(12)의 형상은 도 3에 도시된 형상에 한정되지 않고, 예컨대 원주형, 원추형, 직방체 등의 다른 형상이라도 좋다. 스터드 범프(12)는 예컨대 Au, Ag, Cu, Al 및 Ni를 함유하는 그룹에서 선택된 1개 또는 2개 이상의 금속의 조합으로 이루어진다. 땜납 기판(13)은 땜납볼(14)이 수용되는 개구(15)를 갖고 있다. 개구(15)는 적어도 대응하는 스터드 범프(12)의 개수만큼 형성된다. 개구(15)는 적어도 땜납볼(14)의 일부(하부)가 들어가는 깊이 및 폭(내경)을 갖는다. 개구(15)는 오목부 또는 땜납볼(14)을 유지할 수 있으면 관통 구멍이라도 좋다.
도 4는 반도체 부품(10)과 땜납 기판(13)의 관계를 나타낸 사시 측면도이다. 땜납 기판(13)의 개구(15)는 반도체 부품(10)의 스터드 범프(12)에 1:1로 대응하고 있다. 각 개구(15)에는 땜납볼(14)이 들어가 있다. 도 5는 땜납 기판(13) 및 충전 땜납(18)의 다른 예를 나타낸 도면이다. 도 5a에서는, 개구(15)는 땜납 기판(13)의 표면으로부터 개구의 바닥부를 향해 테이퍼지는 형상을 갖고 있다. 이러 한 형상의 경우, 개구가 확장되어 있기 때문에, 땜납볼(14)을 스터드 범프(12)에 의해 꺼내기 쉽다. 도 5b는 땜납볼(14)을 이용하지 않은 경우의 예이다. 각 개구(15)에 땜납이 충전되어 있는 형상(18)을 갖고 있다. 이 경우, 별도로 땜납볼(14)을 준비하지 않아도 좋다고 하는 장점이 있다. 그 반면, 충전 땜납(18)을 스터드 범프(12)에 의해 쉽게 꺼낼 수 없다고 하는 단점이 있다. 이 단점을 보완하기 위해서 개구(15)에 땜납을 충전하기 전에 개구(15)의 표면에 플럭스를 도포하여 충전 땜납(18)이 개구(15)로부터 빠져나가기 쉽게 해 두는 등의 대응이 필요하다.
도 3으로 되돌아가, 공정 (b)에서 스터드 범프(12)의 각각과 대응하는 땜납볼(14)의 위치가 맞춰지도록 반도체 부품(10)과 땜납 기판(13)을 가까이 한다. 그 후, 스터드 범프(12) 각각의 선단부(17)를 대응하는 땜납볼(14)에 푹 찌른다. 그 때, 반도체 부품(10) 측에서 또는 땜납 기판(13) 측에서 힘을 가한다. 땜납볼(14) 속에 들어가는 스터드 범프(12)의 선단부(17)의 길이는 그 가해지는 힘에 의해 조정된다. 또한, 그 힘은 가압 부재에 의해 직접 또는 공기 등의 기체 혹은 액체를 통해 간접적으로 반도체 부품(10) 또는 땜납 기판(13)에 가해진다. 땜납볼(14)에 스터드 범프(12)를 푹 찌를 때에, 땜납의 융점을 초과하지 않는 범위에서 땜납볼(14)을 가열하여도 좋다. 스터드 범프(12)의 선단부(17)가 땜납볼(14)의 표면에서 미끄러져 버려 땜납볼(14)에 꽂히기 어려운 경우는, 땜납볼(14)의 상부를 평탄하게 하여도 좋다.
도 3의 공정 (c)에서 스터드 범프(12)의 선단부(17)에 부착된 땜납볼(14)과 땜납 기판(13)을 분리한다. 그 때, 반도체 부품(10)을 위로 이동시키거나 또는 땜납 기판(13)을 밑으로 이동시키는 것 중 어느 하나의 동작을 행하여도 좋다. 또한, 그 분리시에 땜납 기판(13)의 하측으로부터 공기 또는 질소 등의 기체를 분사하여 땜납볼(14)이 개구(15)로부터 빠져나가기 쉽게 하여도 좋다. 혹은, 땜납볼(14)과 땜납 기판(13) 사이를 부압으로 하여 땜납볼(14)의 하측에 압력차에 기인한 힘이 가해지도록 하여도 좋다.
공정 (d)에서, 반도체 부품(10)을 별도로 미리 준비된 회로 기판(20) 상으로 이동한다. 회로 기판(20)은 표면에 복수의 스터드 범프(12) 각각에 대응하는 접합 패드(21)를 갖는다. 이 때, 각 접합 패드(21)에, 대응하는 땜납볼(14)이 부착된 스터드 범프(12)가 가볍게 접촉하도록 양자를 위치 설정한다. 회로 기판(20)에는 유리 에폭시 기판, 폴리이미드와 같은 플렉스 기판, 세라믹 기판, 실리콘 기판 등의 각종 재료의 기판이 포함된다. 또한 회로 기판(20)에는, 통상의 인쇄 회로판, 절연층과 배선층을 교대로 적층한 다층 배선 기판 등의 각종 회로 기판이 포함된다. 접합 패드(21)는 기판 표면의 다른 배선층(도시하지 않음)과 접속되어 있다. 접합 패드(21)는 회로 기판의 표면에 대하여 오목부가 되는 형상을 가져도 좋다. 접합 패드(21)는 Cu, Au, Ag, Al, Sn 및 Ni 등을 함유한 그룹에서 선택된 1개 또는 2개 이상의 금속의 조합으로 이루어진다. 접합 패드(21)는 이들 금속으로 이루어진 다층 구조를 가져도 좋다.
공정 (e)에서, 땜납볼(14)을 용융시켜 스터드 범프(12) 각각과 대응하는 접합 패드(21)를 접합시킨다. 땜납볼(14)의 가열은 리플로우 노(爐) 또는 플립 칩 본더를 이용하여 행한다. 다른 가열 수단을 이용하여도 좋다. 가열 온도는 땜납 재료가 용융되고, 스터드 범프(12)와 접합 패드(21)가 접속 가능한 온도이면 좋다. 가열 온도는 사용하는 땜납 재료에 따라 결정된다. 땜납볼(14)은 용융된 후 땜납 접합(22)을 형성한다. 땜납 접합(22)은 접합 패드(21)의 표면 전체를 덮고 있지만, 접합 패드(21)보다도 외측으로 퍼지지는 않는다. 그 이유는 땜납볼(14)이 접합에 필요한 적절한 양으로 제어되고 있기 때문이다. 또한, 땜납볼(14)은 거의 균일하게 만들어져 있기 때문에, 접합 패드(21) 사이에서 땜납의 브릿지(쇼트)를 형성하는 일도 없다. 접합 패드(21)가 Cu로 이루어지고, 또한 땜납 재료가 Sn을 주로 하는 재료인 경우, 땜납의 용융은 1회뿐이므로, 도 1의 종래의 경우에 비하여 Sn-Cu 금속간 화합물의 형성을 경감할 수 있다.
본 발명에 대해서 도면을 참조하여 설명하였다. 그러나, 본 발명은 이들의 실시예로 한정되지 않는다. 본 발명의 취지를 일탈하지 않는 범위에서 어떠한 변형도 가능한 것은 당업자에 있어서는 분명할 것이다.

Claims (10)

  1. 회로 기판 상에 반도체 부품을 탑재하는 반도체 부품 탑재 방법으로서,
    표면에 복수의 스터드 범프가 형성된 반도체 부품을 준비하는 단계와,
    표면에 상기 복수의 스터드 범프 각각에 대응하는 고형 땜납이 배열된 땜납 기판을 준비하는 단계와,
    표면에 상기 복수의 스터드 범프 각각에 대응하는 접합 패드를 갖는 회로 기판을 준비하는 단계와,
    상기 복수의 스터드 범프 각각의 선단부에 땜납 기판 상의 대응하는 고형 땜납을 부착시키는 단계와,
    상기 스터드 범프의 선단부에 부착된 고형 땜납을 땜납 기판으로부터 분리하는 단계와,
    상기 스터드 범프 각각의 선단부에 부착된 고형 땜납과 대응하는 접합 패드를 접촉시키는 단계, 그리고
    상기 대응하는 접합 패드에 접촉된 고형 땜납을 용융시켜 스터드 범프 각각과 대응하는 접합 패드를 땜납 접합시키는 단계
    를 포함하는 반도체 부품 탑재 방법.
  2. 제1항에 있어서, 상기 복수의 스터드 범프 각각의 선단부에 대응하는 고형 땜납을 부착시키는 단계는 복수의 스터드 범프 각각과 대응하는 고형 땜납의 위치 가 맞춰지도록 반도체 부품과 땜납 기판을 가까이 하는 단계를 포함하는 것인 반도체 부품 탑재 방법.
  3. 제1항에 있어서, 상기 스터드 범프 각각의 선단부에 부착된 고형 땜납과 대응하는 접합 패드를 접촉시키는 단계는 복수의 스터드 범프 각각과 대응하는 접합 패드의 위치가 맞춰지도록 반도체 부품과 회로 기판을 가까이 하는 단계를 포함하는 것인 반도체 부품 탑재 방법.
  4. 제1항에 있어서, 상기 땜납 기판은 표면에 복수의 스터드 범프 각각에 대응하는 개구를 가지며, 이 개구에 고형 땜납이 수납되어 있는 것인 반도체 부품 탑재 방법.
  5. 제4항에 있어서, 상기 고형 땜납은 땜납볼로 이루어지는 반도체 부품 탑재 방법.
  6. 제2항에 있어서, 상기 복수의 스터드 범프 각각의 선단부에 대응하는 고형 땜납을 부착시키는 단계는 반도체 부품과 땜납 기판 중 어느 하나 또는 이들 양자를 가압하는 단계를 포함하는 것인 반도체 부품 탑재 방법.
  7. 제1항에 있어서, 상기 복수의 스터드 범프는 Au, Ag, Cu, Al 및 Ni를 함유하 는 그룹에서 선택된 1개 또는 2개 이상의 금속의 조합으로 이루어지는 것인 반도체 부품 탑재 방법.
  8. 제1항에 있어서, 상기 고형 땜납은 납이 함유되지 않은 땜납으로 이루어지는 것인 반도체 부품 탑재 방법.
  9. 제4항에 있어서, 상기 고형 땜납은 땜납 기판의 개구에 충전된 땜납으로 이루어지는 것인 반도체 부품 탑재 방법.
  10. 제1항 내지 제9항 중 어느 한 항의 반도체 부품 탑재 방법에 의해 회로 기판 상에 탑재된 반도체 부품을 갖는 반도체 장치.
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