KR100940115B1 - 반도체 소자의 게이트 형성 방법 - Google Patents
반도체 소자의 게이트 형성 방법 Download PDFInfo
- Publication number
- KR100940115B1 KR100940115B1 KR1020030013154A KR20030013154A KR100940115B1 KR 100940115 B1 KR100940115 B1 KR 100940115B1 KR 1020030013154 A KR1020030013154 A KR 1020030013154A KR 20030013154 A KR20030013154 A KR 20030013154A KR 100940115 B1 KR100940115 B1 KR 100940115B1
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- South Korea
- Prior art keywords
- hard mask
- gate
- film
- insulating film
- pattern
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 4
- 230000000087 stabilizing effect Effects 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (7)
- 반도체 기판 상에 게이트 산화막, 게이트 폴리실리콘막 및 하드 마스크용 절연막을 형성하는 단계;상기 하드 마스크용 절연막 상에 게이트 형성 영역을 정의하는 포토레지스트 패턴을 형성하는 단계;상기 포토레지스트 패턴을 식각마스크로 상기 하드 마스크용 절연막 내지 게이트 산화막을 차례로 식각하여 게이트 산화막 패턴, 게이트 폴리실리콘막 패턴 및 하드 마스크용 절연막 패턴을 형성하는 단계;상기 반도체 기판 상에 매립용 물질로 상기 게이트 산화막 패턴 내지 하드마스크용 절연막 패턴을 매립하는 단계;상기 매립용 물질을 일부 제거하여 상기 하드 마스크용 절연막 패턴의 상부를 노출시키는 단계;상기 노출된 하드 마스크용 절연막 패턴을 제거하는 단계; 및상기 매립용 물질을 제거하여 상기 게이트 산화막 패턴 및 게이트 폴리실리콘막 패턴으로 이루어진 게이트 패턴을 형성하는 단계를 포함하는 반도체 소자의 게이트 형성 방법.
- 제 1항에 있어서,상기 하드마스크용 절연막은 산화막 또는 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.
- 제2항에 있어서,상기 하드 마스크용 절연막을 질화막으로 형성하고 매립용 물질은 SOG 방식을 이용한 산화막으로 증착하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.
- 제 2항에 있어서,상기 하드 마스크용 절연막을 산화막으로 형성하고 매립용 물질은 포토레지스트를 이용하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.
- 제 4항에 있어서,상기 하드 마스크용 산화막은 C2F6와 Ar 혼합 가스 또는 C4F8와 Ar을 혼합한 가스를 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.
- 제 3항에 있어서,CMP 공정을 진행하여 하드 마스크용 절연막 상부를 노출시키는 것을 특징으 로 하는 반도체 소자의 게이트 형성 방법.
- 제 4항에 있어서,O2 또는 O2/N2 가스를 이용하여 하드마스크용 절연막의 상부를 노출시키는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.
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KR1020030013154A KR100940115B1 (ko) | 2003-03-03 | 2003-03-03 | 반도체 소자의 게이트 형성 방법 |
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KR1020030013154A KR100940115B1 (ko) | 2003-03-03 | 2003-03-03 | 반도체 소자의 게이트 형성 방법 |
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KR20040078292A KR20040078292A (ko) | 2004-09-10 |
KR100940115B1 true KR100940115B1 (ko) | 2010-02-02 |
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KR1020030013154A KR100940115B1 (ko) | 2003-03-03 | 2003-03-03 | 반도체 소자의 게이트 형성 방법 |
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20030002382A (ko) * | 2001-06-29 | 2003-01-09 | 삼성전자 주식회사 | 반도체 장치의 게이트 전극 형성 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법 |
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20030002382A (ko) * | 2001-06-29 | 2003-01-09 | 삼성전자 주식회사 | 반도체 장치의 게이트 전극 형성 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법 |
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