KR100914964B1 - 신호 인코더 및 신호 디코더 - Google Patents

신호 인코더 및 신호 디코더

Info

Publication number
KR100914964B1
KR100914964B1 KR1020070086961A KR20070086961A KR100914964B1 KR 100914964 B1 KR100914964 B1 KR 100914964B1 KR 1020070086961 A KR1020070086961 A KR 1020070086961A KR 20070086961 A KR20070086961 A KR 20070086961A KR 100914964 B1 KR100914964 B1 KR 100914964B1
Authority
KR
South Korea
Prior art keywords
signal
output
output terminal
receiving
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020070086961A
Other languages
English (en)
Korean (ko)
Other versions
KR20080112893A (ko
Inventor
치-창 후앙
융-솅 웨이
멩-시우 웨이
Original Assignee
매크로블록 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매크로블록 인코포레이티드 filed Critical 매크로블록 인코포레이티드
Publication of KR20080112893A publication Critical patent/KR20080112893A/ko
Application granted granted Critical
Publication of KR100914964B1 publication Critical patent/KR100914964B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)
KR1020070086961A 2007-06-22 2007-08-29 신호 인코더 및 신호 디코더 Expired - Fee Related KR100914964B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW096122505A TW200901636A (en) 2007-06-22 2007-06-22 Signal encoder and signal decoder
TW096122505 2007-06-22

Publications (2)

Publication Number Publication Date
KR20080112893A KR20080112893A (ko) 2008-12-26
KR100914964B1 true KR100914964B1 (ko) 2009-09-02

Family

ID=40135850

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070086961A Expired - Fee Related KR100914964B1 (ko) 2007-06-22 2007-08-29 신호 인코더 및 신호 디코더

Country Status (4)

Country Link
US (1) US7545178B2 (enExample)
JP (1) JP2009005324A (enExample)
KR (1) KR100914964B1 (enExample)
TW (1) TW200901636A (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI446715B (zh) * 2011-01-03 2014-07-21 Etron Technology Inc 具有雙輸入緩衝器切換功能的輸入緩衝系統及其方法
US9537644B2 (en) 2012-02-23 2017-01-03 Lattice Semiconductor Corporation Transmitting multiple differential signals over a reduced number of physical channels
US9230505B2 (en) * 2013-02-25 2016-01-05 Lattice Semiconductor Corporation Apparatus, system and method for providing clock and data signaling
US9871516B2 (en) 2014-06-04 2018-01-16 Lattice Semiconductor Corporation Transmitting apparatus with source termination
US10348418B1 (en) 2014-07-22 2019-07-09 Esker Technologies, LLC Transient and spurious signal filter
US10417143B2 (en) * 2015-10-08 2019-09-17 Esker Technologies, LLC Apparatus and method for sending power over synchronous serial communication wiring
US9490967B1 (en) * 2015-12-22 2016-11-08 Texas Instruments Incorporated Communication system and method
US10560154B2 (en) 2016-07-11 2020-02-11 Esker Technologies, LLC Power line signal coupler
US10128906B2 (en) 2016-07-11 2018-11-13 Esker Technologies, LLC Power line signal coupler
DE102020205278A1 (de) * 2020-04-27 2021-10-28 Robert Bosch Gesellschaft mit beschränkter Haftung Kommunikationssteuereinrichtung und Sende-/Empfangseinrichtung für eine Teilnehmerstation eines seriellen Bussystems und Verfahren zur Kommunikation in einem seriellen Bussystem
CN113108816B (zh) * 2021-04-16 2024-06-21 深圳市立三机电有限公司 一种多路信号共用一传输通道的磁电编码器电路
CN117220695B (zh) * 2023-09-18 2024-06-07 新港海岸(北京)科技有限公司 一种数据传输电路及方法
KR102822177B1 (ko) * 2023-11-17 2025-06-17 한국전기연구원 다중 신호 전송을 위한 신호 절연회로

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR870002732A (ko) * 1984-08-30 1987-04-06 야마모도 다꾸마 차동 코딩 회로
KR20050086719A (ko) * 2002-11-22 2005-08-30 코닌클리케 필립스 일렉트로닉스 엔.브이. 전기 영동 디스플레이 패널

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3924186A (en) * 1974-02-07 1975-12-02 Ncr Co Staggered quadriphase differential encoder and decoder
US20080054944A1 (en) * 2006-08-30 2008-03-06 Micron Technology, Inc. Method and circuit for producing symmetrical output signals tolerant to input timing skew, output delay/slewrate-mismatch, and complementary device mismatch
US7929640B2 (en) * 2006-11-15 2011-04-19 Northrop Grumman Systems Corporation High speed differential encoder and interleaver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR870002732A (ko) * 1984-08-30 1987-04-06 야마모도 다꾸마 차동 코딩 회로
KR20050086719A (ko) * 2002-11-22 2005-08-30 코닌클리케 필립스 일렉트로닉스 엔.브이. 전기 영동 디스플레이 패널

Also Published As

Publication number Publication date
US20080315920A1 (en) 2008-12-25
TW200901636A (en) 2009-01-01
KR20080112893A (ko) 2008-12-26
JP2009005324A (ja) 2009-01-08
TWI314399B (enExample) 2009-09-01
US7545178B2 (en) 2009-06-09

Similar Documents

Publication Publication Date Title
KR100914964B1 (ko) 신호 인코더 및 신호 디코더
US9928208B2 (en) Methods to send extra information in-band on inter-integrated circuit (I2C) bus
JP6461018B2 (ja) 状態周期ごとに状態を変えるとともにデータのレーン間スキューおよびデータ状態遷移グリッチに
CN101882095B (zh) 信号处理装置和纠错方法
KR102203390B1 (ko) 싱글 엔디드 3-레벨 펄스 진폭 변조 시그널링을 위한 장치 및 방법
JP2012533264A (ja) 組み合わせデータマスクおよびデータバス反転を用いたデータ符号化
WO2013001631A1 (ja) 伝送装置、伝送回路、伝送システムおよび伝送装置の制御方法
CN101257464B (zh) 用于差分信号传输接收器的电路和方法
CN105071912A (zh) 一种基于双电平的二进制数字基带码元通信方法
US7492287B2 (en) Two-bit tri-level forced transition encoding
US10637497B2 (en) Receiver, sender, method for retrieving an additional datum from a signal and method for transmitting a datum and an additional datum in a signal
CN105827351B (zh) 转态强制编码接收器
JPWO2007037312A1 (ja) クロック再生装置及び方法
US9559872B2 (en) Signal transmission system
US6944804B1 (en) System and method for measuring pseudo pixel error rate
CN106998309A (zh) 转态强制编码接收器及用于转态强制编码接收器中接收方法
CN101340422A (zh) 信号编码器与信号译码器
JP2005286662A (ja) データ送信装置、データ送受信システム、データ伝送方法
US7660364B2 (en) Method of transmitting serial bit-stream and electronic transmitter for transmitting a serial bit-stream
US11454943B2 (en) Serial isolation communication method, device and system
KR100226022B1 (ko) 등화기 동작 완료 상태 표시 시스템
JP2001126402A (ja) デジタル信号処理方法及びデジタル信号処理装置
CN115580307A (zh) 曼彻斯特解码方法和装置以及应用其的电池管理系统
CN103986547B (zh) 移动产业处理器接口的信号接收方法及信号接收装置
JP2005354431A (ja) 順序論理回路

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20120802

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20130722

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20140722

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20150730

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20160826

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20160826