KR100843499B1 - 소자 스케일링을 위한 수직 패스 트랜지스터 디램 셀설계에서의 자기정렬 드레인/채널 접합 - Google Patents
소자 스케일링을 위한 수직 패스 트랜지스터 디램 셀설계에서의 자기정렬 드레인/채널 접합 Download PDFInfo
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Abstract
Description
Claims (20)
- 반도체 기판에 형성된 측벽을 가진 트렌치 및 표면(상기 반도체 기판은 도펀트로 도핑됨), 상기 기판의 표면에 카운터도핑된 드레인 영역 및 상기 측벽과 나란한 채널(상기 드레인 영역은 최상부 레벨 및 저부 레벨을 가짐), 상기 채널 아래에 상기 측벽과 병치하여 상기 기판에 형성된 카운터도핑된 소스 영역, 상기 트렌치의 측벽 상에 형성된 게이트 산화물 층, 및 상기 트렌치에 형성된 게이트 컨덕터를 포함하는 상기 반도체 기판 내의 트렌치 수직 트랜지스터(trench vertical transistor)를 형성하는 방법으로서,상기 반도체 기판의 상기 표면 아래로 상기 게이트 컨덕터를 리세싱(recessing)하는 단계와,상기 드레인 영역의 위치 아래의 상기 채널로, 수직 방향에 대하여 θ+δ의 각도로 카운터도펀트의 경사진 이온 주입(angled ion implantation)을 수행하는 단계와,상기 드레인 영역의 위치 아래의 상기 채널로, 수직 방향에 대하여 θ의 각도로 도펀트의 경사진 이온 주입을 수행하는 단계를 포함하되,상기 θ 및δ는 양의 값을 갖는 트렌치 수직 트랜지스터 형성 방법.
- 제1항에 있어서, 상기 게이트 컨덕터의 상기 리세싱은 상기 드레인 영역의 저부 레벨 아래에 도달하는 것인 트렌치 수직 트랜지스터 형성 방법.
- 삭제
- 제1항에 있어서, 상기 카운터도펀트는 비소 및 인으로 구성된 그룹으로부터 선택되는 것인 트렌치 수직 트랜지스터 형성 방법.
- 청구항 5은(는) 설정등록료 납부시 포기되었습니다.제1항에 있어서, 상기 카운터도펀트는 10 keV의 에너지에서 주입되는 비소 이온을 포함하는 것인 트렌치 수직 트랜지스터 형성 방법.
- 삭제
- 청구항 7은(는) 설정등록료 납부시 포기되었습니다.제1항에 있어서,상기 트렌치는 딥 트렌치 커패시터를 포함하고,상기 게이트 컨덕터의 상기 리세싱은 상기 드레인 영역의 상기 저부 레벨 아래에 도달하는 것인 트렌치 수직 트랜지스터 형성 방법.
- 제1항, 제5항, 제7항 중 어느 한 항에 있어서, 상기 각 θ는 7˚이고, θ+δ는 30˚인 것인 트렌치 수직 트랜지스터 형성 방법.
- 반도체 기판 내에 딥 트렌치 수직 트랜지스터를 형성하는 방법으로서, 반도체 기판에 형성된 측벽을 가지는 트렌치 및 표면 - 딥 트렌치는 노드, 스트랩, 칼라(collar), 및 상기 딥 트렌치를 라이닝(lining)하는 노드 절연체를 포함함 - , 및 상기 딥 트렌치를 둘러 상기 반도체 기판에 형성된 매립 플레이트(buried plate) - 상기 반도체 기판은 도펀트로 도핑됨 - , 상기 기판의 표면에서 카운터도핑된 비트라인 확산 영역 및 상기 측벽과 나란한 채널 - 상기 비트라인 확산 영역은 최상부 레벨 및 저부 레벨을 가짐 - , 상기 채널 아래 상기 측벽과 병치되어 상기 기판에 형성된 카운터도핑된 소스 영역, 상기 트렌치의 측벽에 형성된 게이트 산화물 층, 및 상기 트렌치에 형성된 게이트 컨덕터를 포함하며, 상기 방법은:상기 반도체 기판의 상기 표면 아래로 상기 게이트 컨덕터를 리세싱하는 단계;드레인 영역의 위치 아래의 상기 채널로, 수직 방향에 대하여 θ+δ의 각도로 카운터도펀트의 경사진 이온 주입을 수행하는 단계; 및상기 비트라인 확산 영역 아래의 상기 채널로, 수직 방향에 대하여 θ의 각도로 경사진 이온 주입을 수행하는 단계를 포함하되,상기 θ 및 δ는 양의 값을 갖는 딥 트렌치 수직 트랜지스터 형성 방법.
- 제9항에 있어서, 상기 게이트 컨덕터의 상기 리세싱은 상기 비트라인 확산 영역의 상기 저부 레벨 아래에 도달하는 것인 딥 트렌치 수직 트랜지스터 형성 방 법.
- 삭제
- 제9항에 있어서, 상기 카운터도펀트는 비소 및 인으로 구성된 그룹으로부터 선택되는 것인 딥 트렌치 수직 트랜지스터 형성 방법.
- 청구항 13은(는) 설정등록료 납부시 포기되었습니다.제9항에 있어서, 상기 카운터도펀트는 10 keV의 에너지에서 주입된 비소 이온을 포함하는 것인 딥 트렌치 수직 트랜지스터 형성 방법.
- 삭제
- 반도체 기판의 표면, 상기 반도체 기판에 형성된 측벽을 가진 딥 트렌치, 상기 반도체 기판의 표면상에서 측벽과 병치되는 비트라인 확산 영역을 포함하는 반도체 기판 내의 딥 트렌치 수직 트랜지스터를 형성하는 방법으로서,도핑된 반도체 기판에 최상부 및 저부를 가지는 딥 트렌치를 형성하는 단계와,상기 딥 트렌치의 상기 저부를 둘러 상기 기판에 카운터도핑된 매립 플레이트를 형성하는 단계와,상기 딥 트렌치의 내부벽 상에 등각 박막으로서 스토리지 노드 절연층을 형성하는 단계와,카운터도핑된 초기(initial) 스토리지 노드 컨덕터로 상기 딥 트렌치를 충전하는 단계와,상기 초기 스토리지 노드 컨덕터를 리세싱하는 단계와,상기 딥 트렌치의 노출된 내부 벽 상에 등각 막으로서 절연 칼라를 형성하는 단계- 상기 절연 칼라는 상기 딥 트렌치의 상기 최상부 아래로 리세싱됨- ,위로는 카운터도핑되며 상기 초기 스토리지 노드 컨덕터와 접촉하는 보충(complementary) 스토리지 노드 컨덕터로 상기 딥 트렌치를 충전하는 단계와,상기 딥 트렌치에서 매립된 스트랩 레벨로 상기 보충 스토리지 노드 컨덕터를 리세싱하는 단계와,상기 보충 스토리지 노드 컨덕터로부터 상기 기판으로 도펀트를 확산시키는 것에 의해 카운터도핑된 매립 스트랩 카운터도핑된 과확산(counterdoped buried strap conterdoped outdiffusion)을 형성하는 단계와,상기 보충 스토리지 노드 컨덕터 위에 트렌치 최상부 산화물 층을 형성하는 단계와.상기 딥 트렌치의 노출된 내부벽과 등각인 게이트 산화물 층을 형성하는 단계와,상기 트렌치 최상부 산화물 층 위에서 상기 딥 트렌치에 게이트 컨덕터를 형성하는 단계와,상기 비트라인 확산 영역의 저부 표면 아래에서 상기 게이트 컨덕터를 리세싱하는 단계와,상기 비트라인 확산 영역의 위치 아래의 채널로, 수직 방향에 대하여 θ+δ의 각도로 카운터도펀트의 경사진 이온 주입을 수행하는 단계와,드레인 영역의 위치 아래의 상기 채널로, 수직 방향에 대하여 θ의 각도로 도펀트의 경사진 이온 주입을 수행하는 단계를 포함하되,상기 θ 및 δ는 양의 값을 갖는 딥 트렌치 수직 트랜지스터 형성 방법.
- 삭제
- 제15항에 있어서, 상기 카운터도펀트는 비소 및 인으로 구성된 그룹으로부터 선택된 것인 딥 트렌치 수직 트랜지스터 형성 방법.
- 삭제
- 청구항 19은(는) 설정등록료 납부시 포기되었습니다.제17항에 있어서, 상기 카운터도펀트는 10 keV의 에너지에서 주입된 비소 이온을 포함하는 것인 딥 트렌치 수직 트랜지스터 형성 방법.
- 제9항, 제12항, 제15항, 제17항, 제19항 중 어느 한 항에 있어서, 상기 각 θ는 7˚이고, θ+δ는 30˚인 것인 딥 트렌치 수직 트랜지스터 형성 방법.
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US10/604,731 | 2003-08-13 | ||
US10/604,731 US6930004B2 (en) | 2003-08-13 | 2003-08-13 | Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling |
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US (1) | US6930004B2 (ko) |
EP (1) | EP1661176B1 (ko) |
JP (1) | JP4524285B2 (ko) |
KR (1) | KR100843499B1 (ko) |
CN (1) | CN100375270C (ko) |
AT (1) | ATE539448T1 (ko) |
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TW200512886A (en) * | 2003-09-18 | 2005-04-01 | Nanya Technology Corp | Method for forming isolation zone of vertical dynamic random access memory cell |
US6979613B1 (en) * | 2003-11-16 | 2005-12-27 | Nanya Technology Corp. | Method for fabricating a trench capacitor of DRAM |
US20070275532A1 (en) * | 2006-05-24 | 2007-11-29 | International Business Machines Corporation | Optimized deep source/drain junctions with thin poly gate in a field effect transistor |
TWI334222B (en) * | 2007-05-24 | 2010-12-01 | Nanya Technology Corp | Dynamic random access memory and manufacturing method thereof |
US7838925B2 (en) * | 2008-07-15 | 2010-11-23 | Qimonda Ag | Integrated circuit including a vertical transistor and method |
KR101532366B1 (ko) * | 2009-02-25 | 2015-07-01 | 삼성전자주식회사 | 반도체 기억 소자 |
CN102024700B (zh) * | 2009-09-17 | 2012-09-26 | 北大方正集团有限公司 | 沟槽型双扩散金属氧化物半导体晶体管的制作方法 |
KR101164955B1 (ko) | 2009-09-30 | 2012-07-12 | 에스케이하이닉스 주식회사 | 단일 측벽 콘택을 갖는 반도체장치 및 제조 방법 |
US8298908B2 (en) * | 2010-02-11 | 2012-10-30 | International Business Machines Corporation | Structure and method for forming isolation and buried plate for trench capacitor |
US9761728B1 (en) | 2016-05-25 | 2017-09-12 | International Business Machines Corporation | Self-aligned source/drain junction for vertical field-effect transistor (FET) and method of forming the same |
CN117858496B (zh) * | 2024-03-07 | 2024-06-07 | 合肥晶合集成电路股份有限公司 | 静态随机存取存储器单元的制备方法 |
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US5548148A (en) * | 1994-04-15 | 1996-08-20 | International Business Machines Corporation | MOS channel device with counterdoping of ion implant for reduced substrate sensitivity |
US20020096219A1 (en) * | 2000-11-10 | 2002-07-25 | Rosewood Equipment Company | Utility conservation control methodology within a fluid pumping system |
US6414347B1 (en) * | 2001-01-10 | 2002-07-02 | International Business Machines Corporation | Vertical MOSFET |
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JP2008502123A (ja) | 2008-01-24 |
EP1661176A4 (en) | 2010-03-24 |
TW200518273A (en) | 2005-06-01 |
CN1836322A (zh) | 2006-09-20 |
EP1661176B1 (en) | 2011-12-28 |
US20050037561A1 (en) | 2005-02-17 |
JP4524285B2 (ja) | 2010-08-11 |
US6930004B2 (en) | 2005-08-16 |
WO2005020318A1 (en) | 2005-03-03 |
TWI304639B (en) | 2008-12-21 |
KR20060040683A (ko) | 2006-05-10 |
CN100375270C (zh) | 2008-03-12 |
EP1661176A1 (en) | 2006-05-31 |
ATE539448T1 (de) | 2012-01-15 |
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