KR100837812B1 - 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법 - Google Patents

반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법 Download PDF

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Publication number
KR100837812B1
KR100837812B1 KR1020060123574A KR20060123574A KR100837812B1 KR 100837812 B1 KR100837812 B1 KR 100837812B1 KR 1020060123574 A KR1020060123574 A KR 1020060123574A KR 20060123574 A KR20060123574 A KR 20060123574A KR 100837812 B1 KR100837812 B1 KR 100837812B1
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South Korea
Prior art keywords
carry
dbi
data
output
signal
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Expired - Fee Related
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KR1020060123574A
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English (en)
Korean (ko)
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KR20080051839A (ko
Inventor
신범주
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주식회사 하이닉스반도체
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Priority to KR1020060123574A priority Critical patent/KR100837812B1/ko
Priority to US11/878,091 priority patent/US8010586B2/en
Priority to JP2007215679A priority patent/JP2008146807A/ja
Publication of KR20080051839A publication Critical patent/KR20080051839A/ko
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Publication of KR100837812B1 publication Critical patent/KR100837812B1/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
KR1020060123574A 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법 Expired - Fee Related KR100837812B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020060123574A KR100837812B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법
US11/878,091 US8010586B2 (en) 2006-12-07 2007-07-20 Apparatus and method of generating DBI signal in semiconductor integrated circuit
JP2007215679A JP2008146807A (ja) 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060123574A KR100837812B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법

Publications (2)

Publication Number Publication Date
KR20080051839A KR20080051839A (ko) 2008-06-11
KR100837812B1 true KR100837812B1 (ko) 2008-06-13

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KR1020060123574A Expired - Fee Related KR100837812B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법

Country Status (3)

Country Link
US (1) US8010586B2 (enExample)
JP (1) JP2008146807A (enExample)
KR (1) KR100837812B1 (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121918A1 (en) 2000-10-04 2002-09-05 Alani Alaa F. Reducing the effect of simultaneous switching noise
KR100578219B1 (ko) 2004-12-30 2006-05-12 주식회사 하이닉스반도체 온-칩 데이터 전송 제어장치 및 그 제어방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100258870B1 (ko) * 1997-12-24 2000-06-15 김영환 2진 비교회로
JP2001034457A (ja) * 1999-07-19 2001-02-09 Toyo Commun Equip Co Ltd 加減算回路
JP2001325093A (ja) * 2000-05-12 2001-11-22 Mitsubishi Electric Corp １ビット比較全加算器、ｎビット比較全加算器、半導体演算装置、およびレイアウトライブラリ
US6795839B2 (en) * 2000-11-30 2004-09-21 Stmicroelectronics, Inc. Method and device for computing the number of bits set to one in an arbitrary length word
US6665691B2 (en) * 2000-12-08 2003-12-16 Stmicroelectronics, Inc. Circuit for detecting numbers equal to a power of two on a data bus
US6729168B2 (en) * 2000-12-08 2004-05-04 Stmicroelectronics, Inc. Circuit for determining the number of logical one values on a data bus
US6898648B2 (en) * 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
JP4319533B2 (ja) * 2003-12-04 2009-08-26 富士通株式会社 ポピュレーションカウント回路
US7411840B2 (en) * 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
KR100643498B1 (ko) * 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020121918A1 (en) 2000-10-04 2002-09-05 Alani Alaa F. Reducing the effect of simultaneous switching noise
KR100578219B1 (ko) 2004-12-30 2006-05-12 주식회사 하이닉스반도체 온-칩 데이터 전송 제어장치 및 그 제어방법

Also Published As

Publication number Publication date
US8010586B2 (en) 2011-08-30
US20080136462A1 (en) 2008-06-12
JP2008146807A (ja) 2008-06-26
KR20080051839A (ko) 2008-06-11

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