JP2008146807A - 半導体集積回路のｄｂｉ信号生成装置および方法 - Google Patents

半導体集積回路のｄｂｉ信号生成装置および方法 Download PDF

Info

Publication number
JP2008146807A
JP2008146807A JP2007215679A JP2007215679A JP2008146807A JP 2008146807 A JP2008146807 A JP 2008146807A JP 2007215679 A JP2007215679 A JP 2007215679A JP 2007215679 A JP2007215679 A JP 2007215679A JP 2008146807 A JP2008146807 A JP 2008146807A
Authority
JP
Japan
Prior art keywords
dbi
full adder
adder
carry
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2007215679A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008146807A5 (enExample
Inventor
Beom Ju Shin
範 柱 辛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2008146807A publication Critical patent/JP2008146807A/ja
Publication of JP2008146807A5 publication Critical patent/JP2008146807A5/ja
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
JP2007215679A 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法 Ceased JP2008146807A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060123574A KR100837812B1 (ko) 2006-12-07 2006-12-07 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법

Publications (2)

Publication Number Publication Date
JP2008146807A true JP2008146807A (ja) 2008-06-26
JP2008146807A5 JP2008146807A5 (enExample) 2010-09-30

Family

ID=39497223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007215679A Ceased JP2008146807A (ja) 2006-12-07 2007-08-22 半導体集積回路のｄｂｉ信号生成装置および方法

Country Status (3)

Country Link
US (1) US8010586B2 (enExample)
JP (1) JP2008146807A (enExample)
KR (1) KR100837812B1 (enExample)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11249870A (ja) * 1997-12-24 1999-09-17 Lg Semicon Co Ltd 二進比較回路
JP2001034457A (ja) * 1999-07-19 2001-02-09 Toyo Commun Equip Co Ltd 加減算回路
JP2001325093A (ja) * 2000-05-12 2001-11-22 Mitsubishi Electric Corp １ビット比較全加算器、ｎビット比較全加算器、半導体演算装置、およびレイアウトライブラリ
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
JP2005165793A (ja) * 2003-12-04 2005-06-23 Fujitsu Ltd ポピュレーションカウント回路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0024226D0 (en) 2000-10-04 2000-11-15 Lsi Logic Corp Improvements in or relating to the reduction of simultaneous switching noise in integrated circuits
US6795839B2 (en) * 2000-11-30 2004-09-21 Stmicroelectronics, Inc. Method and device for computing the number of bits set to one in an arbitrary length word
US6665691B2 (en) * 2000-12-08 2003-12-16 Stmicroelectronics, Inc. Circuit for detecting numbers equal to a power of two on a data bus
US6729168B2 (en) * 2000-12-08 2004-05-04 Stmicroelectronics, Inc. Circuit for determining the number of logical one values on a data bus
US6898648B2 (en) * 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US7411840B2 (en) * 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
KR100578219B1 (ko) 2004-12-30 2006-05-12 주식회사 하이닉스반도체 온-칩 데이터 전송 제어장치 및 그 제어방법
KR100643498B1 (ko) * 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11249870A (ja) * 1997-12-24 1999-09-17 Lg Semicon Co Ltd 二進比較回路
JP2001034457A (ja) * 1999-07-19 2001-02-09 Toyo Commun Equip Co Ltd 加減算回路
JP2001325093A (ja) * 2000-05-12 2001-11-22 Mitsubishi Electric Corp １ビット比較全加算器、ｎビット比較全加算器、半導体演算装置、およびレイアウトライブラリ
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
JP2005165793A (ja) * 2003-12-04 2005-06-23 Fujitsu Ltd ポピュレーションカウント回路

Also Published As

Publication number Publication date
US8010586B2 (en) 2011-08-30
US20080136462A1 (en) 2008-06-12
KR20080051839A (ko) 2008-06-11
KR100837812B1 (ko) 2008-06-13

Similar Documents

Publication Publication Date Title
JP5254377B2 (ja) 回路デバイス
US8373483B2 (en) Low-clock-energy, fully-static latch circuit
KR100974223B1 (ko) 데이터 버스 인버전 기능을 갖는 반도체 집적회로
TW201019665A (en) Data transmitting system
KR20150038792A (ko) 반도체 메모리 장치 및 이의 데이터 입출력 방법
JP5124209B2 (ja) 半導体集積回路のｄｂｉ信号生成装置および方法
KR20130097574A (ko) 커맨드디코더
JP2006191567A (ja) オンチップデータ伝送制御装置及びその制御方法
CN102956272B (zh) 测试模式信号系统以及传送测试模式信号的方法
CN101645296B (zh) 半导体集成电路
US10756736B2 (en) Fused voltage level shifting latch
US6424179B1 (en) Logic unit and integrated circuit for clearing interrupts
EP3926630B1 (en) Read operation circuit, semiconductor memory and read operation method
JP4956295B2 (ja) 半導体記憶装置
JP5918192B2 (ja) Ｐｌｃシステムでのデータ処理装置及びその方法
JP2008146625A5 (enExample)
KR100837812B1 (ko) 반도체 집적 회로의 ｄｂｉ 신호 생성 장치 및 방법
TWI237347B (en) Integrated circuit device and method for applying different types of signals to internal circuit via one pin
KR100972866B1 (ko) 데이터 출력 제어 장치
KR20130105213A (ko) 노이즈를 감소시킬 수 있는 출력 구동 회로 및 이를 포함하는 반도체 메모리 장치
KR101904142B1 (ko) 테스트 모드 신호 생성 회로
KR100945939B1 (ko) 컬럼 어드레스 전달회로 및 이를 이용한 반도체 메모리장치
US6144228A (en) Generalized push-pull cascode logic technique
JP2004242292A (ja) ゼロ検出で速い計算が可能なインクリメンタ及びその方法
KR20080113733A (ko) 디코더

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100810

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100810

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101013

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120927

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121226

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130314

A045 Written measure of dismissal of application [lapsed due to lack of payment]

Free format text: JAPANESE INTERMEDIATE CODE: A045

Effective date: 20130808